A Single-Chip Quad-Band GSM/GPRS Transceiver in 0.18µm Standard CMOS Berkäna Wireless Inc. Campbell, California
A Single-Chip Quad-Band GSM/GPRS Transceiver in
0.18µm Standard CMOS
Berkäna Wireless Inc.Campbell, California
Desired Features of Commercial Radios
• Low Cost• Small Form Factor • Long Range
DigitalBaseband
(BB)
PFD
CMOS Front-end Transceiver
Presentation Outline
• GSM/GPRS Implementation Challenges
• Transceiver Architectural Tradeoffs
• CMOS Quad-Band GSM/GPRS Transceiver
• Test Results
• Conclusions
Key Receiver Specifications
• Range of the Mobile => Sensitivity < -102dBm• Near-Far Problem => Large Dynamic Range• Presence of Nearby Users => IIP3 > -17dBm
f C- 6
00kH
z
f C- 1
.6MHz
f C- 3
MHz-33dBm
-23dBm
-99dBm
AM Blockers
fCDesired Signal
76dB-43dBm
freq
GSM 900 Blocking Profile
Key Transmitter SpecificationsTX Noise in RX Band
Transmit Band
20MHzSpacing
ReceiveBand
< -162dBc/Hz
freq
Requirement
freqfC
- 60dBc
400 kHz
Modulation Mask
• Receive Band Noise at 20MHz offset, PN < -162dBc/Hz• Modulation Mask at 400kHz offset requires high
linearity and low phase noise• Modulation Accuracy of: < 5oϕRMS
+33dBm
RX Direct ConversionRF
Filter
Q LOI LO
Mixer
ADC
I BB
Q BB
Properties of Direct Conversion
Low frequency signal facilitating programmable filters
Problematic 1/f, DC offset and IP2 interference
Low IF ReceiverRF
Filter
Q LOI LO
Mixer
ADC
I BB
Q BB
Properties of Low-IF Receivers
Less susceptible to low frequency interference
Image rejection must be addressed
Leverage narrowband signal to facilitate integration
Direct Conversion Transmitters
Q LOI LO
Mixer / Modulator
I BB
Q BB
PowerAmp
RFFilter
RFFilter
Properties of Direct Conversion TransmittersSingle conversion eliminates IF filter
Requires Pre-PA filter for harmonic rejection
Wideband modulator noise demands filtering
TX Offset Phase-Locked LoopPowerAmp
LoopFilter
LO2
PFD/CP
VCOI BB
Q BB
Q LO1I LO1
Modulator
PLL frequency translates phase modulated signal
PLL transfer function filters mixer spurs and noise
More design complexity compared to Direct Conversion
Leverage narrowband signal to enable integration
Presentation Outline
• GSM/GPRS Implementation Challenges
• Transceiver Architectural Tradeoffs
• CMOS Quad-Band GSM/GPRS Transceiver
• Test Results
• Conclusion
Quad-Band GSM/GPRS Transceiver
GSM LNA
DCS LNA
PCS LNA
T/R Switch
RF Filters4
2
EGSM LNA
TX INBB IHR Filter
Q LOI LO
ModulatorLoopFilter
PFD
VCO
LoopFilter
PFD
VCO
N/(N+1)
I/QMixers
RHighband Pre-PA Amp
Lowband Pre-PA Amp
2
I/QMixers
ComplexIF Filter
IF LOPGA
Q
I Low-IFDiscrete-Time
ProcessingQ
I
Q
I
Paper17.8
M
Σ∆
PAM
TX INBB Q
TCXO
RX OUTBB I
RX OUTBB Q
PLL Phase Noise vs. Settling Time
-150
-140
-130
0 10 20 30 40
Phas
e noi
se @
3MHz
0.00E+00
2.00E-04
4.00E-04
6.00E-04
8.00E-04
Settl
ing
time (
sec)
pn @ 3MHz
t_settle_prechg_off
Phas
e N
oise
@ 3
MH
z(d
Bc/
Hz)
200
400
600
800
PLL
Settl
ing
Tim
e ( µ
s)
C2
-146 dBc/Hz
PFD
VCORef.Osc.
N/N+1
TX & RX LO Input
Loop Filter
C1R1
C2
CPVC
Typical PLL Settling CharacteristicsVC Range of VC
(Post VCO Calibration)
• VCO calibration minimizes control voltage range• Small charge pump current
~Vdd / 2
time
TSlew =C2*Vdd/2ICP
Principle of Fast Charging PLLRange of VC
(Post VCO Calibration)VCVC
~Vdd / 2
time
TSlew =C2*Vdd/2IBoost
• VCO calibration minimizes control voltage range• Small charge pump current
PLL Fast-Charge Amplifier
Class AB Amplifier
pc
Vi
pc
pcpc
VoM Z
C2
IBoost 15mA
IBoost
≥
VCOCPVC
R1 C1
C2
pcVo= VcVdd/2
Vi
pc
Receiver RF and IF
FilterPGA
1st Stage
FilterPGA
2nd Stage
FilterPGA
3rd Stage
FilterPGA
4th Stage
FilterPGA
5th Stage
LNA
MixerI Channel IF Output
Q Channel IF Output
• Fully differential signal path• Complex Butterworth filter response• Receive gain is 100dB in 2dB steps
High-Band RF Front EndBand Sharing LNA Loads Folded Mixer
IND- INP+
LOQ
VB3
LOI+LOI-
Q MIXEROUTPUT
VB1 VB2I MIXEROUTPUT
DCS Band PCS Band
INP-IND+
Receive IF Filter and PGA StageC2
C2 RC
DC Offset Cancellation Algorithm
R2
R2
I Channel Input
Q ChannelInput
I ChannelOutput
Next FilterStage
Next FilterStage
RC
RC
RC
C2
C2
R2
R2
R1
DC Offset Cancellation Algorithm
Q Channel Output
R1
R1
R1
Transmit Output Driver
• Rail-to-Rail Signal Path• Ko Push-Pull Driver• PO = iop
2*RLOAD/2• Minimal Area
Low BandAmplifier
ChipPad
LevelShifter
Feedback Path of OPLL
High BandAmplifier
Resd
ChipPad Cac_couple
2Resd Rload
Cac_couple
RLOAD
Mp
Mn
Vdd
Cac_couple
TX OPLLOn-chip VCO
Rload
Principle of the Ko Push-Pull AmpHigh Input State
Vdd
Low Input State
RLOAD(Effective)
VOiodp
iodn
Cac_couple Zo
tronn ronp ~Zout
RLOAD(Effective)
Vo
Cac_couple
Vi
t
iodn
Mp VOVi
t
Vdd t
ViMn
Presentation Outline
• GSM Implementation Challenges
• Transceiver Architectural Tradeoffs
• CMOS Quad-Band GSM/GPRS Transceiver
• Test Results
• Conclusion
Chip Radio Evaluation Board
Power Amp Module
Quad-Band Transceiver
Antenna Switch Module
VC-TCXOSAW Filters& Matching
PLL Settling Timew/ Fast Charge Amp.
w/o Precharge Amp
VCVC
time
PLL settling time of 150µs
Receiver Sensitivity (EGSM900)
-112
-110
-108
-106
-104
-102
-100
975
987
999
1011
1023 11 23 34 46 58 70 82 94 10
611
8
EGSM Channel (ARFCN)
Sens
itivi
ty (d
Bm
)
3GPP GSM Spec (-102dBm)
Measured EGSM Sensitivity
-112
-110
-108
-106
-104
-102
-100
975
987
999
1011
1023 11 23 34 46 58 70 82 94 10
611
8
EGSM Channel (ARFCN)
Sens
itivi
ty (d
Bm
)
3GPP GSM Spec (-102dBm)
Measured EGSM Sensitivity
In-Band Blocker Performance (PCS)
-50
-40
-30-20
-10
0
10
2030
40
50
-50
-44
-38
-32
-27
-21
-15
-9.2
-3.4 3.4
9.2 15
20.4
26.2 32
37.8
43.6
Blocker Offset Frequency (MHz)
dB
-26dBm 3GPP Spec for BlockerLevel Input at Antenna
Measured Blocker Level
Margin Relative to 3GPP
-50
-40
-30-20
-10
0
10
2030
40
50
-50
-44
-38
-32
-27
-21
-15
-9.2
-3.4 3.4
9.2 15
20.4
26.2 32
37.8
43.6
Blocker Offset Frequency (MHz)
dB
-26dBm 3GPP Spec for BlockerLevel Input at Antenna
Measured Blocker Level
Margin Relative to 3GPP
49.4
49.4
TX Modulation Mask & Phase ErrorEGSM900 Modulation Mask EGSM900 RMS Phase Error
TX Phase Error at PA Output (PCS)
0.02.04.06.08.0
10.012.014.016.018.020.022.0
512
532
552
572
592
612
632
652
672
692
712
732
752
772
792
Peak Phase ErrorRMS Phase Error
3GPP Required Peak Phase Error
Receiver Performance Summary
9593RX current (mA)-109-110Sensitivity at antenna (dBm)100100RX gain (dB)4040Input IP2 (dBm)-15-15Input IP3 (dBm)2.72.7Noise figure (dB)
DCS1800/PCS1900
GSM850/EGSM900
Receiver Measurements
Transmitter Performance Summary
4545Sideband Suppression (dBc)4040Carrier Suppression (dBc)
-162-165Noise at 20MHz Offset (dBc/Hz)160160Worst Case PLL settling time (µs)+6+6Output Power (dBm)
112108Current (mA)
-65-66Output Modulation Spectrum at 400kHz Offset (dBc)
1.21.0RMS Phase Error (degrees)
DCS1800/PCS1900
GSM850/EGSM900
Transmitter Measurements
Conclusions
• Single-Chip CMOS Transceiver Demonstrates Cellular Performance
• Low Power/Noise Inductorless PA driver
• Fast Settling PLL Supports GPRS Class 12 Operation
• State of the Art RX Sensitivity Performance in Standard CMOS