A Simulation Method for Accurately Determining DC and ...athena.ecs.csus.edu/~pheedley/MSDL_old/MSDL_DOTB...A Simulation Method for Accurately Determining DC and Dynamic Offsets in

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

A Simulation Method for Accurately Determining DC and Dynamic Offsets in Comparators

Thomas W. MatthewsPerry L. Heedley

Mixed-Signal Design LaboratoryDepartment of Electrical and Electronic Engineering

California State University Sacramento

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

Terminology

• A SPICE “test bench” includes~ analysis and measurement commands ~ Circuit elements in the SPICE file to provide

power, signals, and required connections for the device under test (DUT)

~ Circuit elements to facilitate analysis • This presentation describes the

“Dynamic Offset Test Bench” or DOTB.

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

Outline

• Introduction~ Clocked Comparators~ Offset

• Theory of operation of the DOTB• Practical Implementation of the DOTB• Examples of use• Conclusions and future directions

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

Clocked Comparators

• Comparison of vP and vN made at clock edge

• Digital outputs latched until after next comparison• “Analog latch” followed by R-S digital latch

~ Analog latch typically regenerative (switched)

Pv

Nv

Analog inputs

Digital outputs

( )P N OSv v V− > ⇒Q high

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

Importance of Offset

• Offset is fundamental measure of accuracy~ Ideally, VOS = 0~ Random and systematic parts

• Design problems~ Time variant system; analysis problem~ Offset includes dynamic effects~ Simulations may require iteration

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

Dynamic Offset Test Bench(DOTB)

• SPICE “test bench”• Single simulation finds the input-referred offset

voltage~ DC and Dynamic effects are included~ Systematic (direct result of given conditions)~ Find sensitivy of VOS to single offset sources

• Can be combined with statistical analysis

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

Theory of Operation

∫

FBvREFv Pv

Nv

ODv• Comparator operates at speed

• Comparator alternates statesin equilibrium

• avg(vFB) is considered to be the decision threshold

( )OS FB REFV v v= −avgInput offset voltage is given by:

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

ResolutionFBv Gear shift

∆V1 ∆V2

• Resolution limited by size of integrator ∆Vin one period~ Higher integrator gain converges faster,

but has less resolution~ “Gear shift” increases resolution after

convergence• CAD tool calculates avg(vFB) over known period

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

Effects included in result

• Simulated offset includes static effects~ VT - mismatch (input-referred)~ Any other modeled mismatch (e.g. rds)

• Simulated offset includes dynamic effects~ Charge injection from switches~ Mismatch of parasitic capacitances~ Time-varying input signals

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

Practical Application

REFv

FBv 1R2R

CMV

C

INTv

Q

Q

• Circuitry under test in dashed box e.g., differential comparator for pipelined ADC

• Ideal elements realized in SPICE filee.g., controlled sources and ideal switches

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

Sample Simulation Results

INTv20mVREFv =

• Actual simulation results shown• Note gear shift • Some topologies will automatically

center on decision threshold before gear shift

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

Examples of Use• Simulations of comparator circuit

(from pipelined ADC)~ Used real process models and DOTB~ Actual ADC reported good specifications

• Will illustrate ~ VT – mismatch~ Mismatched parasitic capacitances~ Effect of reset switch strength

• Record of success: Industry, UC Davis, Cal. State Sacramento and San Jose State

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

Example Comparator

• Systematic VOS = 200µV• VSW swing minimizing circuit (SMC)

~ Less charge injection~ Adjustable reset switch ON resistance

SMCI

SWV

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

VT -Mismatch Effects

SMCI

SWV

One at a time

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

Parasitic Mismatch Effects

SMCI

SWV∆CP = 5fF(+10%)

ISMC VOS Sensitivity 200µA 32.1mV 6.4mV/fF 100µA 5.4mV 1.1mV/fF 50µA 0.5mV 0.1mV/fF

Weaker Reset(Caution!)

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

MismatchCause

σ Offset*

(mV) Sens. (V/V)

Input- Referred

(mV) ∆VT 1-2 4.0 1 4.0 ∆VT1A-2A 4.0 1 4.0 ∆VT 3-4 2.0 2.6 5.2 ∆VT 5-6 8.0 0.25 2.0

Statistical Analysis

2 2 2 2( ) 4 4 5.2 2OSVσ = + + +

* Calculated from process and Pelgrom’s method

Must include all significant offset sources

Can help decide relative sizes of transistors

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

Monte Carlo• Statistically significant number of simulation runs

~ Assign new mismatches each time based on their distributions

~ Record relevant results after each run~ Summarize statistics (e.g., VOS)~ Faster simulations are better

(hence gear shift)• Assess each offset mechanism as % of total

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

MetastabilityFBV

ODv

• Very small integrator gain~ Metastability no output change

hysteresis~ Finds limits of metastable region

3/8/2006 MixedMixed--Signal Design LaboratorySignal Design Laboratory

Conclusions

• A SPICE test bench has been presented which is useful for~ determining the input-referred offset of

comparators~ identifying the relative contribution of different

effects to the input-referred offset~ giving insight into metastable behavior