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A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards National Bureau of Standards Boulder, Colorado 80302 U.S. DEPARTMENT OF COMMERCE, Elliot L. Richardson, Secretary James A. Baker, Ill, Under Secretary Dr. Betsy Ancker-Johnson, Assistant Secretary for Science and Technology NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Acting Director Issued June 1976
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A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

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Page 1: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

A Satellite-Controlled Digital Clock

J. V. Cateora D. D. Davis D. W. Hanson

T i m e and Frequency Divis ion I n s t i t u t e for Basic Standards Nat ional Bureau o f Standards Boulder, Colorado 80302

U.S. DEPARTMENT OF COMMERCE, El l iot L. Richardson, Secretary James A . B a k e r , I l l , U n d e r Secre tary D r . Betsy Ancker-Johnson, Assistant Secretary fo r Science and Technology

N A T I O N A L B U R E A U O F STANDARDS, E r n e s t A m b l e r , A c t i n g D i r e c t o r

Issued June 1976

Page 2: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

CONTENTS

!

I

1. INTRODUCTION

2. SYSTEM DESCRIPTION

2.1 FORMAT

2.2 TIMF CODE DISTRIBUTION

2.3 TIME CODE GENERATION

2 . 4 TIME CODE RECEPTION

3. DIGITAL CLOCK DESCRIPTION

3.1 DIGITAL CLOCK CIP.CUITRY

3.2 SOFTWARE LISTING

3.3 DIGITAL CLOCK PERFORWNCE

4. CONCLUSION

5. REFERENCES

FIGURE 1

FIGURE 2

FIGURE 3

FIGURE 4

FIGURE 5

FIGURE 6

FIGURE 7a

FIGURE 7b

FIGURE 8a

FIGURE 8b

FIGURE 9a

FIGURE 9b

FIGURE 10

FIGURE 11

FIGURE 1 2

FIGURE 13

FIGURE 1 4

FIGURES

SMS/GOES COVERAGE

INTERROGATION YESSFGE AND TIME CODE FORMATS

TIME CODE DISTRIBUTION

TIME CODE GENERATION AND CONTROL EQUIPMENT

RECEIVER BLOCK DIAGPAM

TIME DELAY THROUGH A GEOSTATIONARY SATELLITE AT 115O WEST LONGITUDE

TYPICAL DELAY DIURNALS FOP. THE EASTERN SATELLITE WITH WALLOPS ISLAND TRANSMITTING

TYPICAL DELAY DIURNALS FOR THE WESTERN SP-TELLITE WITH WALLOPS ISLAND TRANSMITTING

SOFTWARE FLOW CHART

SOFTWARE FLOW CHART (CONTINUED)

RAM MAP

REGISTER MAP

DIGITAL CLOCK BLOCK DIAGRAM

MICROPROCESSOR CLOCK PHASE LOCKED TO DATA CLOCK

DIGITAL CLOCK SCHEMATIC

DIGITAL CLOCK DISPLAY SCHEMATIC

DIGITAL CLOCK, DISPLAY, AND PATH DELAY SLIDE RULE

iii

1

1

3

3

6

6

10

14

20

20

40

41

2

4

5

7

8

8

9

9

11

12

15

15

16

18

19

21

22

Page 3: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

F I G I l R F 1 5 a

F I G L I R E 15b

F I G C R E 15c

F I G U R E 15d

F I G U R E 15e

F I G l i R E 1 5 f

F I G U R E 1 6

F I G U R E 1 7

F I G U R E 1 8

P I S P L A Y BOARD (FRONT)

D I S P L A Y BOARD (BACK)

CLOCK BOARD (FRONT)

CLOCK BOARD (BACK)

CLOCK BOARD COMPONENT LAYOCT

D1SPLP.Y BOARD COYPONENT LAYOUT

UTC (MBS) - S A T F L L I T E CLOCK (MICROPROCFSSOR)

n I G I T A L CLOCK PCRFOP_"~lAXCE YEASUREMENT S E T U P

CTTC ( N B S ) - S A T E L L I ? F CLOCK ( T T L )

23

24

25

2 6

2 1

2 7

36

37

39

i v

Page 4: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

A SATELLITE-CONTROLLED DIGITAL CLOCK

J. V. Cateora, P. D. Davis, and D. W. Hanson

A digital clock, resettable and controlled by the time code relayed by NOAA's SMS/GOES satellites, is discussed. The clock's desiqn is based upon a four-bit microprocessor and uses the redun- dancy of the data to improve its performance. Satellite position is included. in the clock's display for delay corrections to the received time.

A discussion of the generation, distribution, and reception of the time code is also included to aid the explanation of the clock's operation and performance.

Key Words: Clock; microprocessor; satellite; time: time code.

1. INTRODUCTION

This report describes a 3icrital clock developed by the fjational Bureau of Standards (NBS) which is controlled by a time code transmitted from the National Oceanic and Atmospheric A.dministration's (NOAA's) meteorological satellites. The first two satellites launched in this series are known as the Synchronous Meteorological Satellites (SMS) with all others followinq designated as Geo- stationary Operational Environmental Satellites ( G O F S ) . Long-range plans for these NOAA Satellites call for the positioning of one satellite at approxivately 135 degrees Vest Longitude, another at 75 degrees West Longitude, and a third to be an in-orbit spare. The approximate coverage of these satellites is shown in figure 1. As these satellites deteriorate with age, replacement satellites will be launched. This planned configuration of satellites is expected to be in effect by early 1976. During most of 1975, one satellite was operated from 115 degrees West Longitude, an intermediate point between the two planned loca- tions rentioned.

The time code is used by Y O P A in a data collection program where the FMS/ GOES satellites relay data from remote observing platforms such as buoys, auto- matic weather stations, ships, aircraft, and halloons to a processing facility. Many of these platforms will use the time code to date the data as they are collected or to time order their data transmissions to the satellites. NBS designed and implenented the time code for these satellites. To insure com- patibility of the time code with the data collection platforms (DCP), NBS de- signed a digital clock using a simple low-cost microprocessor. The micro- processor approach to the digital clock design was taken because it offered the lowest cost and provided the flexibility to include or delete functions through software changes rather than hardware redesign.

The microprocessor-based digital clock described in this report has a number of interesting and innovatino features. It uses a priori information to improve the effective bit error rate experienced in the satellite link. It also pro- vides the information needed to compute the propagation path delay corrections to the received signals. The total system performance has indicated a 20 p s precision with accuracies hetter than 100 us. The digital clock, once set by the satellite time code, continues to keep time with or without reference to the satellite signal.

The parts cost for the digital clock without the power supply is less than $200 at the time of this writing. Power input is approximately 7 watts or 160 mA at -10 volts dc and 1 ampere at 5 volts dc.

2. SYSTEM DFSCRIPTION

This section describes the tive code system including its generation, dis- tribution, format, and reception. The reception of the time code is described. assuming the use of a receiver which was developed under a MOAA contract. This receiver is part of the Data Collection Platform Radio Set (DCPRS) designed for

Page 5: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards
Page 6: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

unattended operation over long periods of time, severe environments, arid low power consumption. Ohvious improvements can be achieved if the receiver is designed as a thing receiver and the above mentioned requirements relaxed. Because no other receiver existecl at this time, all references to reception assume the use of this receiver.

2.1 FORNAT

The time information, a diaital time code, is multiplexed into an interro- gation nessage format relayed by the SEIS/GOES satellites. The interrogation message is used to activate a transfer of a DCP's collected data to N O M ' S Wallops Island, \"irginia, facilities via the SKS/GOES satellites. The format consists of a 15-bit maximum-length sequence (VLS) for message synchronization immediately followed by 31 bits comprising a (31, 21) binary Bose-Chaudhuri- Rocquenghem (BCR) code. Four additional bits preceed each MLS sequence be- ginning on the 0.5 second and comprise a binary coded decimal (BCD) character of the time code.

Figure 2a shows the interroqation message format: Four time code bits followed by 15 bits of the message synchronization word and 31 bits of the address word. The pattern is repeated every 0.5 second, at a 100 bits per sec- ond rate, The leading edge of the first hit to every time code character de- fines the UTC 1/2 second mark. Figure 2b is the time code format; f o u r bits are extracted from the interroqation frame every half second for 30 seconds. The first 40 bits is the tire code synchronization message consisting of 10 BCD character ?.'s heginning on the UTC minute park and 10 BCD 5 ' s beginninq at the UTC half minute mark.

Following the code synchronization message are 10 RCD characters of the time code followed by 13 BCD characters representins the satellite's current position in geocentric longitude and latitude and its radial departure from a reference orbit expressed in microseconds.

2.2 TIMF CODE DISTRIBUTION

The interrogation message is sent to the SMS/GOES spacecraft at S-Band from Wallops Island, Virginia, and is retranspitted to the earth through a global antenna at approxhately 4 6 9 W z . The Manchester coded message phase- modulates the carrier +60 degrees. The interrogation message is received mainly by data collection platform radio sets (DCPRS) which provide the communication interface with rain and river qauges, ships, buoys, seismograph stations, tide gauges, and tsunami detectors. The DCPRS recovers the data and a data clock from the received interrogation message, the data clock being used for symbol synchronization.

When a DCPRS is addressed, its stored data are transmitted to the SMS for relay to the Wallops Island Command and Data Acquisition Station (CDA.). In some cases, such as the monitoring of seismic actfvities, it is desirable to label the data with the date of occurrence. Attempts to use internal clocks set by infrequent clock carries or by reception of EF or LF radio signals are expensive, labor intensive, and subject to an unacceptable failure rate. The time-of-year code in the interrogation format eliminates these problems and provides the SMS/GOES DCF user with a cheap, reliable, and simple system for data labeling or any other time ordered function required at remote sites or in difficult environments.

Figure 3 illustrates the time code distribution. Derived fror atomic clocks located at the CDA in Wallops Island, Virginia, the time code is com- bined with the current satellite position, multiplexed with the interrogation address and sync worc? and transmitted to the satellites at S-Band. ?he sat- ellites transpond the signal back tc earth at approximately 469 MHz where it is received by the DCPRS's.

-3 -

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Page 8: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

/

z 0

W

0 V

n

m

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Page 9: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

2 . 3 TIYE CODE GENEFViTIOX

NBS has installec? at the CDA at Wallops Island, Virginia, equipment to qenerate the time code and maintain Coordinated Universal Time (IJTC) to within a few microseconds of the Faster clock at YSS in Boulder, Colorado. Figure 4 is a block diaqram of the equipnent. There are two atomic frequency standards each driving a clock and format generator raking two independent systems. systen? provides the time code and satellite position to DCS racks A and B for multiplexins into the interrogation channels of the two SMS/GOES satellites. A l l components of each system are hacked with recharqeable batteries with suf- ficient capacity to operate four hoiirs without primary power. Should a failure he experienced in one of the time reference system t.he other can be switched in until it is repaired. The frequency of the atomic frequency standards can be coFpared to the fiBS frequency standard in Boulder, Colorado, using a freauency meter operating on television signals. This cornparison is accomplished by NBS staff at routine intervals. Satellite position is compated at NBS Boulder from orbital elements issued by X A S A ' s Goddard Space Flight Center and sent to Vallops Island hy telephone. P.n automatic answerinp syster connects the tele- phone line to a v.evory hank which stores the positions in the form of a large table valid for 128 hours for the two satellites. The time code format gener- ator addresses the memory with the date (days, hours, and minutes) and fetches the currently valid position for multiplexing into the interrogation message.

The interrogation channels on hoth satellites are monitored continuously

Each

in Boulder. Pny failure or drift of the clocks at Wallops Island is auto- matically noted for appropriate action.

2 . 4 TIPE CODF I?ECEPTIO?J

The interrogation channel is received hy the DCPRS which usually consists of a receiver and transmitter. A block diagram of the receiver is shown in figure 5. The transmitter section of the DCPRS has heen left out since it has no bearing on this discussion. The demodulator consists of a phase lock loop with a 10 Mz loop bandwidth and a timing recovery loop to derive the data clock for symbol synchronization. The demodulator provides outputs of data and data clock, the two inputs to the digital clock. The signals from the satellite occupy a bandwidth of 400 €12, and have a sianal level of approximately -139 dBm at the output of an isotropic antenna. A DCPRS receiver and digital clock has been successfully and reliably operated using both linearly and circularly polarized antennas with gains as low as 3 d B .

The signal delay from Pallops Island to the earth's surface via the SMS/ GOES satellites is nom.inally 260,000 us. This delay is a function of distance from the subsatellite point as shown in figure 6 . As a first order correction for delay, the time signals are advanced by 260,000 us at Wallops Island thereby forcing them to be nearly on tire when arriving at the earth's surface. Since the satellite is not in a perfect geostationary orbit, that is, it has some inclination and eccentricity, the delay experienced at any one point has a di- urnal component. ical peak-to-peak values of the diurnals for the Eastern and Western satellites are shown in figures 7a and 7b.

The magnitude of the diurnal is also position dependent. Typ-

'The data clock is a sequence of alternating ones and zeros used for symbol synchronization. processor clock is the oscillator governing the function of the microprocessor. The digital clock refers to the system (microprocessor, software, I/O, and dis- play) used to maintain time referenced to the time code from the satellite.

The RAM clock measures the accumulation of time. The micro-

-6 -

I

Page 10: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

T V S T A T I O N S

U A L L O P S ! S L A N O

I- I $-----I

F I G U R E 4. TIME CODE G E N E R A T I O N A N @ C O N T R O L E Q U I P M E N T

-7-

Page 11: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

ANTENNA 4 2 2 . 1 5 M H z + 41 .836 M H z +

, p i ~ l ] - - a ~ + p ~ l J L I M I T E R 4.833245MHz

7 2 0 H z BW I

RECOVERY L O O P )

w P H A S E L O C K E D LOOP,

B I N A R Y OATA

D A T A CLOCK

2 N D ORDER. H I G H G A I N

DEMODULATOR: P H A S E D A M P I N G : 0 .707 L O C K E D L O O P . 2 N O ORDER LOOP B A N D W I D T H : 6.9 H z LOW G A I N

L O O P B A N D W I D T H : 1 0 H z N O I S E B A N D W I D T H : 20 H z

6 S T E A D Y S T A T E ERROR: 5 1 0

FREQUENCY T R A C K : f 5 k H z FIGURE 5 . RECEIVER BLOCK DIAGRAM

F I G U R E 6. T I M E DELAY THROUGH A GEOSTATIONARY S A T E L L I T E AT 1 1 5 O WEST LONGITUDE

-8-

- _

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c

F I G U R E 7a . T Y P I C A L D E L A Y D I U R N A L S F O R T H E E A S T E R N S A T E L L I T E W I T H W A L L O P S I S L A N D T R A N S M I T T I N G

L O l i G l

F I G U R E 7b . T Y P I C A L D E L A Y D I U R N A L S F O R T H E W E S T E R N S A T E L L I T E W I T H W A L L O P S I S L A N D T R A N S M I T T I N G

-5-

Page 13: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

3. DIGITAL CLOCK DESCRIPTION

The digital clock was built to interface with NOFA's DCPRS's as they existed in early 1974. A microprocessor design was chosen because of its poten- tial low cost and simplicity. The microprocessor design replaced a previous random logic design amounting to 80 integrated circuit packages. Special fea- tures and properties of time messages were used in the microprocessor design. For example, each successive time-code frame differs only by 30 seconds, the length of the frame. Thus the nessages have a large degree of redundancy. This fact was used to, in effect, increase the signal-to-noise ratio or lower the bit error rate. The a priori information was used as follows: The microprocessor stores the time-of-year in random access memory (RAM) and continually updates itself by counting the 100 ITz 6ata clock. During every time-code frame received from the satellite the microprocessor compares its PAM time with the new time message. If there is agreement, everything is assumed to be in order. If there is disagreement, the microprocessor will continue to assume that the RAM clock has the correct time, but after four consecutive time frame disagreements the RAM clock is assumed to be in error. The microprocessor will then reset its RAM clock to the next time code message providing the satellite tire is being received as evidenced by the presence of the MLS and time code synchronization word. This procedure is referred to as an error bypass capability.

The 100 Hz data clock from the receiver is also subject to noise introducing additional zero crossings that can be interpreted by the microprocessor as 0.01 second increments in tine. To minimize the effect of this noise and provide a reliable and continuous 100 Hz to count even without the satellite signal, the microprocessor system crystal oscillator is divided down to 100 Hz and phase locked to the received data clock. The phase locked 100 Hz is then used as the time base for the microprocessor time-of-year (TOY) clock.

The two above mentioned procedures have used the cyclic nature of the data and data clock to improve the performance of the diaital clock.

The satellite ephemeris is displayed as received. Consequently, it is susceptible to more error than the TOY. One can only look for consistency in the display from frame to frame. The display is updated at the 00 and 30 seconds. Two successive frames of the same data insure the correct satellite position data is being displayed.

To fully understand the details of the operation of the digital clock, it is well to review the basic tasks it accoxvplishes. F thorough familiarity with the format of the interrogation channel is important to this understanding. Repeated reference to the software flow chart, figures 8a and 8b would also be helpful. just been connected to the receiver and is receivinq the interrogation channel properly. It must look at the data clock for a negative going transition to identify when to sense the data and acquire one bit of information. In other words, it acquires symbol synchronization by looking at the data clock. When the proper data clock transition is recognized, it samples the data and stores the sampled bit in memory, an index register of the CPU. In fact, the last 15 bits of data have been stored in index registers. the last 15 bits stored are examined for the MLS (100010011010111). If the latest stored 15 bits n?atch the sequence stored in program memory, MLS synchronization is declared. The microprocessor now knows the location of the four bits in every interrogation frame constituting a time code BCD character. The micro- processor then loads these four bits every half second into an index register and examines it to determine if it is part of the time code synchronization word, a BCD A or 5 depending on whether the frame is in the first or second half of the minute. When 10 consecutive A ' s or 5's are found, time code synchro- nization is declared. The next four bits to be loaded are the tens of seconds (TS) of the time code, then unit minutes (UM), tens of minutes (TM) , etc. , for the next 11 1/2 seconds or 21 four bit characters finishing with the units of microseconds of the satellite distance. These data are all written into RAM memory.

We begin the explanation by assuming that the digital clock has

The digital clock has available to it the data and the data clock.

After each bit is received and stored,

-10-

"

Page 14: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

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e

RESET ALL

TURN OFf FRAME MLS L COOE

1 I

ERROR

1

LKHT

INCREMENT 31 BIT

I I

NMP

LOAD 4

R A M CLOCK

SET C H N l WRITE TOO IN

FLAG RAM

COUNTER

lNCREMEN1

COUNTER

LOAD 4

SAT WS I N RAM

f

&UP TO

1111

4 INCREMENT

50 BIT CWtlTER ,

IHCREYENT FRAME

COUNTER

FRAMES

F I G U R E 8a. S O F T W A R E FLOW C H A R T

- 1 1 -

Page 15: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

I I

w cs 4 3 k- LL 0 v,

4

- 1 2 -

. _

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Y

The mic roprocesso r now c o u n t s b i t s and f r a m e s u n t i l it a r r i v e s a t t h e TS c h a r a c t e r of t h e n e x t frame. I t does n o t s e a r c h f o r MLS o r code sync a g a i n s i n c e t o t a l s y n c h r o n i z a t i o n may be rr .a intained by s imply c o u n t i n g t h e 1 0 0 Hz t i m e base o v e r t o t h e beg inn ing b f t h e n e x t t i m e code f rame. On t h e second p a s s o f a t i m e code frame t h e mic roprocesso r o n l y compares t h e newly a r r i v e d c h a r a c t e r o f t h e TOY w i t h t h e co r re spond ing i n t e r n a l RAM c h a r a c t e r . Should t h i s comparison f a i l anywhere i n t h e TOY frame it w i l l be coun ted as a frame e r r o r . I f f o u r con- s e c u t i v e frame e r r o r s o c c u r , t h e m i c r o p r o c e s s o r w i l l b e g i n a new s e a r c h f o r b!LS api? t i m e code sync. When s u c c e s s f u l l y a c h i e v e d t h e s a t e l l i t e TOY w i l l be w r i t - t e n i n t o t h e RAN c l o c k , r e s e t t i n g t h e RAM c l o c k . I f t h e mic roprocesso r does n o t f i n d FILS and t i m e code s y n c h r o n i z a t i o n it w i l l n o t d i s t u r b t h e RAM c l o c k . T h i s p r e v e n t s t h e RAM c l o c k f r o v b e i n g reset when no s a t e l l i t e s i g n a l i s p r e s e n t .

The RAM c l o c k c o n s i s t s o f c h a r a c t e r s r e p r e s e n t i n g d a y s , h o u r s , m i n u t e s , s econds , t e n t h s o f seconds , and hundred ths o f s econds . The d a t a c l o c k i s d e r i v e d a t Wallops I s l a n d from an a tomic c l o c k . Each c y c l e of t h e d a t a c l o c k r e p r e s e n t s 1/100 of an a tomic second and i s coun ted by t h e mic roprocesso r t o upda te i t s RPA c l o c k . The m i c r o p r o c e s s o r h a s i t s sys tem o s c i l l a t o r phase locked t o t h e incoming d a t a c lock . I f t h e d a t a c l o c k i s l o s t , t h e i n t e r n a l o s c i l l a t o r w i l l c o n t i n u e t o p rov ide t h e 0 . 0 1 s c o u n t t o keep t h e RAEl c l o c k a c c u r a t e .

The RAM c l o c k , exc lud ing t h e 0 . 1 s and 0 . 0 1 s d i g i t s , i s m u l t i p l e x e d f o r d i s p l a y by L E D ' s under mic roprocesso r c o n t r o l . The s a t e l l i t e p o s i t i o n i s loaded i n t o RAM memory e v e r y frame a s r e c e i v e d . A t t h e 00 and 30 second RAM s t o r a g e o f p o s i t i o n i s t r a n s f e r r e d t o an e x t e r n a l s h i f t r e g i s t e r and m u l t i p l e x e d t o L E D ' s under independent c o n t r o l . Consequen t ly , i f t h e s a t e l l i t e s i g n a l i s l o s t , t h e s a t e l l i t e p o s i t i o n w i l l a l s o d i s a p p e a r from t h e d i s p l a y .

The program f o r c o n t r o l l i n g t h e m i c r o p r o c e s s o r o c c u p i e s two 8 b i t x 256 programmable Read Only Memories (PROMS), t h a t i s , 512 e i g h t - b i t b y t e s . The a c t u a l program r e q u i r e s a b o u t 4 6 0 b y t e s .

The program c o n s i s t s o f a main program c a l l e d START of abou t 21C b y t e s , s u b r o u t i n e WAIT o f abou t 1 7 5 b y t e s , s u b r o u t i n e SPOS o f abou t 25 b y t e s , subrou- t i n e LOAD4 of abou t 30 b y t e s and s u b r o u t i n e WAIT100 of abou t 2 0 b y t e s .

The main program START f i r s t e s t a b l i s h e s "MLS" sync by comparing t h e l a t e s t 1 5 b i t s r e c e i v e d w i t h t h e 1 5 b i t s o f t h e known MLS p a t t e r n s t o r e d i n PROM. T h i s l o c a t e s t h e c o r r e c t s t a r t i n g p o i n t i n t h e b i t stream t o s t a r t look- i n g f o r BCD c h a r a c t e r s , t h a t i s , i d e n t i f i e s t h e BCD c h a r a c t e r s of t h e t i m e code.

Next , START l o o k s f o r 1 0 "A" o r 1 0 "5" c h a r a c t e r s i n o r d e r t o e s t a b l i s h "CODE" o r frame sync .

(BCD c h a r a c t e r " A " ) p a t t e r n s s t a r t i n g a t 00 s or t e n 0 1 O l 2 (BCD " 5 " ) p a t t e r n s

s t a r t i n g a t 30 s. Once "CODE" sync h a s been e s t a b l i s h e d t h e n e x t BCD c h a r a c t e r r e c e i v e d w i l l be t e n s of seconds . E s t a b l i s h m e n t o f "MLS" and "CODE" sync i s i n d i c a t e d by l i g h t s on t h e d i g i t a l c l o c k ' s d i s p l a y boa rd .

Every 30 seconds t h e code c o n t a i n s e i t h e r t e n 10102

V7hen t h e d i g i t a l c l o c k i s f i r s t t u r n e d on , and a f t e r b o t h sync words a r e found, t h e r e c e i v e d TOY and s a t e l l i t e p o s i t i o n a r e w r i t t e n i n t o FWM by START. I n subsequen t p a s s e s of t h e r e c e i v e d code o n l y p o s i t i o n i n f o r m a t i o n i s w r i t t e n i n t o RAM u n l e s s d i s c r e p a n c i e s are found between t h e r e c e i v e d TOY and t h e TOY s t o r e d i n R A M .

Subrou t ine W A I T i s c a l l e d by START t o f i n d d a t a b i t s as t h e y appea r a t t h e i n p u t p o r t . When one i s found, WAIT i n c r e m e n t s t h e RAM c l o c k by 0 . 0 1 s . WAIT a l s o c o n t a i n s t h e coding f o r d i s p l a y i n g t h e TOY. When an 8 0 0 0 Hz t r a n s i t i o n i s sensed a t t h e i n p u t p o r t , WAIT d i s p l a y s one d i g i t of t h e TOY.

S u b r o u t i n e SPOS i s c a l l e d by W A I T a f t e r t h e RAM c l o c k has been updated and t h e t i m e i s 0 . 0 0 o r 3 0 . 0 0 s . When c a l l e d , SPOS l o a d s t h e s a t e l l i t e p o s i t i o n c h a r a c t e r s from RAM i n t o t h e p o s i t i o n d i s p l a y hardware which o t h e r w i s e r u n s independen t ly o f t h e mic roprocesso r .

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Page 17: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

LOAD4 is called by main program START to reconstruct a BCD character from four data bits. LOAD4 calls WAIT to locate the necessary four bits and stores the built-up BCD character in an index register reserved for this purpose.

WAITlOO is a subroutine of 18 bytes whose only purpose is to keep the clock's 1 pps as nearly on time as possible. It is called by WAIT when time is .99 s and waits only for the next .01 s pulse to occur, the instant when the 1 pps should be output, and ignores any 8 0 0 0 Hz pulses for display. As soon as the .01 s pulse is sensed by WAITlOO it outputs the 1 pps. If a scheme such as WAITlOO were not used, the microprocessor could sense an 8000 Hz pulse and be occupied by performing its display function when the .01 s pulse, signaling a change in unit seconds, occurs and could not output the 1 pps until many pro- gram steps later. The use of WAITlOO keeps the 1 pps on time within about 30 ps.

. Without WAITlOO the 1 pps occurs randomly within 400 p s of being on time.

A complete listing of the program appears on pages 2 8 through 35 . Figures 9a and 9b show the microprocessor's register maps. Figure 10 shows a loaical block diagram of the program.

3.1 DIGITAL CLOCK CIRCUITRY

The 4004 Central Processing Unit (CPU), 4702A programmable Read Only Memory (PROM), 4002 Random Access Memory ( R A M ) , 4008 Address Latch and 4009 Input/Output Multiplexers, 4201 Clock Generator, and TTL random logic packages form the microprocessor digital clock (see figure 10). The 4000 family of MOS microprocessor chips was chosen primarily because they are low cost four-bit devices and well suited for handling four-bit characters. The 4004 CPU was selected because of its low cost, easy availability and its proven history of use.

The microprocessor has one four-line input port, to which the received satellite signals are connected and eight four-line output ports which are assigned as follows:

Output Port Function

0 Input port reset 1 Satellite position BCD character 2 Time-of-Year display strobe 3 Time-of-Year BCD character 4 "MLS" and "CODE" sync indicator lights 5 1 pulse per second voltage pulse 6 spare 7 spare

One RAM output Port is also used to disable the satellite position display clock while the satellite position display is being serviced.

The hardware is divided between two circuit boards. One board contains the microprocessor along with its input and output circuitry. The other board con- tains seven-segment Light Emitting Piodes (LED'S) and associated TTL random logic to display the 2 2 time-of-year and satellite position characters. The 9 time-of- year LED's are multiplexed one digit at a time at approximately an 8000 Hz rate under microprocessor control. The 13 satellite position characters are stored in a hex-32 shift register and multiplexed by a free-running hardware clock at about a 60 kHz rate. The satellite position display is updated by the micro- processor every half minute at 00 and 30 seconds. This combination of display methods was chosen to avoid LED flicker associated with multiplexing 2 2 char- acters under the control of a processor with many other sequential tasks.

,

z

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Page 18: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

1 7 31 ond 4 6 Counter 31 and 46 Counter

i---i----* p6 10 M S Carnler. Wr l te F l a g .

Frome Error Counter I Recmstruc l ECO Chor

1 2 4 8 1 2 4 8 1 2 4 8 1 2 4 8

0 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 12345678910l11213141516

2 0

F I G U R E 9a. RAM MAP

E

I REG CHAR I STATUS CHAR I

FIGURE 9b. REGISTER MAP

- 1 5 -

Page 19: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

L

W v)

W U c L 0 a

a e 3

c - v)

"I I

al W L

0 L 0

n n v, v,

0 c L

0 a

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c 3 0 c \ 3 - c 0

0 0

0 0 D c3

c c

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- 1 =I =I

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0

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Page 20: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

The Manchester encoded TOY and position data phase modulates the 469 MHz carrier +60 degrees. Fron this are derived a 100 Hz data clock and serial binary data. The microprocessor's basic clock is 4.096 MHz which is frequency divided by ~ ~ 2 x 1 6 ~ 1 6 ~ 1 0 (=40960) to provide a frequency of 100 Hz. This 100 H z signal is phase compared with the 100 Hz data clock and a voltage proportional to the phase difference is fed hack to a pair of varactor diodes ip parallel with the 4.096 MHz microprocessor clock crystal to phase lock the 4.096 V H z clock to the recovered data clock. Figure 11 is a block diagram of the phase lock loop and microprocessor input circuitry. The phase lock loop and input port arrangement is important hecause if the satellite signal is lost for any reason or for any length of time, the 100 and 8000 Hz signals will still be present as they are now being derived from the crystal controlled microprocessor system clock. Fven though the 100 Hz data clock is lost, the microprocessor will continue to update its ?AM clock with the accuracy of the microprocessor's system clock. The satellite position information is not updated under these conditions and will be lost.

The microprocessor's one input port is connected as shown in figure 12. The 100 Hz satellite data clock is fed to the input port's "1" line through a 7474 latch. The "2" line is fed the 8000 Hz, through a latch also, derived from the frequency divider chain operating on the 4.096 MHz microprocessor clock. The input port " 4 " line is not used and the " 8 " line is connected to the received 100 HZ serial binary data.

The microprocessor, through software program control, samples the input port "1" line connected. to the 100 Hz satellite data clock. If a 100 Hz transi- tion is sensed the program updates an internal RCD clock stored in RAM by 0.01 s . The RAM clock is in the form of 11 4 bit BCD characters representing DDD, HH, MM, SS, ts, hs, that is, Day, Day, Day, Hour, Hour etc., down to .Is, .01 s. The -01 s update of the FW! clock and the appropriate carries ripple up to the tens of hours BCD character. The characters representing days are set by actually reading the received code into RAM.

The sensing of a 100 Hz transition at the input port "1" line also triggers the storage of data present at the "8" line as one bit of the four bits of a BCD charater. Four 100 Hz data clock transitions, sensed at the appropriate time, will therefore cause the PAM clock to be updated and one BCD character representing TOY or satellite position to be saved.

After looking for a 100 Hz transition, and whether or not one is found, the microprocessor next attempts to sense an 8000 Pz transition at the input port's "2" line. If an 8000 Fz transition is sensed, one digit of the date will be displayed on a 7-segment LED display character. If no 8000 Hz transition is sensed the microprocessor loops back and continues attempting to find either a 100 or an 8000 Fz transition. Basically then, the microprocessor spends its time looking for one of two conditions, a 100 or an 8000 Ez transition and then either updates its RAE1 clock or displays a character. Although the llAM clock contains BCD characters representing .01 and .1 s they are not displayed.

The microprocessor continuously compares the received TOY characters with the TOY characters stored in RAM. If four consecutive comparison frame errors occur the next received TOY character is rewritten into RAM and will be dis- played. the RAM clock to lessen the possibility of a noisy or marginal received signal causing an unintentional time reset. noisy signal conditions has shown this to be a good choice, but not necessarily the optimum strategy for all environments.

Four consecutive frame errors were chosen as the criterion for resetting

Experience with the digital clock under

Display of TOY is accomplished by a 7-segment decoder on the display board which receives the BCD data and time-of-day characters from output port #3 and drives the display segments. ?he associated multiplex count from output port ?I2 is decoded by a 1 to 16 multiplexer with 2N3638 transistors driving the LED strobe inputs.

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Page 21: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

i L

u X 0 0 0 a,

n W Y V 0

@L 0 v) v) W

7

7

W

x

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Page 22: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

L J

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Page 23: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

Figure 13 shows the wiring diagram of the display board. Figure 14 shows the clock, display, and a "delay slide rule." This slide rule is used to com- pute the delays from Wallops Island, VA, to the user's location via the satel- lite using the satellite position data contained in the time code format. See references 1-3 for more detail on the design and use of this slide rule. Figures 15a - 15f provide board layout and component location information.

The satellite position display consists of a hex-32 shift reaister which stores the 13 satellite position characters plus three hlank characters twice over. The 32 characters are then clocked out of the shift register in sequence by a hardware clock on the display board that runs independently of the micro- processor. The.output of the shift register goes into a 7-segment decoder and the 13 position characters are displayed. The position display runs by itself

hex-32 shift register is reloaded. Presently the satellite position changes only each half hour and the shift register receives the same satellite position information 60 consecutive times. able to update the position information at a higher rate.

. and receives attention from the microprccessor only at 00 and 30 s when the

However, in the future it may become desir-

3 . 2 SOFTWARE LISTING

Pages 28-35 show a listing of the digital clock's software. The program was punched into standard 80 column data processing cards only as a convenient method of documentation., The format of the listing is as follows:

Column

1 2 Blank 3-4 Hexadecimal instruction address within ROP chip 5 Blank 6-7 Hexadecimal microprocessor instruction 8 Blank 9-18 1 to 10 character label 19 Blank 20-22 1 to 3 character operation mnemonic 23 Blank 24-33 1 to 10 character operand (data, register, condition, label, etc.) 34-37 Blank 38-80 Comments

I

Hexadecimal page or ROM chip number

Some 4004 instructions require two bytes in which case the second line of the instructions may contain data or a jump address.

3.3 DIGITAL CLOCK PERFORMANCE

The digital clock has been in operation for many months in a number of locations but at this time only NBS at Boulder has explored its full potential. The chart shown in figure 16 illustrates the long-term performance of the digital clock. The chart represents the time difference between the NBS master clock and a 1 pps from the digital clock and was obtained using the equipment shown in figure 17. The chart shows a peak-to-peak noise of less than 40 p.5. The chart also shows the delay diurnal with a peak-to-peak value of approximately 450 us. tion was approximately 1/2 degree.

This chart was made during November 1975, when the satellite's inclina-

The accuracy of the digital clock is dependent upon the correct assignment of path and equipment delays. The receiver and digital clock delays were studied

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Page 24: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

r 1

a x x V 0 -1

-1

k- a

L J

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Page 25: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

-22-

Page 26: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

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0 I 0 (3 0 0 0 0 0 I 0 0 0 0 0 0 0 0

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Page 27: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

-24-

Page 28: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

h

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2 u 0 -J u

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Page 29: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

-26-

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Page 30: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

,

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FIGURE 15e. CLOCK BOARD COMPONENT LAYOUT

0 8 0

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a o o o o o o o o o o o o o o o o o o o d no &Zl

& 3 8 7 1 - 1 1 ZOOP' -

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F I G U R E l 5 f . D I S P L A Y BOAR0 COMPONENT LAYOUT

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R1 - l k R2 - 4.fk R3 - 7.5k R4 - 47 R5 - 47 R7 - 10k R8 - 10k R9 - 20k pc R10 - lOOk R11 - 10k R12 - 2.7k

R14 - 10k R15 - 10k R16 - 10k

R18 - 270 01 - IN4004 02 - IN4004 . D3 - IN4004 04 - IN4004 D5 - HV1628 D6 - MV1628 07 - IN4004 D8 - IN4004 X I - 4.096 HHz

C 1 - 47 pf 1 6 V C2 - 4.7 u f t a n t . C3 - 22 p f silver mica c4 - 1 u f C5 - 5.5-18 p f C6 - 0.1 uf ~ O V C7 - 4.7 uf t a n t . C8 - 4.7 Uf t a n t . c9 - .001 u f C10 - 4.7 uf t a n t . c 1 1 - 0.1 u f 1ov C12 - 4.7 U f t a n t . C l 3 - 4.7 uf t a n t . C14 - 4.7 pf t a n t . C15 - 4.7 Uf t a n t . C16 -74.7 uf t a n t . C17 - 4.7 pf t a n t . C18 - 4.7 uf t a n t . C19 - 4.7 uf t a n t .

~ 1 3 - 2.7k

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Page 31: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

a& G 01 3 02 FO STAFT 0-4-3 2.z 0 04 00 0 0 5 24 E-& 434 0 07 2 6 0 0 8 00

. 6--8428 0 O A 0 0 0 OB 2 A 8 6C 0 0 0 00 2c 0 OE 0 0 8 e f 2E 0 10 0 0 0 11 20 0 12 40 0 13 2 1 0 14 OF 0 15 E2 0 16 4 0 0 17 2C

0 19 0 1 A 8 le 0 I C 0 io 0 IE J 1F 0 20 5 21 5 1 ANOTHER il 2 2 0 0 0 2 3 22

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MNEMONIC

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COMMENTS

S A T € L L I T € - D?GET& GLtOcIcv T I M E OF YEAR AN0 S A T E L L I T E P O S I T I O N I h T H I S VERSION THE I H Z OUTPUT I S G€HWXW&B T 0 KX-T:FH€N 38 H+690 SfcW+Df

6e-m MT -A~+STAY t)w-It A -IAM OF B M 6000

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H Z T;ZANSITION OCCUPS

15 B I T HLS SYNC PATTERN H I L L BE STORED AS THE B I T S ARE QECEIVED

S H I F T RAM CHARS C T H R U F (HLSJ RIGHT ONE B I T T O MAKE ROOH FOR A NEHLY RECEIVED B I T

T H I S DATA I S THE H L S SYNC PATTERN AND I S STORED HERE BECAUSE THESE ROM mft€e%Wm *m "€ S-ME-Ki F t t € f e k t l ~ - . -

HLS SYNC PATTERN AN0 T H I S S I M P L I F I E S T H E I R COHPARISON L A T E R AT ADD. 046 ( H I L L BE EXECUTED AS NOPS)

r

RDP RAE CttW f f T I t t SftEf3Y0 It+ M - S f i f t W CLC 9 I T OF 4 M L S RECEIVED CHARACTERS = 0 RA L , if- CLB LO R a REG 8 CONTAINS A DATA B I T I N I T S 2 P O S I T I O N

THfS-+tAS-fFBREO -€*-R€G-6*33 +"-A--IMl H Z T q A N S I T I O N HAS SENSED AND A JUMP T O

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Page 32: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

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it 4 8 E6 '3 41 EO 0 42 21 OK II 63 32 0 4 4 FL 0 45 A 3 0 46 ki3 0 47 1 c ? 46 21 0 49 7 1 0 4A 4 2 il 4% 20 i? 4 C 4 G 0 40 2 1 0 4E DE 0 4 F E 2 0 50 2E 0 51 It 0 52 5 1 A G C I I I 0 5 3 O G 0 54 7 t 0 55 5 2 0 56 7F 0 57 52 S 5 % 06 0 59 B C C 5A 5 1 4 5d EO

0 SO 6 R 0 5E 2 E .HOi.E 0 5 F 20 G 60 5 1 VCFE+2 B 61 C O 0 62 7t 0 63 60 0 6 4 7 F ii 65 6 0 0 66 5 1 0 67 EO 0 6 d f 0 COOE SYNC il 69 2 3 0 6A A 5 0 ER A 0 0 6C 9c d 60 1 4 0 6E 75 D 6F FC

0 7 1 YC 0 72 1 4

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43 5 c 40 ~

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ssc P Q = I N P 1 C L E LO 2 3 SFjh JCFJ A 1 - Aba3TH' IJ IS7 91 - O K F I M PC

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CLP LO ?l SUE 9i J i b ! A C

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A9t) NEWEST 3 I T Yi=C:IVfO TO 8 P O S E T f O N O f CHAYACTLI? C p 1.E. STORE I T I N Q P H

PUT LOh(TEtiT'-3 OF AOO-'CSS O C I N T O P l

PUT CCNTEhTS O f '13 ( = t ) I N T O ACCUMULATOR SU3TFFrCT K A ~ CHuQ L F 2 O Y ACCUWJLATO?

I F L H A ? JU3P T O AGAINST I f T H I S T l J i N ON

C = (ACCUHULGTOK) I N C 3 E H E h T e l Ah& O K TO TEST NLXT 2AE CHAkACTEk CATA P O I N T IS k-LACHEO MLS M A T C H S S -- Y L S L I G H T

S E T U F p 7 TO COUNT 31 C A L L S T O WAIT

N&<E 3 1 CALLS TO h A I T T O S K I P 5 1 2 I T S J!TW:EN M i S AND :)LO LHA0ACTcR

I h I T I A L f Z i lG A / 5 C W N T E ?

CALL LOAD4 TO H A K i 4 CALLS TO WAIT TO 6ET O K 5 9CO C H A K A C T E ~

S E T UP ro P A K ~ 46 C A L L S T O WAIT

S K I P 46 G I T S BETHC_EN 6 C O CHARACTERS -- ONCE ' ILS SYNC i 3 E S T A B L I S H E D F R A W SYNC AND CODE R f i E I V I M G 1 5 GONE 3Y SYIPPIFJG B I T S E E T H E f N

G C T N E X T E C D CHARACTER accl C H A S C C T E ~ S

S C T UP TEST FG? P. O? 5 CHA;lACTE?, THAT IS LOOK FOG FRAME SYNC L O 4 0 THE GHAPACTCK A I N T O THE ACCUHULATOR

JUHP TO CONTIHUf IF CONTENTS O f P C = CHLi tACTkR A

LOG3 C H A V P C T E C 5 I N T 3 AGCUHULATOR

J U Y P TO CUNTINU: I F CONTENTS OF R C = 5

kFSET THE 13 A / 5 C3c)NTEe T O 6 , 1.E. GET REQOY TO COUNT 10 AS O? L O 55 AN0 G O 3ACK T O STAYT GO TO HO? I F NOT 1 3 AS O? 10 5s FOUNO

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f! 0 4 0 95 0 06 0 07 C 98 0 49 0 98 0 99 0 9c o 90 0 OE ? 9F 0 A0 2 P I T C O 0 A 1 3 6 I! A2 OC 0 A3 B O

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0 e5 A 4 0 e6 A 9

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i

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S r L L S T T O Y e 3 1 S k C O i 4 0 C H A k A C T F l IN k A H

F i N D I P l G 1 U US 9 4 13 55 CONSTITUTES COPE

C O 3 L SYNC O X U R S AT 4.54 A i 4 3 3 4 . 5 4 SECOND TH<FE FCJGC SET U N I T SECONll = 4

T t N T H S SECObi9 = 5 HUNU<:GTHS S E C O N D = 4

S Y N C , T H A T 15 LOCATZS STAG1 O F T O Y LOLL --

S t T UP T O SELECT KAY i ) / h C G 3/CHAt?S b T H 3 U F T I H t O F Y E A S (TOY) SCT ? 4 , T O Y CHAPACTTk E f l 4 O i i FLAG = 3

S E T iJP 46 9 I T COUNTER

SKIP 46 UITS I~ETWEE-N eca CHARALTERS

GET NEXT T I M L OF YEAR CHA2ACTES

TEST WRITE FLPL ($0) -- I f NOT = 0 JUMP TO C O Y F A Y E -- iLSi W K I T E TGY I N T 9 RAM

W F I l F . T O Y ChBkACTESS I N T O RAM O/REG 3 1 CHAqPCTERS C THRU F IPGKcI.!Z.NT AN0 TEST FOP i0 T O Y CHARACTtRS 2EAU AN0 W P I T l E N I N T O ? A d O R COMPARt.3

TEST 29 ( T O Y CHAR EPFIOQ F L A G ) TO SEL I F A T LEAST ONE TOY CHA<ACTER ESROR OCCURRED

INZREHENT TO INCQEMENT FRAME cRROR COUNTER E L S c R E S t T FEAME E.CZ?OR COUNTER T O 3: ABLE T O COUNT C, CONSECUTIVE FRAHE ERRORS

I N 3 Q E H E N T T O Y CHAR tREOE. COUNTEG

O U i I N G T H i r L k S T FiZAHi. I F I T 010 -- GO T O

-30-

Page 34: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

0 co 14 0 C l 0 2 0 c2 4c 0 c 3 oe '1 c4 G c 5 0 C 6 29 CO?!PA?E 0 C 7 A C 0 C 8 E 8 0 C9 F 1 0 CA 1 4 c CB B4 0 Cc' Dl 3 CD 09 3 CE 4G J CF 8 4 0 80 0 Dl 0 02 0 03 3 04 0 c5

0 07 0 08 ZA I S P T J 09 13 0 DA 2f N E X T 1 3 0 GB 20 0 DC 5 1 A G A I N 1 5 0 co o c C GE 7 E 0 OF OC 0 EO 7 F 0 Cl oc 12 E2 5 1 0 E 3 E[! 5 € 4 26 C F5 AC I! E6 E(! O =7 7 P 0 E 8 O b 0 E9 4 0 0 EA FO C E 9 r! fC 0 EO 0 EE 0 EF 0 FO E B J F 1 B O 0 F2 Z F NFXT37 3 f 3 E C 0 F 4 5 1 A G A I N 5 2 0 F5 O C 0 F6 7F 0 F7 F 4 0 FB 7 F 8 F9 F4 0 FA 7A 0 Fa F2 0 FC 7 6 0 FO F 2 0 FE GO 0 F F A G

o e6

J C N A&

JUN - - STA2T

- I S A T

ssc 635 L D sc S3t4 CLC JCN A d

LDH 1 XCh 44 JUN -

- R:T?19N

- YETUDN

F I P P5 1 3 FIr. P 7 2 D JYS - I S 2 Rt

I S 2 P.F

JHS - s9c P 5 La KC W C V IS2 Y t i

JUN -

- W A I T

- A G A I N 1 3

- A G b I N 1 3

- L C L D 4

- N E X T 1 3

- O f 2

F I k P 5 9 0 FIH P 7 E C J M S - I S 7 R =

I S Z i F

I S Z

IS2 RR

JUN -

- WAIT

- A G & I N 5 u

- AGA I N 5 0

- N X T 3 7

- N 1 X T 3 7

- I T 0 0

I F R S = 0 THEN 4 CONSECUTIVE F R A M E ERRORS OC:UF.~ED -- G O tjACK T O START -- E L S C GO ON T O ; iECEIUL SATELLIT : P O S I T I O N INFORMATION

AEKIVE H E ~ E IF WRITE f t a 6 - 1 ~ 0 ) I S - N O T = a TD COhPLIRL T C Y C H A I A C T E k I N RC WITH T O Y C H A 2 A C T R I N RAM

GO T O RtTUWh I F T O 3 CHA2ACTER I S THL SAME

S t T = 9 * CHA? ER%OF, FLAG =1 AN0 GO TO RETURN I F T O Y CHASACTER I S NOT T H k SAME

I N I T I A L I Z E 13 WOK0 COUNT AN2 SELECT OF ? A H C / i i E G l / C H A h A C T E & S 3 THSU F S A T L L L I T E PUS I T I O h I t 4 I T I E T c 46 611 COUNTES

S K I P 46 b i T 5 OkTHcEN SAT. POS. C H A R A C T € i S

G L T N f X T S A T E L L I T i P O S I T I O N CHAI?ACTER

H S I T E S A T . PUS. CHA?. I N T O RAC

INCSEf lENT S A T . POS. CHAK. ADORESS I N RAM

HhEP! T H I S P O I N T I S ?,EACHtU 13 SAT. POS. iHAt;.ACTERS H A V E BEEN 2 E C k I V f i I AND WFITTEN I N T O R A M

I N ~ T I A L I Z C Fa'? 3 7 F9AHE COUHT

I H I T I A L I Z L FOR 513 B I T COUNT

S K I P 50 b I T S I N A FcAHE

S K I P 3 7 FctAt lES BETWEtN ENG OF S A T E L L I T E P O S f T I O N A N 3 START OF T I M E OF Y E A R

i ;U BACK T O t l L C E I V t T I M E i l F YEAR A G A I N

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Page 35: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

I68-Q. u 1 0 1 2 2 1 0 2 O G a- 03-23 1 3 4 EA 1 C5 F 6 4 &-I72 1 07 30 1 0 8 k G9 F6 1 O A 1 2 I oa O F

i ao o c 3 e f 0 2 DISPLAY

.+ - OC 4 1

I CE

1 10 E2 1 11 A 7 1 12 ic 1 13 18 1 1 4 2 6 1 15 35 I 16 24 1 17 25 1 18 2 7 NZFRO 1 19 DO 1 I A E 2 1 %e 2 5 1 1C A 5 1 10 F 4 I 15: E2 1 1F 27 1 2 0 E9 1 2 1 F 4 1 22 E 2 I 2 3 67 I 24 6 5 1 2 5 41 1 2 6 00 I 2 7 1 2 8 1 2 9 1 EA 1 2B 8 6 COUNT 1 2 c D l I 2 0 E 2 1 2E 2 2 I 2 F 2 0 1 30 2 3 1 31 OF I 32 E2

1 3 4 F 1 1 35 F 6 1 36-fl 1 37 8 8 I 38 22 1 39 33 1 3 A 23 1 38 E9 i - X - f 2 1 30 F 8 1 3 E EO 1 3F 63

i 33 e 8

UA3 F I H P I 0 0 S?G +% ?T)R 9AR -JG + t 4 2 - COUNT

st84 JCN C1

JUN - - OISPLPY

- W A I T

L O # 2 WRc: L O 9 7 3CN A i

FIH P 3 3 5 F I H P 2 2 5 SRC P 3 LDH 0 WYG s9c P 2 L O R 5 C3A H Q R ssc P 3 Fz ON CMA WRK I N C R 7 I N C R5 JUN -

- NZERO

- H A I T

XCH 9 8 Lon 1 w FII” P i 2 0 SYC P i LDH F WXR XCX R 8 CLC RA R Ct& XCH 2 3 F I M P i 3 3 siic P 1 QDM H G O A A W RH I N C R 3

SELECT IN/OUT PORT NO. 0 FOR I N P U l AND K s F T

I F B O O 0 HZ IS PRESENT JUMP TO D I S P L A Y

CONTINUE LOOKING FO? 100 OR 80JO HZ T SANS I T IO& RfSET--&&S HZ

I F R 7 = 0 RESET RAf l &HIP/!?EG/GHAS SELECT ;\NO P E S 5 1 HUX STROBE AND ElUX OUTPUT FORT FO2 T I N , OF YEAR CHAqACTES

W?ITE LANK DATA ( a L A N Y = NOT 0 = F)

H l i I T ; OUT T I Y E OF YEAR STi70BE

W I T E OUT T I H E -OF YfdP, CHASACTER

INCFEMENT RAH T O Y C H A R A C T C ~ A D D ~ E S S I N C R t H E N 1 STRO0E

G O BACK AND H A I T FOZ ANOTHER 1 0 0 OR 8000 HZ T Fib NS I T I O N

S A V E INPUT PORT NO. o IN H R TEHPORARIL~ W R I T E OUT 1 T O RESET 130 HZ L A T C H ON WW&T Pew NO. 8

P O I N T TOY STROBE AT D I S P L A Y D I G I T NO. 0 WHEN 8 3 0 0 HZ occws T O tuw+tIzf-urSPtaY F L I C K c S -- PREVENTS A O I G I T FROH S T A Y I N G ON WHILE CLOCK I S B E I N G UPDATED R f S f O S E I N P U T PORT W J B 8 4 T A fo AGGGWtBfeA CLEAR 100 HZ FROM CARRY

€ t 5 A R - & 3 8 8 ItZ HFPrifffW

SELECT .SAM O/REG 3 / C H A 9 3 THRU FI THAT I S START WITH TOY a i 3 1 SECOND €ttAi?aC-TER

SAVE DATA I N R 8 2 B I T P O S I T I O N

READ .Ol SECOND CHARACTER I N T O ACCUMULATOR

I F C Y = l O S ACCUMULATOR IS GREATER THAN 9 SET ACCUMULATOR = ACCUHULATOR + 6

f+!EtFTHEtS-f +?Act 2leC-K BY -if1 SEeOtiB

WRITE e01 S BACK I N T O SAHE R A M L O C A T I O N

-32-

Page 36: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

1 4 0 23 I 4 1 F7 1 4 2 E€! 1 4 3 F9 I 44 EO I 4 5 12 1 46 60 I 47 20' 1 4 8 90 i k Q 9 F 1 4 A 1 C 1 48 58 1 4c Fl 1 40 2 0 I 4E 33 1 4F 21 1 50 E 9 1 5 1 2 0 1 52 9 0 I 53 4 c 1 54 I C 1 55 59 1 56 4 1

i 58 F1 NOTNINe 1 59 2 0 1 5 A 50 1 5 0 2 1 1 5c D F 1 50 E 2 I 55 1 5F I 6 0 6 3 USLC 1 6 1 2 3 1 62 F7 1 6 3 E L I 6 4 F f I 65 FC 1 66 6 3 1 67 23 1 6 0 F 7 1 6 9 E E i hA EO 1 6 8 DA 1 6C E e i 60 I A 1 6E 71 I 6F DO I 7 0 EC 1 7 1 63 HIFtUTE 1 7 2 2 3 1 73 F 7 1 7 4 E 6 1 75 F E I 76 EO 1 77 63 1 7 8 2 3 I 79 F 7 1 7 A LEI 1 70 EO I 7 C DA 1 70 E B 1 7E I A 1 7F 8 2

I 57 eo

S P C Pi TCC ADP OAA w RE' JCN C l - 'JSEC FI: : P j 9 0 Sub Ri JCN A 1

CL c F I 1.1 P 2 3 3 s3c PO 00 E' F I ' FC 9 9 sui5 i7c JCN A 1

JUEl - CLC F I M PO 5 J Y3C PG LOM F WliR

- NDTNINE

- N O T h I N E

- W A I T l C G

I N C 3 3 spc P i TCC ADV DAA W ?E; I N C 33 SSC P1 TCC A DM

LDP I C APE! JCN CO

L o b J

I N C 9.3 S"C PI T cc AL jM

DA A W?:! I N C ? 3 siic P i TZC A OM WaM L D K It A O M JCN CC;

n?r'

- M l N U T E

- HCIU?

- s I NE&€ PiE NT 2 AP; -6H AGAGT E-R-MM€S C L E A h ACCUHULATORI Y C V E CAReY T O 1 P O S I T I O N OF ACCUHULATORI CLEAR CARRY

CPA2ACTEE I n \ ( K A H -- D E C I Y A L AGJUST ACCUM. B ~ D .i 5 IN kntf TO C A W Y FROM .oi s

I f CY F i i O N - 1 SECOHG-= 1- DWT- TEST-FOE+S BECAUSE AFTER T H c SUET2ACTION CY IS CLEARED

i f H T H S SECONO S T I L t - I f f bGBUHULATUt - TEST F G I TENTHS SLCOND = 9

Q E U b e 0 1 SECOND I N T O ACCUHULATO? AND TEST FO? .O1 SfCONLj = 3

I F .I AND .Jl S i C O N l i = -99 JUHP T O S P E C I A L W A I T ~ O U T I N L WHICH ONLY H A I T S FOR lClr HZ TDCNSITION -- E L S ~ OUTPUT o T O PORT rlo. 5

OUTPUT F (NEG. L O G I C ill T O P O R T NO. 5

S ~ L E C T u h I r SECOND C H A R A C T E R IN R A M

ADA U N I l YECON3 ChArtACTES I N 4AH TO CAP,F.Y FYUY TENTHS bcCONf f I N ACCUt lULkrOR W h I T f U N I T SECONU ZHAkACTER I h T O RAN

SELECT T E K S OF SECOND ChAdACTER I N k A H

WPITE TENS OF SECOND CHASbCTEK I N T O R B f l

A C ~ L J ~ U L A T O ~ S T I L L cONTAI l . rS T L h S OF SECOND-- 4 r D 10 -- I F TENS 3 f SEtOPr'U WAS A b THEN A CPRSY OLCbRS -- I F S O SET T c N S SCCONO = 0

SfCONO C A k 2 U = 0 THzN SET T r N S SECOND = C At43 AUD THE Ckl i iZY T O U Y I T I I INUTES. I F TENS

S i L E C T U N l T E I N U T L CHASACTcP I N RAM

Ana U N I T M I N U T L I N ? & M TO CAitntY F R O r I TENS OF SECOND WGITE U N I T H f N U T E S I N T O S A Y

SFLECT TENS OF MINUTES C H P S A C T E E I N R A M

A C G TLNX OF MINUTE CHAKACTES I N RAM TO C A S K L F K O M U N I T H I N U T E S I N ACCUMULATO? ANG N F I T E TENS OF N I N U T E S I N T O ?AM I F TENS OF MINUTES = 6 C A 4 Y OVES T G U N I T HOUZS JUHP TO HOUII I F TENS OF H I N U T E S CARRY = 0

-33-

Page 37: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

a-8Q-m 1 8 1 EO 1 82 6 3 HOUS 1 83 23 1 84 F 7 1 85 E 8 1 86 F 6 1 67 EO 1 85 6 3 1 99 2 3 1 8A F 7 1 9B E B 1 8C EG 1 90 FG 1 RE 2 2 1 8 F 35 1 50 23 1 9 1 E 9 1 9 2 148 1 93 95 1 94 C J 1 95 2 2 TEST03 1 96 36 1 97 23 1 3 8 E 9 1 99 1 4 1 9A A2 1 98 22 1 4C 3 0 1 50 02 1 ¶E 1% I 9F A 2 I A0 FO 1 A 1 C t 1 A2 22 TENTHS 1 A3 3 4 I 44 2 3 1 A5 E? 1 F6 1 4 1 A7 A 9

4a-M 8 W9P I N C 9 3 SRC P t -

ADV DA I W?r , I N C 5 3 s=?c Pl TCC A3P H?N C L r, F IH Pi 3 5 ssc P 1 9 on J C N A 0

d dL F I H P 1 3 6 S 3 C P 1 4OH J C N A5

F I k P i 3 0 SU? ? Z J C N A G '

C L E 9JL F I P P 1 3 4 s6c P 1 ?OH JCF' A G

rcc

- T E S T 3 3

- TENTHS

- TENTr lS

- HUV0C.r-i) THS 1 A8 CC a9L 1 A9 22 HUNDK,ECTHS FIW P1 1 A A 33 3 3 1 AB 2.3 SIC P i 1 AC E9 ?OH 1 110 14 J C t i A 5 1 AE C4 - SFOS 1 AF CC 93L 1 fl0 FO H A I T 1 0 0 C L 6 1 61 z c FIt! PC 1 82 00 3 0 1 63 2 1 SRC P t 1 €34 E A 9 k D 13R 1 85 F 6 ?AR 1 B6 1 A J C N CC 1 87 8 4 - R E A G 1 Btl 2 0 F I N PO 1 P9 50 5 G 1 BA 2 1 ssc PO I EB Of LQH E 1 ec E2 H2R I BO 0 1 LDK 1 1 %.E E 2 W W 1 BF FO C L 9

WQITE U h I T HOUR I N T G R A M

S E t e G T - T E N S OF YOUSS CHAikCTEfc EN RAit

GEAO U V I T SECONL I N T G ACCU3ULATGR

I F bi.1IT SECChU = ii G O TEST FC' TEhS OF SEC3NL = L 32 J -- i L S E i i E T U i N

k = A O TENS OF SECONO I N T G ACCU'ULATOF

I F TENS OF SECGNC = 6 O D 3 GO TEST TLNTHS -_ SELONO = 2 -- = & S E ZETURN

I F T I N T H S OF SiCOND = G 60 TEST FOS HUMD2EDTHS OF SECOVOOS = G -- t L S E RETURN

I F HUNDPEUTHS StCOND = 0 GO S E R V I C E S A T E L L I T E P O S I T I O N D I S P L A Y -- ELSE 2ETUrlN

S P E C I A L W B I T S O U T I N 5 TO K i E P 1 H Z ot.( T I H E

SELECT I N / O U T PORT NO.0 FOR I N P U T AND RESET

IF ieG H Z IS NOT P E S ~ N T GO escK AND HAIT

3 ' SOnE MORE -- E L S E OUTPUT 1 HZ

OUTPUT C: (NEG. L O G I C 1) TO P O 3 1 NO. 5 .

WRITE OUT 1 TO KESE-T 1 3 0 HZ LATCH ON OUTPUT ?O;iT NO. L

-34-

Page 38: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

1 LO 4 1 1 C 1 65 1 c 2 1 c3 1 c4 20 SPOS 1 c5 1 3 1 C 6 21 1 L7 PI I C8 f L1 1 c9 2 2 1 LA 1 1 CB 2 1 4 Q A H 1 CC E9- 1 CD 2 3 1 CE F 4 1 C F E 2 i no 21 L r i c 3 1 02 E l I 03 G1 I D 4 E l 1 C5 7 1 1 C6 C t 1 97 7 3 I 0 8 C r j 1 c9 D @ 1 CA El 1 ce c c 1 cc 1 DO 1 PE 1 DF 1 F O G C L O A Z 4 1 € 1 R G 1 E 2 51 1 F3 G 3 1 E4 A b 1 E5 fl 1 E 6 F 6 1 E 7 AC. 1 E 3 U C 1 t 9 5 1 1 EA G O 1 €0 A F I F C 6 C 1 € 0 BC I E E 5 1 1 FF 0 0 1 FO A 8 1 F 1 F l 1 F2 F 5 I F3 8 C 1 F4 E C 1 F 5 5 1 I F6 O C 1 F 7 A P 1 F a F 1 1 F9 F5 1 FA F5 1 FO AC

1 FO C9 1 FE 1 FF

I FC ac

Jut4 - - U S t C

F I I l P b 1 3 S?C F E LL)K 1 ‘r( YP F I V P I 1 E S‘IC PC q j t . !

ssc P 1 CMA HF? SL;C F t

U WF L O M 1 W “P IS2 K l

I S Z 93

L@h r! WHP S t i L

Lsrt 3

- $F-ct-i

- i F A f 1

Litr c

JPlS - L O ? 5 C L C ?AS AGO P.L. XCH >C, J 3 S - LU ;is A30 2 C XCH S,C JMS - io i?i C L C ?AL A J D ?C XGI- kC

XCI- zt

- W L I T

- E C I T

- N A I T

JUS - - H b I T

LO ;i% CtC QA L QOL A O O F.C XZP RC BCL

G O BACK TCj P?OCESS U N I T SECONI lS

S E T UP S E L E C T O F d A Y 0 / 9 E G I / C H A R A C T E > S 3 ThZU F, S A T E L L I T E P O S I T I O N

v l R I T L A 1 T 3 r 7 A M OUTPUT PORT T O T U R N OFF 2 5 1 6 S H I F T C L G I S T E T S CLOCK SET U F O U T P U l POqT NO. 1 SELECT AN0 P 3

? = E O A S A T E L L I T E P O S I T I O H CHAR FKCH R A H

W G l T L OlJr A S C T C L L I T P O S I T I O N CHARPCTt t? T O OUTPUT PO’T NUflOE4 1

hF.ITE A 2 10 ?Ah O J T P U T POST T O CLOCK OATA I r i r L i 5 i e ~HIFT F,rGIST:i! -- B U T A i ~ U S T STILL aL LOING OUT T O K E - P SHIFT ~EGISTERS CLbCK Off I N L S E M E N T S A T C L L I T C F ’ O S I T I O N CHAR ALJOGESS F I L L H L X - 3 2 S H I F T 2 i G I S T E R (2518) l h I C E , T P A I IS, 2+413 CHA? + 3 Y L A N K S ) = 32 C H L Y

I i ’ i T r A i T O ;.‘AH OUTPUT POST T O T U q N S H I F T 4 z ; l S T t k S CLOCK SGCK ON

C L E U ? <C 1 N P k E P A I A T I O N T O GECUNSTRUCT 3CG ChA?ACT’% I N RC

GO TO & A I S T O G I 1 9 2 2 C H A > u C T t ? I J I 7

t l O V c u A T ~ B I T TCI 1 3 0 S I T i C i d ANO A C D TC r iC

D A T A 6 i T 1s A L i ? t A O Y I t 4 P D O S I T I O N - - J U S T A C D IT r o RC

GFT CtCU C t i A k A C T t r Z G b I T

i.1C.Vc b A T A 3 I T T O 4 P O S I T I O N A N 0 A D O 1 0 YC

GET 3CJ CkiA?ACTE? 8 B I T

P:GV= D L T A 1311 TO d P O S I T I O N Ah3 A O U T O ?C

- 3 5 -

. .

Page 39: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

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Page 40: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

i I

I

\

Data

Data Clock

L DIGITAL

* CLOCK

Antenna

IPPS

\

. . .

lpps From NBS Master Clock

t t

\

FIGURE 17. D I G I T A L CLOCK PERFORMANCE MEASUREMENT SETUP

-37-

Page 41: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

separately. ' The digital clock's delay was measured to be -5074 us with no sig- nificant variation over an observed time of a few weeks. The delay is rather artificial since it is a function of software and can be set to any value by instruction. As an example the software can be adjusted to effectively remove delay from the digital clock. The receiver's delay was measured as a function of signal level and modulation index with the results shown below. The manu- facturer specified the receiver's operating range to be between -100 and -130 dBm. The receiver delay for different modulation index was also investigated.

Input Signal Delay (us) Leve 1 Modulation Index

(dBm 1 +soo +60° +70

-100 10,874

-105 10,844

-110 10,838 10 , 829 10,814

-115 10,800

-120 10,748

-12 5 10,697

-130 10,626 10,598 10,576

0

The delay versus signal level over the full manufacturer's specified range amounted to nearly 300 ps with rather small sensitivity to modulation index. The receiving system variability lmplies problems when attempting to achieve a 100 ps time synchronization. A change in antenna gain, local interference adding to the receiver's total power input, or receiver gain changes can cause problems. The reason for the receiver's delay sensitivity is believed due to the absence of automatic gain control (AGC). A limiter was used in the second IF only. It must be remembered that this receiver was optimized to enhance an ability not directly related to time recovery. Simple modifications should stabilize its delay considerably.

A discussion of path delay correction will be based,on the results shown in figure 18 taken ln the same manner as that of figure 16, but using a clock which counts the 100 Hz transitions using only TTL circuitry rather than under micro- processor software control. 10 ps whereas the microprocessor, using 4 machine cycles (.instructions 1B4 through 1B7), had a peak-to-peak variation of approximately 40 us. In either case the following discussion is valid. The equipment delay in this case was 46,162 vs, most of this due to the clock using TTL only for 100 Hz transition counting,

In figure 18, at point X, the time interval counter indicates UTC(NBS) - Satellite Clock = 40370 ps. satellite's position as:

The resolution of the TTL approach is better than

The satellite clock also for point X provides the

Satellite Longitude 114.92OW

Satellite Latitude - 0.38O Satellite Radius 46 ps

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Page 42: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

L

Y u 0 -1 V

-1 -1 W I- 2

I

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Page 43: A Satellite-Controlled Digital Clock - NIST · A Satellite-Controlled Digital Clock J. V. Cateora D. D. Davis D. W. Hanson Time and Frequency Division Institute for Basic Standards

'.

The coordinates of NBS Boulder, Colorado, and Wallops Island, Virginia, are:

Longitude Lati tude

NBS/Boulder , CO 105.26OW 40. OOON

Wallops Island, VA 75.46OW 37.85ON

Using the delay slide rule, the path delays are computed to be:

Wallops Island to SMS2 SMS2 to NBS/Boulder Total Path Delay Equipment Delay Total Delay Time Advance at Wallops Island Expected Time Difference of Decoder Clock 1 pps and NTC(NBS) UTC(NBS) - Digital Clock =

The measured value was UTCtNBS) - Digital Clock =

128839 ps 125418 ps 254257 ps 46162 us

300419 ps 260000 ps

40,419 ps

40,370 ps

It is therefore concluded that

Wallops Island - UTC(NBS) = 49 ps

Part or all of this difference can be associated with:

a) Satellite position error b) Equipment delay error at Boulder c) Clock error at Wallops Island dl e) Ionosphere and troposphere (not accounted for)

Equipment delay at Wallops Island (assumed neiligible)

4. CONCLUSION

A simple'and inexpensive clock has been designed using a four-bit microprocessor which is set and controlled by the interrogation channel.of a SMS/GOES satellite. Preliminary measurements show the clock and its as$ociated system to provide a time resolution of better than 40 microseconds and an 'accu- racy better than 100 microseconds. The accuracy is presently limited by the delay uncertainty in the system, mainly the receiver, and by the uncertainty in the satellite's predicted position.

NBS is continuing an effort to reduce and account for all sources of error. A delay stable,receiver to reduce the equipment delay uncertainty will be devel- oped in later phases of the program. ephemeris generator will replace the present generator and a path delay correct- ing clock will be developed, as an extension to the basic clock described, to allow for high accuracy automatic time recovery.

A potentially more accurate satellite

. ~ . . ~ :-

-40-

. ..

-

I ,