1 Abstract- The project that our group chose was the high speed data converters project where we will design a first- order switched-capacitor sample/hold and amplifier with a closed-loop gain of 2. Sample and hold circuits are analog devices that grab the voltage of a varying signal and then hold it for a specific time at a constant level. These are the elementary analog memory devices. The sample and hold that we will be designing will be used specifically for pipeline analog to digital converters. I. SPECIFICATIONS AND BACKGROUND typical sample and hold uses capacitors to store the charge of the input signal. Most sample and holds use at least one operational amplifier which charges or discharges the capacitor so that the voltage across the capacitor is equal to the input voltage. A switch connects the capacitor with the output buffer. Here is diagram of a very simple sample and hold as well as a graph showing how a signal is sampled. C is a control signal controlling when the switch is open and closed. Figure 1. Sample and hold Diagram and Plot For our sample and hold, we will be using an operational amplifier that needs to have gain above 50 dB and a GBW greater than 250 MHz. The phase margin should be greater than 45 degrees and it should have a slew-rate above 250 V/us. Our supply voltages will be +/- 1.5 volts. II. SEARCH OF EXISTING SOLUTIONS There are a multitude of sample and hold circuits and applications and many that pertain to pipeline analog to digital converters. We went online to IEEExlore and found a couple of papers on pipelined ADCs. This helped us gain a better understanding of the functionality of our project and also realize the applications of this field. It also gave us some ideas that we could use for our own projects. The papers that we went over are listed in the reference section at the end of the report. We also used the Razavi textbook in our search. Chapter 12 on switched capacitor circuits was very useful and we were able to learn many new concepts as well as gain valuable insight for our project. Much of the circuits in our project stemmed from the textbook. III. JUSTIFICATION AND DEFINITION OF ARCHITECTURE We decided to implement our sample and hold circuit using the differential realization of the unity-gain sampler in Razavi’s book. The circuit is described in detail in Ch.12.3 on switched-capacitor amplifiers. Here is the schematic of the circuit we implemented. Figure 2. Differential Unity-gain Sampler For the switches in this circuit, we used simple MOSFETs. These switches are also described in Razavi’s book in the previous section. There are two types of switches that we tried to implement. The first is the charge injection cancelling switch which uses a dummy transistor to reduce charge injection and clock feedthrough. This switch is shown below: A Sample and Hold Circuit for Pipeline ADCs ECEN 474 Final Project Samuel Lee, Alexander Edward, and Peter Zhou A
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A Sample and Hold Circuit for Pipeline ADCs ECEN 474 Final ... · PDF file2 Figure 3. Dummy Transistor Switch to Reduce Charge Injection The second switch we used was the complementary
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Abstract- The project that our group chose was the high
speed data converters project where we will design a first-
order switched-capacitor sample/hold and amplifier with a
closed-loop gain of 2. Sample and hold circuits are analog
devices that grab the voltage of a varying signal and then
hold it for a specific time at a constant level. These are the
elementary analog memory devices. The sample and hold
that we will be designing will be used specifically for pipeline
analog to digital converters.
I. SPECIFICATIONS AND BACKGROUND
typical sample and hold uses capacitors to store the
charge of the input signal. Most sample and holds use at
least one operational amplifier which charges or
discharges the capacitor so that the voltage across the
capacitor is equal to the input voltage. A switch connects the
capacitor with the output buffer. Here is diagram of a very
simple sample and hold as well as a graph showing how a
signal is sampled. C is a control signal controlling when the
switch is open and closed.
Figure 1. Sample and hold Diagram and Plot
For our sample and hold, we will be using an
operational amplifier that needs to have gain above 50 dB and
a GBW greater than 250 MHz. The phase margin should be
greater than 45 degrees and it should have a slew-rate above
250 V/us. Our supply voltages will be +/- 1.5 volts.
II. SEARCH OF EXISTING SOLUTIONS
There are a multitude of sample and hold circuits
and applications and many that pertain to pipeline analog to
digital converters. We went online to IEEExlore and found a
couple of papers on pipelined ADCs. This helped us gain a
better understanding of the functionality of our project and
also realize the applications of this field. It also gave us some
ideas that we could use for our own projects. The papers that
we went over are listed in the reference section at the end of
the report. We also used the Razavi textbook in our search.
Chapter 12 on switched capacitor circuits was very useful and
we were able to learn many new concepts as well as gain
valuable insight for our project. Much of the circuits in our
project stemmed from the textbook.
III. JUSTIFICATION AND DEFINITION OF ARCHITECTURE
We decided to implement our sample and hold circuit
using the differential realization of the unity-gain sampler in
Razavi’s book. The circuit is described in detail in Ch.12.3 on
switched-capacitor amplifiers. Here is the schematic of the
circuit we implemented.
Figure 2. Differential Unity-gain Sampler
For the switches in this circuit, we used simple
MOSFETs. These switches are also described in Razavi’s
book in the previous section. There are two types of switches
that we tried to implement. The first is the charge injection
cancelling switch which uses a dummy transistor to reduce
charge injection and clock feedthrough. This switch is shown
below:
A Sample and Hold Circuit for Pipeline ADCs
ECEN 474 Final Project
Samuel Lee, Alexander Edward, and Peter Zhou
A
2
Figure 3. Dummy Transistor Switch to Reduce
Charge Injection
The second switch we used was the complementary
switch containing a PMOS and NMOS transistor which also
reduces charge injection. We will run tests using these two
switches and see which one gives us the best performance.
Figure 4. Complementary Switch to Reduce Charge
Injection
For the operational amplifier, we modeled our op-
amp after the one that is described in Abo and Gray’s paper