1 A Practice of ESL Verification Methodology from SystemC to FPGA – Using EPC Class-1 Generation-2 RFID Tag Design as An Example William Young, Chua-Huang Huang†, Alan P. Su‡, C. P. Jou and Fu-Lung Hsueh, TSMC, Feng Chia University†, and Global Unichip Corp.‡, Taiwan
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1
A Practice of ESL Verification Methodology
from SystemC to FPGA – Using
EPC Class-1 Generation-2 RFID Tag Design as An Example
William Young, Chua-Huang Huang†, Alan P. Su‡, C. P. Jou and Fu-Lung Hsueh,
TSMC, Feng Chia University†, and Global Unichip Corp.‡, Taiwan
Outline
RFID System Design ChallengesESL Design FlowESL Design Verification ResultsSummary and Future WorkQ&A
20Jan, 10
3
RFID System Design Challenges
July 7 ‘08
System Design NeedsReader - SimulatorData TransferTag – Simulator
RFID IC Architecture‘STD’ - IP
STD CellMemory (MTP)
Customized - IPDigital
PHY/CodecProtocol Engine
PMURF Transceiver
Reader Tag/RFID
RFID System Design (C++)Reader
Simulator
CommandInterpreter
ReaderOperation
CommandFramer
ReplyDeframer
TagSimulator
ReplyFramer
StateTransitionMachine
CommandDeframer
Test CaseInputdata
CommandFrame
CommandFrame
ReplyFrame
ReplyFrame
RTLDesign
ESL Design Flow
Specification
Algorithm Analysis
Data Flow Analysis
Janus ESL Design PlatformLegacy RTL IP ReuseTLM 2.0 ModelingArchitecture DesignHybrid ESL VerificationPerformance AnalysisESL IP VerificationHigh Level Synthesis (HLS)
HybridESL Verification
HLSRTLCoding
FPGAESL Verification
Architecture Design
ESL Design Verification
RFID C++ Reader& Test Harness
RFIDC++ Tag
Janus System BoardTSMC RFID C++ Reader/Tag Models
TL
M
2.0
Proxy
PCI I/F
=
A 200 X Faster Regression Testthan RTL Simulation
Xtor
TAGRTL
ESL Verification FlowConventional
RTL Design
Verilog TargetSimulation
C++ Developed& Verified
C++Test Vectors
VerilogTest Vectors
FPGA TargetEmulation
FPGA ReducedTest Vectors
Re-Write
Co-Emulation
RTL Design
FPGA TargetEmulation
C++ Developed& Verified
C++Test Vectors
Verilog TargetSimulation
VerilogTest Vectors
SCV
TLM 2.0
FunctionalVerification
Re-Use
ESL Design on RTL
Logic Bugs Identified
Debug
Fast Regression Test200X faster than RTL Simulation
RTL Design
FPGA TargetEmulation
C++ Developed& Verified
C++Test Vectors
Verilog TargetSimulation
VerilogTest Vectors
SCV
TLM 2.0
FunctionalVerification
Re-Use
ESL Design Verification Efficieny
Bug Count Distribution
0
5
10
15
1 5 9
Verification Week
Bug
Num
bers
ESL
TestBench
10
Summary - ESL Design Flow on RFID
July 7 ‘08
1. C++ Reader-Tag Simulator per STD
2. Test-suites
Tag/RFIDReader
’94 Pent.FDIV$$TSMC
TAGModule(…
3. ESL/IC Verification
4. IC Design
5. Customized Tester
Future work :ESL w. High Level Synthesis
Logic Bugs Identified
DebugFast Regression Test
RTL from HLS
FPGA TargetEmulation
C++ Developed& Verified
C++Test Vectors
Verilog TargetSimulation
VerilogTest Vectors
SCV
TLM 2.0
FunctionalVerification
Re-Use
Q & A
12
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