A novel physical model for the SCR ESD protection device

A Novel Physical Model for the SCR ESD Protection

Device

Alexandru Romanescu (1)(2), Pascal Fonteneau (1), Charles-Alexandre Legrand (1), Philippe

Ferrari (2), Jean-Daniel Arnould (2), Jean-Robert Manouvrier (1), Helene Beckrich-Ros (1)

(1) ST Microelectronics, 850 rue Jean Monnet, 38926 Crolles Cedex, France

tel.:+334 76 92 61 46, e-mail: [email protected]

(2) Institute of Microelectronics, Electromagnetism, and Photonics (IMEP-LAHC),

UMR 5130 CNRS, Grenoble INP, UJF, Univ. of Savoy, BP 257, 3 parvis Louis Neel, 38016 Grenoble cedex 1, France.

50 Words Abstract - The SCR (silicon controlled rectifier) is one of the most efficient ESD protection devices.

In order to improve the accuracy, convergence, scalability, and the parameter extraction and support time, a new

model was developed. It aims to reach its goals through a stronger relation between the physical phenomena and

its constitutive equations. The compact model was validated in CMOS 40 nm and CMOS 130 nm technologies.

I. Introduction In the context of increased demand from the industry

of more accurate, scalable and easier to maintain ESD

protection devices models, many studies regarding the

SCR (silicon controlled rectifier) have been carried

out throughout the world. All of them are based on the

bipolar junction transistor (BJT) device (the SCR – a

pnpn device – being similar to a pair of npn and pnp

interconnected BJTs (see Figure 1)).

We can identify two main approaches. The first uses

only BJTs – with an advanced electrical model (ST-

BJT or vbic) – in order to model the behaviour of the

SCR [1-4]. The most important drawbacks are that (i)

several unneeded phenomena are modelled,

unnecessarily burdening and complicating the model

and (ii) the plethora of available parameters allows us

to fit the main characteristics at both low and high

current, but we tend to model certain aspects with

equations that do not have any physical support (the

phenomenon modelled in the BJT differs from the one

in the SCR). The later has a very high impact on the

scalability of the model and over the parameter

extraction procedure.

The second approach pays a greater respect to the

SCR particularities [5,6]. It divides it into two

functioning states: one before the snapback, modelled

with 2 BJTs, and a second one, at high injection,

usually modelled with a pin diode. This separation

comes with two concerns: (i) the model is less

consistent and might lead to divergence related

problems due to its discontinuity and (ii) the

switching point, being strongly related to the

snapback, should be an output of the model, given by

the other effects, and not an empirical input.

Figure 1: SCR represented by 2 BJTs.

Model support and parameter extraction are important

resource-consuming tasks. A good model should not

only take into account the complexity-accuracy trade-

off, but also the efficiency of the related parameter

extraction strategy and maintainability.

The newly developed model aims to solve problems

like divergence, versatility (as the ability to be used in

various configurations or ESD protection designs),

and scalability domain (limited by too empirical

laws). This is obtained by the use of a more physical

approach, and can be considered as a real

improvement upon the existing state of the art.

II. Model theory The SCRs studied here are multifinger structures, with

one-finger layout shown in Figure 2, made in a

CMOS technology.

Being a pnpn structure, the main phenomenon at the

base of a SCR is the bipolar effect described in Figure

3. Previous investigations showed that a simple

approach with two bipolar transistors (BJT) cannot

model the SCR throughout its entire operating range

[5,6]. The main difference concerns the base charge

level, during high injection conditions. Also, the base

of each transistor shares the same physical volume as

the collector of the complementary one. Thus, the

charge balance differs in this case from what normally

happens (and is modelled) in a single (isolated) BJT.

Figure 2: One finger layout – seen from top

The herein developed model is still based on classical

transistor models. However it is seen from a SCR

point of view and the interaction between the different

parts is better taken into account. The equations were

modified and adjusted as needed. All of the code was

completely written in VerilogA.

From the transistor point of view, a simple model –

like the Ebers-Moll one – does not suit our

requirements. It lacks important effects like high

injection beta degradation, base width and resistance

modulation, and so on. In order to fit the

measurements, the extracted parameters would need

to be optimized to compensate the non-modelled

effects and, consequently, they get farther from their

physical meaning. This raises serious problems when

dealing with the scalability of the model, leading to

the necessity of highly empirical laws.

Figure 3: SCR turn-on mechanism; the two bipolar effects (of the

npn and pnp respectively) are interacting, leading to a

recombination area at high injection (in red)

A step forward, the Gummel-Poon model is based on

the base charge – a very important quantity in the

behaviour of a SCR. Therefore modified Gummel-

Poon equations, that reflect the particularities of our

device, are considered for the proposed model related

to the currents’ flow shown in Figure 3.

Figure 4: Model schematic

These particularities include:

redistribution of collector and base resistance,

modulation of the base/collector resistance,

high injection beta degradation correction

(due to physical coupling effects between the

two BJTs used to model the SCR),

transit time dependence of the currents

flowing through each transistor.

More complex phenomena like Kirk effect and Early

potential variation were tested and found unnecessary.

Quasi-saturation is, up to a certain level, taken into

account through the base/collector resistance

variation.

ESD-specific effects like avalanche breakdown and

self-heating [7] were taken into account and modelled.

A. Basic model

We start describing the SCRs' BJTs with common

Gummel-Poon equations. ITn and ITp (Figure 4) are

described by:

;Bn

RnFn

Tnq

II=I

Bp

RpFp

Tpq

II=I

(1)

where

;1

T

BEn

SnFn

V

V

eI=I

1T

BC

SRnRn

V

V

eI=I (2)

;1

T

BEp

SpFp

V

V

eI=I

1T

BC

SRpRp

V

V

eI=I (3)

ISn and ISp are the forward saturation currents of the

npn and, respectively, the pnp transistors; VBEn is the

voltage between the p-well (PW) and the cathode (the

base and the emitter of the npn transistor); VBEp is the

voltage between the n-well (NW) and the anode (the

base and the emitter of the pnp transistor). ISRn and ISRp

are the reverse saturation currents; VBC is the voltage

between NW and PW. qBn and qBp are the normalised

base charges.

2n1n 4q112

++q

=qBn (4)

2p

1p4q11

2++

q=qBp (5)

;11n

AFn

BC

ARn

BEn

V

V+

V

V+=q

KRn

Rn

KFn

Fn

I

I+

I

I=q2n (6)

;11p

AFp

BC

ARp

BEp

V

V+

V

V+=q

KRp

Rp

KFp

Fp

I

I+

I

I=q2p (7)

where VARn, VARp, VARp and VARp are the Early voltages

and IKFn, IKFp, IKRn, IKRp the knee currents.

For modeling the current gain, ISF has been chosen as

a model parameter (instead of the more common β),

so that:

;T

BEn

SFnBFn

V

V

eI=I T

BC

SRBC

V

V

eI=I (8)

T

BEp

SFpBFp

V

V

eI=I (9)

The relation between ISF and β is:

;SFn

Sn

FnI

I ;

SFp

Sp

FpI

I (10)

;SR

SRn

RnI

I ;

SR

SRp

RpI

I (11)

Note that for the reverse current only one parameter

(ISR) is used, the junction being shared by both

transistors. If β parameters were used, we would have

been forced to have two parameters (βRn and βRp), that

are in fact bound together (eq. 11).

IRE and IRC represent the low current recombination:

;TEn

BEn

SEnREn

VN

V

eI=I

TC

BC

SCRC

VN

V

eI=I

(12)

TEp

BEp

SEpREp

VN

V

eI=I

(13)

Each capacitance is divided in two parts: one given by

the transition charges (caused by the space charge

region at the p/n contact) and the second given by the

diffusion charges (given by the carriers transported

during the current flow):

;BEn

BEn

BEnV

Q=C

BC

BCBC

V

Q=C

(14)

BEp

BEp

BEpV

Q=C

(15)

transitionBEn

diffusionBEnBEn Q+Q=Q (16)

transitionBEp

diffusionBEpBEp Q+Q=Q (17)

transitionBC

diffusionBCBC Q+Q=Q (18)

n

mje

JEn

BEn

JEn

JEntransition

BEnmje

V

VV

C=Q

n

1

1

1

(19)

p

mje

JEp

BEp

JEp

JEptransition

BEpmje

V

VV

C=Q

p

1

1

1

(20)

mjc

V

VV

C=Q

mjc

JC

BC

JC

JCtransition

BC

1

1

1

(21)

CJEn, CJEp and CJC represent the junctions’ zero bias

depletion capacitances, VJEn, VJEn and VJC the built-in

potentials and mjen, mjep and mjc the junctions’

exponential factor.

The diffusion charge is discussed below.

B. Base charge model

The base charge is one of the most important

quantities, influencing both the DC behavior (high

injection beta degradation) and the transient one.

1. High injection beta degradation

The high current beta degradation is caused by the big

number of carriers in the base. They slow down the

accelerated charges, reducing the collector current in

respect to the base one. In the case of a SCR, the

phenomenon is different (see Figure 3). The base

charge of a transistor depends on the complementary

one, being evacuated by its collector current. For

instance, the base charge of the npn (electrons) is

neutralized by the collector current coming from the

pnp (holes). At high injection levels, the

base/collector becomes a recombination region,

stabilizing the current. The modification of the q2 term

(eq. 4) in the base charge equation (eq. 3) traduces the

coupling between the two BJTs:

HCCRnI

I+

HCCFnI

I=q

KRn

Rn

KFn

Fn

2n (22)

HCCRpI

I+

HCCFpI

I=q

KRp

Rp

KFp

Fp

2p (23)

),,( FpKFnFn IIIf=HCCFn (24)

),,( RpKRnRn IIIf=HCCRn (25)

),,( FnKFpFp IIIf=HCCFp (26)

),,( RnKRpRp IIIf=HCCRp (27)

where HCCF and HCCR are the high injection

correction coefficients.

2. Transit time

The base charge also influences the transit time and,

thus, the diffusion charge:

Bn

Fn

diffusionBEn

q

ITFFn=Q (28)

Bp

Fp

diffusionBEp

q

ITFFp=Q (29)

Bp

Rp

Bn

Rn

diffusionBC

q

I+

q

ITR=Q (30)

TFFn and TFFp represent the forward transit time, also

depending on the bias and the current flow:

TF

C'B'

TFF

FTFFFF

V

V

eI+I

IX+T=T

1.441

2

(31)

The XTF and ITF parameters serve for modelling the

increase of TFF at high currents, while VTF traduces the

variation with VBC (equivalent of Early effect in DC).

C. Base-Collector resistance

The base and the collector share the same regions –

the n-well and, respectively, the p-well; thus an

adapted model must take the place of the classical

base and collector resistances from the classical BJT

one.

Figure 5: Base/Collector resistance – terminal notations for the

npn transistor

Next, the well resistance has been divided in two

parts: RC and RB. The first term RC is constant and

models the contacts. The latter depends on the

injection level:

;bn

Bn

CpBCnq

RRR

bp

Bp

CnBCpq

RRR (32)

NWPW

n+ p+

np

n+p+

B E C

PW cathode anode NW

psub

D. Substrate effect

The substrate effect is modeled by a parasitic pnp

transistor (Figure 4):

Bpsub

RpsubFpsub

Tpsubq

II=I

(33)

IFpsub and IRpsub are modeled in the same way as (eq. 3)

and (eq. 4). There is no need to specially model the

forward current gain for this transistor. This

phenomenon is already modeled through ITpsub (with

ISpsub as a parameter) and IBFp (with ISFp as parameter).

The substrate is considered to have a depletion

capacitance (Csub), modeled in the same way as (eq.

20).

E. ESD-specific effects

Certain effects like the base-collector breakdown and

contacts self-heating are crucial for an ESD

simulation.

1. Avalanche breakdown

Unlike the case of a BJT, where a weak base-collector

avalanche model is used, the particularities of an

SCR's breakdown leads to a strong avalanche model:

BCbk IMM=I 1 (34)

cm

BCbk

BC

V

V=MM

1

1 (35)

where MM is the multiplication factor and VBCbk the

breakdown voltage; mc is the breakdown factor and

typically equal to 2. The expression (Eq. 18) was

linearised in order to avoid divergence.

2. Self heating

At high voltage pulses, the temperature modification

leads to an increase in the metal strips resistance [7]:

ΔT)TCR+(R=R 0 1 (36)

where R0 is the resistance before the self heating and

TCR represents the temperature coefficient resistance.

We can calculate the temperature increase knowing

the dissipated energy and the thermal capacitance:

ΔT(t)C=(t)E THR (37)

The energy is:

Δt

RRR (t)I(t)V=(t)E0

(38)

The thermal capacitance will be divided in two parts:

the thermal capacitance of the metal strips and the one

of the dielectrics enclosing it:

Vδ(t))c+(c=C+C=C DMTHDTHMTH (39)

tα=δ(t) D , (40)

with V representing the metal volume and αD

integrates the thermal diffusion coefficient and the

shape factors of heat conduction. A more detailed

approach is given in [7].

III. Characterisation and

parameter extraction The model has currently been tested in CMOS 40 nm

and CMOS 130 nm technologies.

Our parameters can be divided in three categories,

along the different necessary kinds of measurements:

DC, transient and high current (ESD).

A. DC parameter extraction

A high degree of similarity was kept between our

model’s parameter extraction strategy and BJT

techniques [9]. Classical set-ups were used for each

“transistor”.

The DC parameters are:

- basic current flow: ISn, ISp, IR, ISFn, ISFp, ISR,

ISpsub, ISRpsub

- low current recombination: ISEn, ISEp, ISC, NEn,

NEp, NC

- early voltages: VAFn, VAFp, VARn, VARp

- high injection beta degradation: IKFn, IKFp, IKRn,

IKRp

- resistances: REn, REp, RBn, RCp, RBp, RCn

IS and VAR are extracted from normalised collector

current plots (ICnormalised vs. VBE):

)exp(T

BE

C

normalized

V

V

IIC (41)

In a similar way, ISF is extracted from the normalised

base current plot. VAF is extracted from the forward

output plot (IC vs VC) (see Figure 6), taken at different

base current values. The same plot is used for

extracting the knee current.

All the other parameters are extracted using the

Gummel and beta plots (see Figure 7), in both forward

and reverse mode. As VAF extraction is not always

accurate - reverse output measurements should also be

done.

The parameters for the substrate pnp transistor are

extracted together with the lateral pnp.

Figure 6: Output characteristic for extracting the forward Early

voltage and knee current

Figure 7: DC beta (A.) and Gummel (B.) plots used for extracting

bipolar parameters for the pnp BJTs and substrate parasitic.

B. Transient/overshoot

Capacitances parameters (CJ, VJ and mj) were

extracted using classical C-V measurements.

On the other hand, for the transient time related

parameters, the extraction methods were adapted to

using ESD specific transient measurements, as shown

in Figure 8. Even though the procedure is not very

rigorous, it offers a sufficient level of accuracy,

saving characterization and extraction time. The

measurements were done using an internally

developed Very Fast Transient Characterization

System (VF-TCS) setup [8]. Multiple transient

measurements, taken at different voltage amplitudes,

are required. For the transit time, a plot taken just

after the trigger is used. Transit time is given by the

Figure 8: VFTCS waveform of anode voltage: measurement (red)

vs. model (black)

Figure 9: VFTCS overshoot measurement (red) vs. model (black)

obtained from transient plots

0

0.0005

0.001

0.0015

0.002

0.0025

0 1 2 3 4

I CE

[A]

VCE [V]

measurement

model

0

0.2

0.4

0.6

0.4 0.7 1 1.3

bet

a

VBE [V]

IB [

A]

VBE [V]

pnpmeas…

0

1

2

3

4

5

6

7

8

9

10

1.00 5.00 9.00 13.00 17.00

VA

[V

]

time [ns]

measurement

model

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0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

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I A[A

]

VA [V]

measurement

model

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1

2

3

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0,00 5,00 10,00 15,00

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[V]

time [ns]

model

measurement

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1

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0,00 5,00 10,00 15,00

VA[V

]

time [ns]

A. B.

width of the overshoot. For the high-current

behaviour, the IT and VTF parameters are tuned.

XTF can be considered equal to 10. Also, the model

can be simplified by combining the npn and pnp

effects (a factor of 2 between them – for instance

FnFp TT 2 – can be used with good results).

Although the accuracy of the extraction is not very

important, taking into account these effects is capital

for the prediction of the overshoot.

A final optimization should be done on an over-shoot

plot, obtained from multiple VF-TCS transient

measurements as shown in Figure 9. The graph plots

the peak value of the voltage versus the average on

the stable period of the current. The optimised

parameters are CJC, VJC and ITF.

The above plots were obtained by measuring a SCR

with a 50 Ω resistance connected to the NW, in order

to force the triggering through the pnp transistor

(similar to the real operation circuit - see Figure 10 A)

C. TLP - quasi-static

Quasi-static I-V characteristics were obtained using

classical TLP (Transmission Line Pulse) and VFTCS

setups. Each point of the characteristic is obtained by

averaging a transient measurement (and simulation)

during its stable period (between 5 ns to 10 ns in

Figure 9). Two ways were used for turning the device

on:

by turning on the pnp bipolar using a 50 Ω

resistance connected to the Nwell (Figure 11),

by turning on the npn bipolar by using a 50 Ω

resistor connected to the Pwell (Figure 13).

The 50 Ω resistors were used in order to simulate the

trigger environment.

Figure 10: Set-up with external resistance. A - Nwell grounded

through a 50 Ω resistor, B - Pwell grounded through a 50 Ω

resistor.

These measurements show the real behaviour of the

whole SCR.

Figure 11: Quasi-static TLP 9 ns measurement (red) vs. model

(black) with a 50 Ω resistance connected to the Nwell in the

CMOS 040μm technology

Figure 12: Quasi-static TLP 9 ns measurement (red) vs. model

(black) with a 50 Ω resistance connected to the Nwell in the

CMOS 040μm technology - logarithmic scale (details on

triggering)

Both of the triggering mechanisms - through the npn

(Figure 11) and through the pnp (Figure 13) - are

necessary to validate the model, especially the

resistances. It may happen that one of the two fit very

well the measurements while the other cannot predict

the triggering point. As many parameters require

manual tuning, it is important to have different turn-

0.001

0.01

0.1

1

10

0.5 1 1.5 2 2.5

I A[A

]

V A[V]

on configurations in order to assure that their value is

not artificial.

Figure 13: Quasi-static TLP 9 ns measurement (red) vs. model

(black) with a 50 Ω resistance connected to the Pwell in the

CMOS 040μm technology

Figure 14: Quasi-static TLP 9 ns measurement (red) vs. model

(black) with a 50 Ω resistance connected to the Nwell in the

CMOS 130μm technology

The graphs obtained from the VFTCS characterization

offer a good resolution around the trigger point, but

are not suitable for high current characterization.

They are used for the validation and fine tuning of the

DC and transient parameters extracted before.

The TLP characterisation is used to optimize the self-

heating parameter and validate the high-current part of

the model.

The Quasi-static I-V characteristic for an SCR in a

CMOS 40 nm technology is given in Figure 11 and

Figure 13 and for a CMOS 130 nm technology in

Figure 14. The agreement between measurement and

simulation results is very good. This is a validation of

the developed model.

IV. Model complexity impact on

scalability We have stated that one of the reasons leading to the

development of a new, more physical model was the

perspective of accurate and simple scaling laws.

Although it is not the purpose of this paper to present

a scalable model, we will show the needs of modeling

some of the effects.

We will use three different SCRs, with the only

variable parameter being the length of a finger (Figure

2) – w. We will call the three SCRs SCR1, SCR2 and

SCR3, with their finger length w1, w2=1.5w1 and w2 =

2w1.

For the saturation current we assumed a dependence

on both the area and the perimeter of the electrode

(emitter for the internal transistor):

PJAJI PA (42)

A is the area of the emitter and P its perimeter. JA and

JP represent current densities. They are extracted

using two SCR1 and SCR3 (two equations for two

unknown values). SCR 2 is used for validation. One

of the most important parameters is, however, the well

resistance. They play a very important role in

predicting the triggering voltage and current.

Using the complete model presented above, we

extract the Pwell resistance of each SCR:

Table 1: PW resistance variation with the geometry – parameter

individually extracted

Device SCR1 SCR2 SCR3

Finger length w1 1.5 x w1 2 x w1

-4.50

-4.00

-3.50

-3.00

-2.50

-2.00

-1.50

-1.00

-0.50

0.00

-4 -3 -2 -1 0

I A[A

]

VA [V]

measurement

model

0.00

0.50

1.00

1.50

2.00

2.50

0 2 4 6

I A[A

]

VA [V]

measurement

model

RBn 32 Ω 22 Ω 15 Ω

We can easily see that the parameters follow the

simple scaling law with respect of w:

w

RR w (43)

Now we will modify our model in order to ignore the

high injection beta degradation effect.

The other parameters can fit the quasi-static curve, but

they have to compensate the excluded effect. Thus, by

tuning the resistances, their values move away from

their first approximation. The extraction is also more

difficult, not being able to base ourselves on the

individual BJT plots to extract the resistances.

The newly obtained values (tuned in order to obtain a

fit on the quasi-static TLP plot of the SCR triggered

using a 50 Ω resistance connected to the Nwell –

Figure 11 A) are:

Table 2: PW resistance variation with the geometry – parameter

individually extracted – ignoring the high injection effects

Device SCR1 SCR2 SCR3

Finger length w1 1.5 x w1 2 x w1

RBn 47 Ω 34 Ω 28 Ω

In this case, the error of the scalability would be

significant by using (eq. 27), leading to the need of a

more complex (and artificial) scaling law.

Figure 15: Quasi-static TLP 100 ns measurement (red) vs. model

(blue) with a 50 Ω resistance connected to the Nwell in a CMOS

130nm technology – comparison between SCRs of different finger

lengths (w and 2w)

The artificial character of the tuned parameters can

also be seen from the following:

- the individual BJT plots do not fit any more;

- it is impossible (at the same time - with the

same set of parameters) to predict the trigger

of the SCR using a 50 Ω on the Pwell (Figure

11 B);

The latter would be however possible by tuning other

parameters – like the gain (ISF), but in this case they

lose their physical sense and break other scalability

laws, like (eq. 26).

Thus, although complicating the model with

secondary phenomena might not bring a capital gain

in ESD simulations’ precision, they are important for

determining a more correct value for all the

parameters and improve their scalability.

V. Conclusion A novel compact model for the ESD protection SCR

device has been developed. It is based on the

Gummel-Poon equations with emphasis on the

physics of the device. It has been validated on ST

CMOS 40 nm and CMOS 130nm technologies. The

parameter extraction strategy is simple, highly based

on BJT extraction techniques combined with ESD-

specific characterisation methods. It improves over

the existent work by adapting its equations to the SCR

particularities, most notably in the case of the base

charge. The latter’s further influence over the transit

time leads to a good overall prediction of the SCR’s

temporal, overshoot and quasi-static behaviour. Also,

being closer to the physical phenomena, the model

becomes very promising for scalability, this being the

next focus of our research.

Acknowledgements The authors would like to thank Hanen Boussetta

from ST Microelectronics Tunis for all the help in

designing the ESD protection devices. The authors

also wish to thank Godfried Notermans and Vasselin

Vassilev for their suggestions that helped making this

article better.

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Beckirch, C. Richier, and G. Troussier,

0,00

0,50

1,00

1,50

2,00

2,50

0 2 4 6

IA [A

]

VA [V]

SCR1 measurement

SCR1 model

SCR3 measurement

SCR3 model

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[2] L. Lou and J.J. Liou, “A comprehensive compact

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[3] Y. Zhou, J.-J. Hajjar and K. Lisiak, “Modeling

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