A NEW COMPENSATION TECHNIQUE FOR ENHANCING POWER SUPPLY REJECTION RATIO IN TWO-STAGE CMOS OPERATIONAL AMPLIFIERS BY SRI HARSH PAKALA, B.Tech A dissertation submitted to the Graduate School in partial fulfillment of the requirements for the degree Master of Sciences, Engineering Specialization in: Electrical Engineering New Mexico State University Las Cruces, New Mexico February 2012
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A NEW COMPENSATION TECHNIQUE FOR ENHANCING POWER
SUPPLY REJECTION RATIO IN TWO-STAGE CMOS OPERATIONAL
AMPLIFIERS
BY
SRI HARSH PAKALA, B.Tech
A dissertation submitted to the Graduate School
in partial fulfillment of the requirements
for the degree
Master of Sciences, Engineering
Specialization in: Electrical Engineering
New Mexico State University
Las Cruces, New Mexico
February 2012
“A New Compensation Technique for Enhancing Power Supply Rejection Ra-
tio in Two-Stage CMOS Operational Amplifiers,” a dissertation prepared by
Sri Harsh Pakala in partial fulfillment of the requirements for the degree, Mas-
ter of Sciences has been approved and accepted by the following:
Linda LaceyDean of the Graduate School
Chair of the Examining Committee
Date
Committee in charge:
Dr. Paul M. Furth, Associate Professor, Chair.
Dr. Jaime Ramirez-Angulo, Professor.
Dr. Abbas Gassemi, Professor.
ii
DEDICATION
Dedicated to my mother Gayatri, father Gopal Mani, sister Jyotsna, my
grandmother Suryakantham.
iii
ACKNOWLEDGMENTS
I would like to thank my parents Gayatri Kappaguntala and Hara Gopal
Mani Pakala for their support and their confidence. I am who I am because of the
way they brought me up. I would like to thank my sister Sirisha Sri Jyotsna Gorti
and my brother-in-law Gorti Narasimha Murty for being there for me during a
turbulent summer in 2010. I would like to thank my grandmother Suryakantham
Pakala for being the foundation stone for my family. Our family is in a good
position by the grace of the Almighty God and due to her perseverance.
I am forever indebted to my advisor Dr. Paul M. Furth. It is due to
him that I found the interest in Microelectronics. His teaching methods and
his treatment of students encouraged me to study harder during my graduate
program. Dr. Paul M. Furth also is a great human being and I would like to
thank him for inviting us to his residence for over a year during friday evenings.
I learnt a lot about him and his family during that time and I thank him for
trusting us and sharing his life with his students.
Great appreciation to Dr. Jaime Ramirez-Angulo for being a member of
my thesis committee. I like him as a professor and also as a human being. I learnt
a lot from all his courses and It woud be a dream to perform research with him.
I would like to thank Dr. Abbas Ghasemmi for accepting my request to
be a member of my thesis committee. He was the first professor to offer financial
support to me during the second semester. That greatly helped me as an Interna-
iv
tional student. He is an angel in NMSU and I am lucky to know such a brilliant
man.
Thanks to my cousins, Su,Teju,Sidhu,Puppy,Chelli,Keerthi and all my rel-
atives.
I would like to thank my undergraduate friends, Goutham, Vamsi, Swa-
roop, Santhosh, Anil, Revanth, Murali, Sushma, Saranya, Sherin, Rachana and
Priyanka.
I would also like to mention my buddies for life, Avinash, Rohini, Sharada,
Akhilesh and Shilpa. We have been a close-knit group for a decade and I shall
always miss not being with them.
I would like to thank my seniors in las cruces, Rajesh Satyavada, Chaitanya
mohan, Harish, Ramesh, Venkat, Annajirao and Punith. They taught me Cadence
and also many vital concepts (esp. Punith and his night lessons).
Thanks to my friends in las cruces, Venkat Harish Nammi, Nitya, Srikanth,
2011 - 2012 Nominated for Outstanding Graduate Student Award, NMSU,USA.
Experience
Graduate Research Assistant, Arrowhead Center, Entrepreneurship Institute, NMSU,Fall-2010, Spring 2011, Fall 2011, Spring 2012Graduate Research Assitant, Klipsch School of Electrical and Computer Engineer-ing, NMSU, Spring-2010
vi
ABSTRACT
A NEW COMPENSATION TECHNIQUE FOR ENHANCING POWER
SUPPLY REJECTION RATIO IN TWO-STAGE CMOS OPERATIONAL
AMPLIFIERS
BY
SRI HARSH PAKALA, B.Tech
Master of Sciences, Engineering
Specialization in Electrical Engineering
New Mexico State University
Las Cruces, New Mexico, 2012
Dr. Paul M. Furth, Chair
February, 2012
Thomas and Brown Hall, TB 207, 1:30 PM
CMOS operational amplifiers are used in various applications such as: low-
dropout voltage regulators, audio amplifiers, and filters. To ensure stability, fre-
quency compensation techniques are required. In most electronic devices, ripple
noise in supply line is unavoidable. Hence a robust noise performance at high
frequencies is required. A new compensation technique is applied to a two-stage
CMOS operational amplifier. The compensation is established by a capacitor con-
nected between the output node and the source node of the input differential am-
vii
plifier. The technique allows better performance in terms of unity-gain frequency
and Power Supply Rejection Ratio (PSRR) when compared to existing compensa-
tion techniques, such as Miller and cascode compensation. Operational amplifiers
using Miller, cascode and the proposed compensation methods were fabricated in
a 0.5 µm 2P3M CMOS process. The circuits operate at a total quiscent current
of 90µA with ±1.5V power supplies when driving a load of 20pF||20kΩ. Experi-
mental results show that the proposed compensation scheme increases unity-gain
frequency by 25% and improves PSRR from the positive rail by 22 dB and 26
dB at 3 MHz when compared to Miller and cascode compensation techniques,
The approach for analyzing the small signal model for the proposed com-
pensation scheme differs slightly when compared to the Miller and cascode com-
pensation schemes. Fig. 3.9 depicts the small signal diagram for tail compensa-
tion. In order to cleary model all the effects, the node VX has to be exposed in
the model. The compensation capacitor CT is placed between nodes VOUT and
VX . Here too, the effect of the feedback is modeled as −gm1VX . The feed-forward
path is modeled as Kgm1(VOUT -VX). The effect of the feedback is shown through
33
CC VOUT
o13r
OUTR’ OUT
C
(gm13 VDD -V1 )
VOUT
Kg
2m1
V
V1
o2r
C1
VOUT
-g
2
m1
ci
o1rDD
gm4
1
VY
Cgd
VDD
Figure 3.8: Small signal diagram of Cascode scheme for PSRR analysis.
(gm13 VDD -V1 )
VX
-gm1
VX
VOUT
Kgm1( )-VX
VDD
o1r
VDD
V1
o2r
C
gm2
1
CT
gm1
1
Cgd
11
VOUT
o13r
OUTR’ OUTC
1
Figure 3.9: Small signal diagram of tail scheme for PSRR analysis.
34
Table 3.8: Location of Poles and Zeros PSRR Cascode
Poles/Zeros Cascode Freq. (Hz)
ωp11
gm13ro13·ro1CC1.2k
ωp2gm13
C1160M
ωp3gm4
Cgd340M
ωz1gm1
2CM7.6M
ωz2gmC
Cgd340M
ωz3gm1gm13
C1CL800M
Table 3.9: Location of Poles and Zeros PSRR Tail
Poles/Zeros Proposed Freq. (Hz)
ωp11
gm13ro13·ro1Cgd25k
ωp22gm1
CT17.3M
ωp3gm13
C1150M
ωz1gm1
CT8.75M
ωz2gm13CT
2C1CL10M
ωz32gm1
CT17.3M
the connection of a voltage buffer of gain 1 between nodes VOUT and VX through
the 1gm1
source terminal of transistor M1. The pole-zero equations along with their
approximate frequency locations are given in Table. 3.9.
35
3.5 Simulation Results
All eight two-stage operational amplifier variants are designed and sim-
ulated in the ONSEMI 0.5µm CMOS process. DC, AC, transient and PSRR
simulations are done and the outputs are shown in the next subsections. The
results in each design configurations I, II and III are compared and presented in
Table. 3.10, 3.11 and 4.1.
+
Vout
+
-
RLCL
VSIN
+
-
Amplifier
RLargeCLarge
AC magnitude =1
Phase = -180
Figure 3.10: AC analysis test bench of two-stage operational amplifiers
3.5.1 AC Analysis
Frequency analysis of the amplifiers are done by breaking the loop of the
amplifier with a large resistor as shown in Fig. 3.10. The test bench has an AC
input source withAC magnitude set to 1 and phase set to 180o, such that the
phase plot starts from 0o. AC simulation is done for output load of 20pF||20kΩ.
The frequency plots of two-stage opamps in design I, design II and de-
sign III with Miller, cascode and proposed compensation schemes are shown in
Fig. 3.11, Fig. 3.12 and Fig. 3.13, 3.14, 3.15 respectively.
36
Figure 3.11: Frequency plots of Design I two-stage opamps with Miller Compen-sation and proposed Compensation.
3.5.2 Transient Analysis
Time-domain analysis is done using transient analysis. The amplifier is
tested in an inverting configuration. Two resistors of 40kΩ are used to have a
gain of unity to the amplifier. The positive terminal is connected to ground and
a 200kHz pulse signal is given as the input. The analysis is done for a load
of 20pF||40kΩ, and the waveforms are plotted. Metrics such as slew rate are
computed and used for comparing different designs.
The transient simulation outputs of two-stage opamps in design I, design
II and design III with Miller, cascode and proposed compensation schemes are
shown in Fig. 3.17, Fig. 3.18 and Fig. 3.19 respectively.
37
Figure 3.12: Frequency plots of Design II two-stage opamps with Miller Compen-sation, Cascode Compensation and proposed Compensation.
3.5.3 Bandwidth Analysis
The bandwidth of each opamp was obtained by simulating them in a similar
method to that of transient analysis. Here, an input of 100mV peak-peak is given
to the positive terminal of the opamp and the negative terminal through the 40kΩ
resistor is given to ground. The rms voltage is found and the frequency is increased
till output voltage is 3dB lower than at low frequencies. Since this is a gain of
two configuration, the measured frequency is doubled to obtain the bandwidth of
each opamp.
38
Figure 3.13: Frequency plots of Design III two-stages opamp with Miller compen-sation.
3.5.4 Power-Supply Rejection Ratio
Power-supply rejection ratio (PSRR) is used to find the attenuation of the
noise from the power-supply by the amplifier. The test bench for finding PSRR
is shown in Fig. 3.20. The inputs of the amplifier in the inverting configuration
is connected to ground and an AC sinusoidal signal source with 100mVPP is con-
nected in series with the dc power-supply. The frequency of the ac signal is varied
to calculate PSRR at different frequencies. The equation of PSRR is
PSRR+ = 20log(RippleSupplyRippleOutput
). (3.5)
The PSRR is plotted at various frequencie ranging from 100 Hz - 3 MHz, for
all the designs I, II and III two-stage operational amplifiers and summarized in
39
Figure 3.14: Frequency plots of Design III two-stages opamp with cascode com-pensation.
Table. 3.10. Simulated PSRR plots for design I, design II and design III are shown
in Fig. 3.21, 3.22, 3.23, 3.24, 3.25, 3.26.
40
Figure 3.15: Frequency plots of Design III two-stages opamp with proposed com-pensation.
Vout
+
-
RLCL
VIN
+
-
Amplifier
RF1RF2
+
200kHz step
input
Figure 3.16: Transient analysis test bench in inverting configuration.
41
Figure 3.17: Transient output of Design I two-stage opamps with Miller compen-sation and proposed compensation schemes.
42
Figure 3.18: Transient output of Design II two-stage opamps with Miller compen-sation, cascode and proposed compensation schemes.
43
Figure 3.19: Transient outputs of Design III two-stage opamps with Miller, cas-code and proposed compensation techniques.
Vout
+
-
RLCL
VIN
+
+
-
Amplifier
RF1RF2
+
VSIN
+
-
Figure 3.20: Test bench for measuring PSRR.
44
Figure 3.21: Frequency plots of PSRR for Design I opamps using Miller andproposed compensation schemes.
Figure 3.22: Frequency plots of PSRR for Design II two-stage opamps using Miller,cascode and proposed compensation schemes.
45
Figure 3.23: Frequency plots of PSRR for Design III two-stage opamp using millercompensation technique.
Figure 3.24: Frequency plots of PSRR for Design III two-stage opamp using cas-code compensation technique.
46
Figure 3.25: Frequency plots of PSRR for Design III two-stage opamp using pro-posed compensation technique.
Figure 3.26: Frequency plots of PSRR for Design III two-stage opamp using pro-posed compensation technique.
47
Table 3.10: Simulated Results for Design I two-stage opamps
Parameters Miller proposed
Power supply ±1.5V ±1.5V
Dc gain 60dB 60dB
Bandwidth 4.6MHz 7.8MHz
Phase margin 61.2o 61.3o
RL 20kΩ 20kΩ
CL 20pF 20pF
CC 1.8pF 2.3pF
SR + /SR− (V/µs) 4.4/1.04 4.2/1.5
PSRR @1kHz 72.9dB 72.4dB
PSRR @500kHz 53.6dB 53.1dB
PSRR @1MHz 33.6dB 32.9dB
48
Table 3.11: Simulated Results for Design II two-stage opamps
Parameters Miller Cascode proposed
Power supply ±1.5V ±1.5V ±1.5V
Dc gain 63dB 63dB 63dB
Bandwidth 4.6MHz 7.7MHz 7.7MHz
Phase margin 60.9o 61.5o 61.7o
RL 20kΩ 20kΩ 20kΩ
CL 20pF 20pF 20pF
CC 1.85pF 1.72pF 2.35pF
SR + /SR− (V/µs) 4.3/1.04 5.0/1.08 4/1.08
PSRR @1kHz 72.9dB 72.4dB 79.3dB
PSRR @500kHz 53.6dB 53.1dB 61.0dB
PSRR @1MHz 33.6dB 32.9dB 41.2dB
49
Table 3.12: Summary of Results with a supply voltage of ±1.5V of Design IIITwo-stage Opamp
Parameter/Design Miller Cascode proposed
RC , CC 15kΩ, 1.25pF -, 1.55pF -, 2.75pF
ADC (dB) 63.6 63.6 63.6
Bandwidth (MHz) 5.9 8.2 10.6
Phase Margin 62.9o 63.0o 62.7o
RL 20kΩ 20kΩ 20kΩ
CL 20pF 20pF 20pF
SR+/SR- (V/µs) 6.3/2.9 5.8/3.0 3.4/5.1
PSRR+ @ 1kHz (dB) 74.4 74 76
PSRR+ @ 100kHz (dB) 44 40 66
PSRR+ @ 3MHz (dB) 14 8 36
50
Chapter 4
EXPERIMENTAL RESULTS
Layout of all the amplifiers, a micrograph of the fabricated chip and hardware
results are discussed in this chapter.
4.1 Layout
Figure 4.1: Overall chip layout.
51
The overall chip layout, consisting of Design I (Miller and tail), Design
II (Miller, cascode and tail) and Design III (Miller, cascode and tail) two-stage
opamps are shown in Fig. 4.1. On the left side of the chip, eight two-stage opamps
(design I, design II and design III) are laid out in closed-loop configurations. The
resistors used for the closed-loop setup are two 40kΩ resistors. The right side
of the chip consist of the eight opamps in open-loop configuration. The rest of
the chip is filled with substrate contacts and metal layers as per the requirements
for submitting the chip to MOSIS. There are VDD and VSS that are used for the
padring and open-loop amplifiers. There is a second set of VDD and VSS for the
closed-loop opamps. All 40-pins were utilized carefully to be able to test each
block individually. The supply and output wires are laid out with extra width as
they carry the maximum currents.
Figure 4.2: Layout of design I two-stage opamp with Miller compensation..
The layout of Design I two-stage opamp with Miller compensation is shown
in Fig. 4.2. The area of the amplifier is 136x63µm2.
The layout of Design I two-stage opamp with proposed tail compensation
is shown in Fig. 4.3. The area of the amplifier is around 155x58.8µm2.
The layout of Design II two-stage opamp with Miller compensation is shown
in Fig. 4.4. The area of the amplifier is around 176x74.5µm2.
52
Figure 4.3: Layout of design I two-stage opamp with Tail compensation.
Figure 4.4: Layout of design II two-stage opamp with Miller compensation.
The layout of Design II two-stage opamp with cascode compensation is
shown in Fig. 4.5. The area of the amplifier is around 169x74µm2.
The layout of Design II two-stage opamp with proposed tail compensation
is shown in Fig. 4.6. The area of the amplifier is around 199x74µm2.
The layout of Design III two-stage opamp with Miller compensation is
shown in Fig. 4.7. The area of the amplifier is around 179x74µm2.
The layout of Design III two-stage opamp with cascode compensation is
shown in Fig. 4.8. The area of the amplifier is around 181x75µm2.
The layout of Design III two-stage opamp with proposed tail compensation
is shown in Fig. 4.9. The area of the amplifier is around 210x74µm2.
53
Figure 4.5: Layout of design II two-stage opamp with Cascode compensation.
Figure 4.6: Layout of design II two-stage opamp with Tail compensation.
4.2 Test Apparatus
We used voltage supplies of ±1.5 V and ground to test the chip. An Agilent
5400 function generator is used to generate a 200 kHz pulse signal with a peak-to-
peak voltage of 1.6 V. A Hewlett Packard 54603B oscilloscope is used to observe
the waveforms of transient analysis as described in the test procedure shown in
APPENDIX A.
4.3 Hardware Test Results
The chip was fabricated in the 0.5µm 2P3M ONSEMI technology through
MOSIS. The chip was tested with supply voltages ±1.5V and an input bias current
of 10µA to all the amplifiers.
54
Figure 4.7: Layout of design III two-stage opamp with Miller compensation.
Figure 4.8: Layout of design III two-stage opamp with Cascode compensation.
Transient measurements were performed for the closed-loop amplifiers in
an inverting configuration and gain of one. Two integrated and carefully matched
40 kΩ resistors were used in the negative feedback to achieve unity gain. The
Figure 4.9: Layout of design III two-stage opamp with Tail compensation.
55
input is a 200 kHz square wave with peak-to-peak voltage of 1.6 V. All amplifier
types were tested with an external load of 40 kΩ and 20pF in parallel. Three of
the combination outputs are presented. The positive slew rate is measured as the
slope of the rising edge from 10% to 90% of output peak-to-peak voltage and the
negative slew rate is similar for the falling edge.
Figure 4.10: Hardware waveforms of Design III two-stage amplifiers with Miller,cascode and tail compensation schemes.
The time-domain response of the design III two-stage opamps in closed-
loop configuration of gain -1 V/V were measured and are shown in Fig. 4.10.
Though the positive going slew-rate of Miller and cascode schemes are marginally
faster, the negative going slew-rate of the proposed tail compensation scheme is
much faster when compared to those of Miller and cascode schemes.
The measured PSRR performance for Design III two-stage opamps are
shown in Fig. 4.11, 4.12, 4.13 and 4.14. The PSRR performance of all the schemes
are identical at low frequencies. Miller and cascode schemes portray similar pos-
56
itive supply noise rejection performance across a wide range of frequencies. The
proposed tail compensation performs exellent in this characteristic. At a high
frequency of 1MHz, the tail compensation has a PSRR gain of 44 dB, whereas the
Miller and cascode schemes have PSRR gains of 21 dB and 19 dB respectively.
The measured results of the opamps are summarized in Table 4.1.
Figure 4.11: Hardware PSRR frequency response outputs of Design III two-stageamplifier with Miller, cascode and tail compensation schemes.
Figure 4.12: Hardware PSRR frequency response outputs of Design III two-stageamplifier with cascode scheme.
57
Figure 4.13: Hardware PSRR frequency response outputs of Design III two-stageamplifier with tail scheme.
Figure 4.14: Hardware PSRR frequency response outputs of Design III two-stageamplifier with tail scheme.
58
Table 4.1: Summary of Measured Results of Design III Opamps with a supplyvoltage of ±1.5V while driving a load of 20kΩ||20pF
Parameter/Design Miller Cascode Tail
RC , CC 15kΩ, 1.25pF -, 1.55pF -, 2.75pF
UGF (MHz) 6.4 8.2 10.3
SR+/SR- (V/µs) 6.3/2.9 5.8/3.0 3.4/5.1
PSRR+ @ 1kHz (dB) 74.4 74 76
PSRR+ @ 100kHz (dB) 44 40 66
PSRR+ @ 3MHz (dB) 14 8 36
59
Chapter 5
DISCUSSION AND CONCLUSION
A novel compensation scheme is introduced in detail and verified for two-stage
opamps. Eight opamps were designed and simulated. Miller, cascode and the
proposed compensation technique were implemented with similar specifications.
In comparison, the new compensation technique exhibits a greater PSRR from
positive supply line by 22dB and 26dB at 100kHz than that achieved by Miller
and cascode compensation techniques, respectively. At 3MHz, the PSRR achieved
through the proposed compensation scheme is greater by 22dB and 28dB with
respect to Miller and cascode compensation schemes, respectively. The unity-gain
frequency was also improved to 10.3MHz from 6.4MHz for Miller and 8.2MHz for
cascode compensation techniques, respectively. The minimum slew rate achieved
through the proposed compensation technique is 3.4V/µs, while that measured for
Miller and cascode is 2.9V/µs and 3.0V/µs, respectively. The theoretical analysis
for small signal modeling and PSRR analysis was performed and presented in the
report. The theoretical pole/zero values are verified with simulated and measured
data. A summary of measured results of Design III Two-stage opamps are shown
Table 5.1.
5.1 Issues
The bias pin is shared between two sets of opamps, one closed-loop and
one open-loop. This leads to errors in the generated bias voltage. Measurement
60
Table 5.1: Summary of Measured Results of Design III Opamps with a supplyvoltage of ±1.5V while driving a load of 20kΩ||20pF
Parameter/Design Miller Cascode Tail
RC , CC 15kΩ, 1.25pF -, 1.55pF -, 2.75pF
UGF (MHz) 6.4 8.2 10.3
SR+/SR- (V/µs) 6.3/2.9 5.8/3.0 3.4/5.1
PSRR+ @ 1kHz (dB) 74.4 74 76
PSRR+ @ 100kHz (dB) 44 40 66
PSRR+ @ 3MHz (dB) 14 8 36
of PSRR in open-loop configuration was unsuccessful, which lead us to analyze
the opamps in closed-loop configuration.
5.2 Future Work
This compensation scheme was implemented on a two-stage opamp for the
purpose of verifying its feasibility. The amplifier can be improved by designing it
into a Class-AB amplifier. Also the usage of the proposed compensation scheme
for multi-stage opamps can be explored. Another possibility would be to design a
Low Dropout voltage regulator (LDO) using the proposed compensation scheme.
61
APPENDICES
APPENDIX A
Test Document
SriHarsh Pakala 800431266
Test Procedure
Pin Description Table:
P# Name Pad Type Pin Description
1. V_o_opn4 Protect Output of open loop design_2_casc/ opamp4 2. V_o_opn3 Protect Output of open loop design_2_miler/ opamp3 3. V_o_opn2 Protect Output of open loop design_1_tail/ opamp2 4. V_o_opn1 Protect Output of open loop design_1_miler/ opamp1 5. Vdd_opn Protect Vdd= +1.5V for all open loop opamps 6. V_in-_opn1 Protect Input of open loop design_1_miler/opamp1 7. V_in-_opn2 Protect Input of open loop design_1_tail/opamp2 8. V_in-_opn3 Protect Input of open loop design_2_miler/opamp3 9. V_in-_opn4 Protect Input of open loop design_2_casc/opamp4 10. Vdd_global Vdd Global Vdd connecting vdd power rail across chip 11. Vbias_1 Protect Vbias for both clsd & open loop design_1_miler/opamp1 12. Vbias_2 Protect Vbias for both clsd & open loop design_1_tail/opamp2 13. Vbias_3 Protect Vbias for both clsd & open loop design_2_miler/opamp3 14. Vbias_4 Protect Vbias for both clsd & open loop design_2_casc/opamp4 15. V_in+_clsd Protect Vin+ for all closed loop designs 1-8 16. Vdd_clsd Protect Vdd=+1.5V for all closed loop opamps 17. V_o_clsd_1 Protect Output of closed loop design_1_miler/opamp1 18. V_o_clsd_2 Protect Output of closed loop design_1_tail/opamp2 19. V_o_clsd_3 Protect Output of closed loop design_2_miler/opamp3 20. V_o_clsd_4 Protect Output of closed loop design_2_casc/opamp4 21. V_o_clsd_5 Protect Output of closed loop design_2_tail/opamp5 22. V_o_clsd_6 Protect Output of closed loop design_3_miler/opamp6 23. V_o_clsd_7 Protect Output of closed loop design_3_casc/opamp7 24. V_o_clsd_8 Protect Output of closed loop design_3_tail/opamp8 25. Vss_clsd Vss Vss= -1.5V for all closed loop designs 1-8 26. V_in-_clsd Protect Vin- for all closed loop designs 1-8 27. Vbias_5 Protect Vbias for both clsd &opn loop design_2_tail/opamp5 28. Vbias_6 Protect Vbias for both clsd & opn loop design_3_miler/opamp6 29. Vbias_7 Protect Vbias for both clsd & opn loop design_3_casc/opamp7 30. Vbias_8 Protect Vbias for both clsd & opn loop design_3_tail/opamp8 31. V_in-_opn5 Protect Input of open loop design_2_tail/opamp5 32. V_in-_opn6 Protect Input of open loop design_3_miler/opamp6 33. V_in-_opn7 Protect Input of open loop design_3_casc/opamp7 34. V_in-_opn8 Protect Input of open loop design_3_tail/opamp8 35. V_in+_opn Protect Vin+ input for all open loop designs 1-8 36. Vss_opn Vss Vss= -1.5V for all open loop designs 1-8 37. V_o_opn8 Protect Output of open loop design_3_tail/ opamp8 38. V_o_opn7 Protect Output of open loop design_3_casc/ opamp7 39. V_o_opn6 Protect Output of open loop design_3_miler/ opamp6 40. V_o_opn5 Protect Output of open loop design_2_tail/ opamp5
SriHarsh Pakala 800431266
Testbench for Transient Analysis:
Figure 1: Transient analysis testbench
Supply Voltages:
Vdd = 1.5 V
Vss = -1.5 V
Ibias = 10µA
Procedure:
1) Connect global Vdd (Vdd_global) (pin 10) and global Vss (Vss_opn) (pin 36) and check whether chip is good or fired up.
2) Connect closed loop Vdd (Vdd_clsd) (pin 16) to global Vdd (Vdd_global) (pin 10). 3) Connect global Vss (Vss_opn) (pin 36) closed loop Vss (Vss_clsd) (pin 25). 4) Connect Vin+ input for all closed loop designs (V_in+_clsd) (pin 15) to ground. 5) Connect Vin- input for all closed loop designs (V_in-_clsd) (pin 26) to the Function Generator with input
800mV peak-to-peak signal at a frequency = 200kHz. 6) Calculate and attach the bias resistor required for each op-amp design.
a) Closed loop design_1_miller/opamp1 i) Calculation of Rbias1: Vbias 1 = -397mV
!"#$%1 =!"" − !"#$%1
!"#$%
!"#$%1 = 190KΩ But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias1 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_1 (pin 11).
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SriHarsh Pakala 800431266
iii) Connect Vout_1 (pin 17) to RL=40KΩ and RL to ground.
b) Closed loop design_1_tail/opamp2 i) Calculation of Rbias2: Vbias 2 = -397mV
!"#$%2 =!"" − !"#$%3
!"#$%
!"#$%2 = 190KΩ
But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias2 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_2 (pin 12). iii) Connect Vout_2 (pin 18) to RL=40KΩ and RL to ground.
c) Closed loop design_2_miller/opamp3 i) Calculation of Rbias3: Vbias 3 = -397mV
!"#$%3 =!"" − !"#$%3
!"#$%
!"#$%3 = 190KΩ
But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias3 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_3 (pin 13). iii) Connect Vout_2 (pin 19) to RL=40KΩ and RL to ground.
But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias4 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_4 (pin 14). iii) Connect Vout_4 (pin 20) to RL=40KΩ and RL to ground.
But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias5 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_5 (pin 27). iii) Connect Vout_5 (pin 21) to RL=40KΩ and RL to ground.
But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias6 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_6 (pin 28). iii) Connect Vout_6 (pin 22) to RL=40KΩ and RL to ground.
But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias7 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_7 (pin 29). iii) Connect Vout_7 (pin 23) to RL=40KΩ and RL to ground.
But since each bias line is shared by 2 op-amps (one closed loop and the other open loop), we would need to use an Rbias8 = 95KΩ. ii) Connect 95 KΩ from Vdd (pin 16) to Vbias_8 (pin 30).
i) Connect Vout_8 (pin 24) to RL=40KΩ and RL to ground. 7) The outputs of opamps 1-8 are observed on the scope by connecting the outputs V_o_clsd1 – V_o_clsd8 of
each opamp to the scope to tabulate and measure the SR+ and SR- of each design.
1) Repeat steps 1 to 3 as in transient analysis testbench procedure. 2) Connect Vin+ (pin 15) to Function Generator with input signal of 100mV pk-pk at a frequency =
1kHz with an 1X probe. 3) Connect Vout_1 (pin 17) to RL=40KΩ and RL to ground. 4) Connect Vout_2 (pin 18) to RL=40KΩ and RL to ground. 5) Connect Vout_3 (pin 19) to RL=40KΩ and RL to ground. 6) Connect Vout_4 (pin 20) to RL=40KΩ and RL to ground. 7) Connect Vout_5 (pin 21) to RL=40KΩ and RL to ground. 8) Connect Vout_6 (pin 22) to RL=40KΩ and RL to ground. 9) Connect Vout_7 (pin 23) to RL=40KΩ and RL to ground. 10) Connect Vout_8 (pin 24) to RL=40KΩ and RL to ground. 11) In order to measure bandwidth, apply input signal through the Function generator and calculate Vrms
of each opamp’s outputs (Vout_1 to Vout_8). 12) Then calculate !1 = !"#$/ 2 and keep increasing the frequency of the input signal till the
output signal = !1. 13) The value of frequency obtained would then have to be doubled as the analysis is conducted with a
Testbench for Power Supply Rejection+ (PSR+) Measurement
Figure 3: Testbench for measuring PSRR+
Inputs: Both Vin+ and Vin- are grounded. Input given to Vdd pin = 100mV Output: connected to spectrum analyzer
Procedure:
1) Repeat steps 1 to 3 as in transient analysis testbench procedure. 2) Connect Vin+ (pin 15) and Vin- (pin 26) to ground. 3) Connect Vdd_clsd (pin 16) to function generator’s red (positive terminal) wire. 4) Connect negative terminal of function generator (black wire) to the +ve terminal of the D.C
power supply. 5) Ground the negative terminal of the D.C power supply. 6) Make sure to ground the Function generator, Oscilloscope and the Spectrum Analyzer to same
ground region. 7) In order to observe the outputs connect Vout_6 (pin 22), Vout_7 (pin 23) and Vout_8 (pin 24) to
the spectrum analyzer one at a time. 8) To measure till 100kHz Digital spectrum analyzer (Stanford Research SR770) can be used but
beyond that analog spectrum analyzer (HP 4195) was needed. 9) In order to measure using the HP 4195, a voltage buffer was used (LMC 6482). This buffer too
was tested with the spectrum analyzer at frequencies ranging from 1kHz to 1MHz, it’s effect observed and tabulated such that it could be considered to obtain final PSR values.
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SriHarsh Pakala 800431266
Freq. Vin (mVrms) Vout (m Vrms) Phase
dB
-‐0.3
100 67.6
65.8
inphase
-‐0.3 200 67.7
65.6
inphase
-‐0.3
500 67.6
65.6
inphase
-‐0.3 1k 70
68
inphase
-‐0.3
10k 70
67.5
inphase
-‐0.3 20k 67.4
65
-‐0.3
50k 13.6
12.8
-‐0.5 100k 13.5
11.6
lag -‐35 degrees
-‐1.31
200k 13.5
9.2
lag -‐45 degrees 3dB down -‐3.33
500k 33.3
10
-‐10.4 1M 68.5
5.1
-‐22.6
The dB value should be subtracted from figure shown on analyzer for each corresponding frequency.
10) Formula to convert dBm to dB: ! !"# = 20 log(!"#$ !"#$%&'())+ 10 !"
Ex: 73 dBm = 63 dB 11) In such a way PSR values were observed and tabulated for opamp6-8 through pins 22-24. 12) The 100mV input signal’s footprint in dB was observed to be -20 dB. 13) This value has to be subtracted from the figure shown on the analyzer. 14) Further normalization is performed by considering the 2X gain lost due to grounding of the input
terminals. Hence a 6dB has to be added to the values obtained after step 12. 15) The final PSR values are calculated and tabulated.
SriHarsh Pakala 800431266
Tail compensation/opamp8:
Freq. SR770 HP4195 (dBm) HP4195(dB)
Invert (inp@-‐20dB)+20dB
2x gain +6dB
subtract follower
final PSRR
10 20 50
100 200 500
1000 2000 5000 10k 20k 50k
100k 200k 500k 1M 3M
Cascode Compensation/opamp7:
Freq. SR770 HP4195 (dBm)
HP4195(dB)
Invert (inp@-‐20dB)+20dB
2x gain +6dB subtract follower
final PSRR
10
20
50
100
200
500
1000
2000
5000
10k
SriHarsh Pakala 800431266
20k 50k
100k
200k
500k
1M
3M Miller Compensation/opamp6:
Freq. SR770 HP4195 (dBm) HP4195(dB)
Invert (inp@-‐20dB)+20dB
2x gain +6dB subtract follower
final PSRR
10
20
50
100
200
500
1000
2000
5000
10k
20k
50k
100k
200k
500k
1M
3M
APPENDIX B
Maple
O O
(3)(3)
(4)(4)
O O
(2)(2)
(1)(1)
O O
A. Design III Miller Compensated Small Signal Analysis : Summary of DC Gain, Poles and Zeros