A Mixed-Signal/MEMS CMOS Co-Design Flow with MEMS-IP Publishing / Integration Che-Sheng Chen 1 ([email protected]), Louis Thiam 2 , Ahmed Hussein Osman 2 , Kuei-Ann Wen 1 , Long-Sheng Fan 3 1 Inst. Of Electronics, National Chiao Tung Univer sity, Taiwan 2 VCAD, Cadence Design System, Ltd, USA 3 Inst. Of NanoEngineering and MicroSystems, National Tsing Hua Unversity, Taiwan
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A Mixed-Signal/MEMS CMOS Co-Design Flow with MEMS-IP Publishing / Integration
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A Mixed-Signal/MEMS CMOS Co-Design Flow with MEMS-IP Publishing / IntegrationA Mixed-Signal/MEMS CMOS Co-Design Flow with MEMS-IP Publishing / Integration
MEMS electrical ports corresponding to silicon ports
Mechanical ports expressed in VHDLAMS displacement type
Advantages of HDL behavioral modelling for MEMS:
Multi-disciplinary language Multi-disciplinary language combining physics and combining physics and electrical quantitieselectrical quantities
Open standard to enable Open standard to enable re-use and flexible mixed-re-use and flexible mixed-signal simulation signal simulation environmentenvironment
Ability to create highly Ability to create highly parameterizable parameterizable component librariescomponent libraries
MEMS geometrical MEMS geometrical structure description can structure description can be part of the macro-modelbe part of the macro-model
Natural convergence Natural convergence toward mixed-signal and toward mixed-signal and digital verificationdigital verification
MEMS HDL Macro-Modeling (2)Describing multi-physics equivalence with electricalMEMS HDL Macro-Modeling (2)Describing multi-physics equivalence with electrical
Expression of external force induced on the proof mass due to acceleration and electrostatic interaction of proof mass in motion
Electrical behaviour implemented as induced capacitance on electrical ports
Each physical equations can be stated independently and HDL concurrent process statement enables system solution convergence
No limit to describe 2nd, 3rd order effects but at expense of development time
Models can be further enhanced based on results extracted from FEM simulation
SIPP-SIMPLI Subflow conceptIP publishing and integrationSIPP-SIMPLI Subflow conceptIP publishing and integration
SIPP-SIMPLI (SIPP MEMS PLatform Integrator)
MEMS Design Sub-flow
MEMS/Mixed-Signal Design Sub-flow
CM
OS
ME
MS
Fou
ndry
Des
ign
Kit
IC S
ystem S
pecifications
Functional Validation Physical Integration
ME
MS
Specifications
GU
I
GU
I
Encrypted Electrical-Mechanical Model
Electrical Parasitic Network
Silicon Calibrated Model
MEMS Black-box Abstract
Black-box Physical Verification
Layout Sign-Off
Inte
grat
ion
/ Pub
lishi
ng
SIPP-SIMPLI MEMS IP Publishing SubflowAutomated approachSIPP-SIMPLI MEMS IP Publishing SubflowAutomated approach
Auxiliary Virtuoso not shipped
Required MEMS IP input files
SIMPLI Library Processor
Spice, Spectre
coupled C Netlists
Layout View
Target PDK
Specification Files
LEF Files
GDSII Files
Symbol Generation
Layout Generation
DRC
Coupled C extraction
Abstract Generation
Symbol View
Black-boxing
Abstract View
Layout GDSII File
Abstract LEF File
Assura customization
Functional View
Encrypted Functional
File
Functional Description
Files
CDL Netlist
Measurement Files
CDL Black-box
Spectre Black-box
Spice Black-box
Functional View
SIPP-SIMPLI operated on standard inputs and generates views required for Mixed-Signal design within Cadence environment
SIPP-SIMPLI requires following Cadence tools: AMS Incisive for AMS Incisive for
processing HDL processing HDL modelsmodels
Abstract Generator Abstract Generator for black-box layout for black-box layout generationgeneration
Assura for MEMS Assura for MEMS DRC compliance DRC compliance
QRC for MEMS QRC for MEMS parasitics extraction parasitics extraction
SIPP-SIMPLI MEMS IP Integration SubflowAutomated approachSIPP-SIMPLI MEMS IP Integration SubflowAutomated approach
Only Virtuoso views have to be re-created in target PDK which might be packaged differently between MEMS IP provider and end-user
If PDK package identical between MEMS IP provider and IC designer then MEMS IP published by SIPP-SIMPLI can be re-used as-is
Required MEMS IP package
SIMPLI Library ProcessorTarget PDK
Symbol Generation
Abstract Generation
Symbol View
Black-boxing
Abstract View
Assura customization
CDL Black-box
Spectre Black-box
Spice Black-box
Functional Functional View
SIMPLI MEMS Package
SIPP-SIMPLI Virtuoso Custom InterfaceSingle interface for publishing and integrationSIPP-SIMPLI Virtuoso Custom InterfaceSingle interface for publishing and integration
Single interface and options for both publishing and integration
Interface integrated directly with Virtuoso platform and compatible with both IC 5.1.41 and IC 6.1.3
Support batch processing through SKILL APIs for entire library management and maintenance
SIPP-SIMPLI Layout ProcessingLayout black-boxing while enabling accurate integrationSIPP-SIMPLI Layout ProcessingLayout black-boxing while enabling accurate integration
Before After
SIP
P-S
IMP
LI
Abstract with antenna information
SIPP-SIMPLI Functional ProcessingHDL description encrypted while enabling accurate simulationSIPP-SIMPLI Functional ProcessingHDL description encrypted while enabling accurate simulation
Before After
SIP
P-S
IMP
LI
RSA encrypted code readable in AMS Designer
SIPP-SIMPLI Extraction ProcessingLayout extraction while enabling accurate parasiticsSIPP-SIMPLI Extraction ProcessingLayout extraction while enabling accurate parasitics
Before After
SIP
P-S
IMP
LI
Vibrating sensor floating in air dielectric
Sensor harness connecting to normal CMOS substrate
CDS circuit is suitable for capacitive sensor readout Offset cancellation & Low frequency noise reductionOffset cancellation & Low frequency noise reduction Suitable for following Analog to Digital conversionSuitable for following Analog to Digital conversion Following another S/H amplifier for proper sensitivityFollowing another S/H amplifier for proper sensitivity
Process: UMC CMOS-RF 180nm
Schematic Capture of Monolithic IntegrationSchematic Capture of Monolithic Integration
Accelerometer mechanical inputs stimuli through inherited connections
System output
Parameterizable accelerometer suitable for both simulation optimization and schematic-driven layout
Switched-cap sampling clock
Schematic-Driven Layout AssemblyHierarchical layout while reducing LVS errorsSchematic-Driven Layout AssemblyHierarchical layout while reducing LVS errors
MEMS accelorometer as abstract
Opened MEMS connections
Readout as plain footprint
List of nets that are completed routed.
Schematic-driven layout enables to track connectivity between schematic and layout view
SIPP-SIMPLI creates a connectivity aware view for safe layout integration
Custom router could be leveraged since MEMS black-box as connectivity and antenna information
SIPP-SIMPLI has also LEF file for digital P&R integration
Design SummaryDesign Summary
Specifications Conditions Value UnitSensor Input Range ±2 g
Sampling Freq. <100 kHz
Sensitivity Vsupply = 3.3v 218 mv/g
SFDR Vsupply = 3.3v 58.5 dB
Resonate Freq. 6.3 kHz
Output RMS Noise < 4kHz Vsupply = 3.3v 141 uV
Current Consumed Vsupply = 3.3v
Clock Freq. = 100KHz
360 uA
[2] Movement of the fingers triggered by external voltage source
[1] SEM of the ACC
The first result of accelerometer (ACC) fabricated with .18m 8” CMOS foundry under the constrain of standard CMOS process.
[3] Capacitance variation under the excitation of shaker with 20~8kHz shaking. ( The green one is the "PZT reference accelerometer“ provided as the reference and the blue one is the performance of DUT.)