A Low Noise CMOS Voltage Reference A Thesis Presented to The Academic Faculty by William Timothy Holman In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in Electrical Engineering Georgia Institute of Technology October 7, 1994 Copyright c 1994 by William Timothy Holman
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or 95.45%. If the offset voltage of a single amplifier is multiplied by a factor n in a
standard bandgap reference topology, the standard deviation will be multiplied by the
same factor. If n = 3, the value of F(VOS) for this example becomes
F VOS( ) = Φ23
− Φ −
23
≈ 0.74857 −0.25143 = 0.49714 (4-22)
or 49.71% . In other words, multiplying the input offset voltage of a single amplifier by a
factor of three decreases the probability that the output offset voltage will be less than or
equal to 1 mV from 95.45% to 49.71%.
100
Now consider the buffer amplifiers in the summing subcircuits of the ∆VBE
summing bandgap reference. The offset voltage at the reference output due to the input
offset voltages of the buffer amplifiers will be
VOFFSET = VOS1 + VOS2 + . . . + VOSn (4-23)
where n is the number of ∆VBE summing subcircuit stages. Assuming each input offset
voltage is an independent random variable [43], the probability function for the output
offset voltage of equation (4-19) becomes
F VOFFSET( ) = ΦVM
n σ
− Φ −
VM
n σ
. (4-24)
Unlike the multiplication of a single input offset voltage, summing n input offset voltages
results in a multiplication of the standard deviation by a factor of n . In other words,
summing versus multiplication gives the same n advantage for output voltage variations
due to device mismatch as it does for output noise. Returning to the previous example,
the probability that the total offset voltage of three ∆VBE summing subcircuit stages will
be less than or equal to 1 mV will be
F VOFFSET( ) = Φ23
− Φ −
23
≈0 .87493−0.12507 = 0.74986 (4-25)
or 74.99%, far better than the 49.71% probability if a single ∆VBE summing subcircuit
stage were multiplied by a factor of three. This argument can be extended for any
101
randomly distributed component parameter that is duplicated between the ∆VBE
summing subcircuits.
102
CHAPTER V
THE ∆VBE SUMMING BANDGAP REFERENCE
Given the measurement results for the lateral PNP transistors and DBiLNA
operational amplifiers fabricated in the MOSIS 1.2 µm CMOS process, creation of a
∆VBE summing bandgap reference circuit appeared feasible. Initially, a single ∆VBE
subcircuit was fabricated as a test structure. After confirming the functionality of this
subcircuit, a complete bandgap reference was fabricated and tested. This chapter
summarizes the experimental results of the circuit and compares them to circuit
simulations made with PSpice [44].
Layout and Fabrication
Figs. 5-1 and 5-2 are the schematics for the low noise bandgap reference and
∆VBE summing subcircuit, respectively. This circuit is essentially identical to the
proposed circuit in Chapter III, with the major exception that the PFET current mirrors in
the bias circuit and summing subcircuits have been cascoded. Equation (3-26) in Chapter
III shows that the output voltage of the ∆VBE summing bandgap reference is independent
of the bias current to the first order. Because PMOS transistors in the MOSIS 1.2 µm
CMOS process have a large lambda and low output resistance, these devices were
cascoded not because of concerns of drain current variation, but instead to increase the
internal loop gain and power supply rejection of the PTAT bias circuit [6]. The penalty
for stacking these PMOS transistors is a higher minimum supply voltage for the bias
circuit. The diode-connected LPNP transistor D1 was biased at 10% of the quiescent
current of the ∆VBE summing subcircuits (exclusive of additional current required to
103
operate the buffer amplifiers). Given the results of preliminary simulations, a value of 13
KΩ was chosen for the R1 resistor in the summing subcircuit, and four ∆VBE summing
subcircuits were placed on the chip. To minimize process variations and thermal gradient
effects, the four subcircuits were placed in a mirrored four-quadrant configuration.
A simple means of trimming the output voltage was also required for this circuit.
The reference voltage is easily adjusted by changing the value of resistor R1B in the
PTAT bias circuit, which in turn alters the magnitudes of currents through diode D1 and
the ∆VBE summing subcircuits. As shown in the circuit pin-out of Fig. 5-3, four different
R1B resistors in the range of 300 Ω to 550 Ω were placed on-chip in the hope that one of
them would be fairly close to the desired value for minimum reference temperature
coefficient. Unfortunately, all of these values ultimately proved to be too small, and
external resistors were used for the R1B resistor.
Subsequent testing and examination of the packaged circuit received from MOSIS
revealed an unanticipated problem with the circuit layout. Because of the need to
connect nodes in the circuit to external pads, long runs of metal1 and metal2 were used
throughout the circuit. At the time the chip was submitted for fabrication, little
consideration was given for the parasitic resistance of these metal traces, but these
resistances ultimately proved to be quite significant given the large quiescent currents and
high desired resolution of the reference voltage. According to the parametric
measurements for the MOSIS 1.2 µm CMOS process, metal1 and metal2 have typical
resistances of 0.05 Ω and 0.04 Ω per square, respectively. Some metal traces only a few
µm in width run as far as 1.2 mm across the surface of the chip, with resulting parasitic
resistances as high as 40.63 Ω.
104
. . .
10X
150
µm/
3.6
µm
150
µm/
3.6
µm
150
µm/
3.6
µm
150
µm/
3.6
µm
500
µm/
3.6
µm50
0 µm
/3.
6 µm
200
µm/
3.6
µm
200
µm/
3.6
µm XD
1
BIA
S
VIN
VO
UT
BIA
S
VIN
VO
UT
BIA
S
VIN
VO
UT
VR
EF
VD
D
∆V
BE
Sub
ckt
∆VB
E S
ubck
t
∆VB
E S
ubck
t
VD
DV
DD
VD
D
M3
M3
A
VD
D
M1
M1 A
M2
M2
A
R1B
Q2B
Q1B
M4
M5
1
5
6
2 4 78
9
10
3
11
12
13
Not
e: C
ircl
ed n
umbe
rs d
enot
e PS
pice
nod
es.
Fig. 5-1. The ∆VBE Summing Bandgap Reference
105
-
+
106
98
98
105
104
100
99
99 99
98
2000 µm / 3.6 µm
13 KΩ
10X
OUT
IN
98
99
Note: Circled numbers denote PSpice nodes.
101
103
2000 µm / 3.6 µm
M P1
MP2
VDD
VDD
VDD
V DD
VSSVSS
VSSVSS
102
R1
XA1
XD2 XD3
Fig. 5-2. The ∆VBE Summing Subcircuit
106
D1
D2
M13
0
M16
0
M14
0M
160
10X
150/
3.6
150/
3.6
500/
3.6
500/
3.6
M0
200/
3.6
Pin
24 P
in 1
5 pF
Pin
25
Pin
28
Pin
27
XD
10P
in 1
Pin
34
M14
0AM
160A
150/
3.6
150/
3.6
M0A
200/
3.6
Pin
33
Pin
26
Pin
29
Pin
30
Pin
31
Pin
32
300
Ω35
0 Ω
475
Ω55
0 Ω
Pin
34
Fig. 5-3. Chip Pin-Out for the ∆VBE Summing Bandgap Reference
107
-+ DB
iLN
A #
1V
DD
VSS
Pin
19
Pin
20
Pin
1
Pin
23
Pin
18
Pin
35 C
omp
M2A
2000
/3.6
XD
3AX
D4A
10X
Pin
26
Pin
20
P
in 2
0
Pin
1
Pin
21
Pin
1
M1A
2000
/3.6
Pin
25
Pin
20
Pin
22
13 K
Pin
1
-+ DB
iLN
A #
2V
DD
VSS
Pin
16
Pin
15
Pin
1
Pin
12
Pin
17
Pin
11C
omp
M2B
2000
/3.6
XD
3BX
D4B
10X
Pin
26
Pin
15
P
in 1
5
Pin
1
Pin
14
Pin
1
M1B
2000
/3.6
Pin
25
Pin
15
13 K
Pin
1Pin
13
Fig. 5-3 (cont). Chip Pin-Out for the ∆VBE Summing Bandgap Reference
108
-+ DB
iLN
A #
4V
DD
VSS
Pin
2P
in 4
0
Pin
1
Pin
37
Pin
3
Pin
36 C
omp
M2D
2000
/3.6
XD
3DX
D4D
10X
Pin
26
Pin
40
P
in 4
0
Pin
1
Pin
39
Pin
1
M1D
2000
/3.6
Pin
25
Pin
40
Pin
38
13 K
Pin
1
-+ DB
iLN
A #
3
VD
D
VSS
Pin
5P
in 6
Pin
1
Pin
7
Pin
4
Pin
8
Com
p
M2C
2000
/3.6
XD
3CX
D4C
10X
Pin
26
Pin
6
Pin
6
Pin
1
Pin
9
Pin
1
M1C
2000
/3.6
Pin
25
Pin
6
Pin
10
13 K
Pin
1
Fig. 5-3 (cont). Chip Pin-Out for the ∆VBE Summing Bandgap Reference
109
As shown in Figs. 5-4 and 5-5, the most critical metal pathways occurred either in
the circuit ground node or between the D2 diode-connected LPNP transistor and the
buffer amplifier output in the ∆VBE summing subcircuits. The effects are dramatic:
given the nominal 10 mA supply current of the circuit, simulations at 27 ˚C indicate a 67
mV increase in reference voltage due to parasitic ground resistances, and a 27 mV
increase in the total PTAT voltage generated by the ∆VBE summing subcircuits. These
error voltages are simply too large to ignore in a practical bandgap reference design. On
the other hand, the parasitic resistances could be dramatically reduced in a layout with no
external nodes, reduced quiescent current, and widened metal traces. Future submissions
of the ∆VBE summing bandgap reference will address these issues. Despite the error
voltages, it was still possible to obtain good temperature coefficient and output noise
results from the circuit. Every parasitic voltage drop in the circuit is either PTAT or
IPTAT, and as such can be canceled by adjusting the PTAT or IPTAT voltages used to
generate the bandgap reference voltage.
1.581 Ω
9.473 Ω
5.301 Ω
1.446 Ω 3.600 ΩTo PTATBias CircuitGround
To SummingSubcircuit #3Ground
To SummingSubcircuit #1, #2 Grounds
To VBE1 Generator Circuit Ground
Fig. 5-4. Parasitic Ground Resistances in the Bandgap Reference Layout
110
-
+VIN
D2
A1
V IN
11.97 Ω, 9.58 Ω, 4.25 Ω
40.63 Ω,22.74 Ω,25.98 Ω
Fig. 5-5. Parasitic Resistances in the ∆VBE Summing Subcircuit
Fig. 5-6 is a photograph of the fabricated ∆VBE summing bandgap reference as
received from the MOSIS service. The entire circuit requires about 1.70 mm2 of chip
area, although the bias circuit on the bottom half of the chip would certainly be arranged
more compactly in a production layout. Most of the compromises in layout efficiency
were a direct result of the need to bring out individual circuit nodes to external pads.
Note the symmetrical four-quadrant layout configuration for the ∆VBE summing
subcircuits. These subcircuits are dominated by the DBiLNA buffer amplifier structures,
which take up a total area of 0.864 mm2, more than half the reference circuit size.
However, as mentioned in the previous chapter, the DBiLNA amplifier is extremely
inefficient in terms of area and power consumption for this particular application. In the
first place, each amplifier has an individual bias circuit. A single bias circuit for all four
buffer amplifiers would be sufficient. The gain-bandwidth is too high, leading to
instability in unity-gain configuration unless a 20 pF external compensation capacitor is
used in addition to the 3 pF internal compensation capacitor. Most importantly, the
111
output stage of the DBiLNA maintains a quiescent current of more than 1 mA through
the push-pull output stage. Because the buffer amplifier in the summing subcircuit only
needs to sink current and never source it, the PMOS output device could be removed
without a performance penalty. Overall, the DBiLNA area and quiescent current
requirements could be dramatically reduced in future submissions by redesigning the
output stage and using a common bias circuit. Some type of cascode amplifier topology
with lateral PNP input transistors may prove to be the best solution for this particular
application.
112
Fig. 5-6. Photograph of the Fabricated ∆VBE Summing Bandgap Reference
113
Simulation of the ∆V BE Summing Bandgap Reference
Simulating the reference circuit proved more challenging than originally
anticipated. The simulations in this chapter were made after the fabricated bandgap
reference was tested in order to provide a correlation between the PSpice models and
actual working hardware. Critical layout resistances in high current pathways were
added to the subcircuits in the simulation. The average temperature coefficients of the
internal polysilicon resistors and external metal film resistors were measured and found
to be 834 ppm / ˚C and -16 ppm / ˚C, respectively. However, the most difficult
component to simulate proved to be the lateral PNP transistor. Ideally, the lateral PNP
should be simulated as a dual collector device, or at the very least as a vertical transistor
and lateral transistor with common base and emitter contacts. Unfortunately, PSpice
contains no dual collector transistor models, and there is no simple way to separate the
individual base currents of the vertical and lateral devices in a two transistor model.
Characterization of the vertical PNP transistor without the lateral collector connected was
not sufficient, since the performance of the vertical device proved to be correlated to the
lateral device. The simplest solution was a standard PNP transistor model with a
dependent current source connected to the collector terminal (Fig. 5-7). The current
source sinks a fraction of the total emitter current to simulate the vertical collector, and
the remaining current becomes the lateral collector current. The main drawback is that
the model is valid only for a particular bias point, and therefore multiple models must be
used in the simulation.
Even with the lateral PNP macromodels, parasitic resistances, and component
temperature coefficients taken into account, the final model-to-hardware correlation
proved only partially satisfactory. Precise matching of DC bias voltages and currents
along with simultaneous matching of noise and temperature performance proved
114
impossible, but a reasonable compromise that matched DC voltages within 20 mV was
finally achieved. Given the sensitivity of the ∆VBE summing bandgap reference to small
changes in layout and contact resistances, this difficulty in correlating the results to the
simulation was not surprising. Other effects such as circuit self-heating from the
relatively high power dissipation of 50 mW were also ignored in the simulation.
Appendix A contains the PSpice listing of the ∆VBE summing bandgap reference
simulation. Because of the three high-gain buffer amplifiers, the simulation initially
suffered from very slow DC convergence. This problem was eventually resolved by
increasing the RELTOL tolerance parameter and obtaining .NODESET voltages that
permitted faster convergence with a normal RELTOL value. The PSpice .MODEL Level
3 MOSFET parameters were supplied by MOSIS for this particular 1.2 µm CMOS
fabrication run. The .MODEL parameters for the lateral PNP transistors were generated
from Figs. 4-4 through 4-7 using the PARTS program supplied with PSpice [44].
Parameters such as PNP transistor base resistance and MOSFET flicker coefficient were
obtained from measurements of test structures from previous runs of the MOSIS 1.2 µm
CMOS process. In the following sections the simulation results will be compared to
actual circuit measurements and the differences discussed.
ICL ICV = K IE
IE
Fig. 5-7. PSpice Macromodel for the Lateral PNP Transistor
115
Experimental Results
Because of high quiescent currents, resistive ground paths, and the numerous
external pads of this integrated circuit, the low noise bandgap reference was extremely
sensitive to very small changes in resistance for connections between circuit nodes
through which large currents flowed. Given the necessity of measuring voltages at
resolutions as low as 10 µV, even a change of a few milliohms in the resistance of a
critical metal-to-metal contact has a significant effect on the reference voltage value.
Preliminary attempts to use protoboards and IC sockets gave mixed results; while
repeatable output voltages could be obtained at room temperature if great care was taken,
thermal expansion and contraction of circuit contacts during measurements in the
temperature chamber made reference voltage values impossible to repeat from one run to
the next. Mechanical vibration also affected the output voltage, especially at times when
several people would be walking around or near the lab. Intermittent voltage fluctuations
as high as 500 µV in amplitude were not unusual.
To solve this dilemma, test fixtures were created on universal printed circuit
boards and every component, including the MOSIS bandgap reference chips, were
soldered directly into the test circuit. Every contact in the temperature chamber was
soldered, and critical contacts outside the chamber used Molex pins and sockets. A
soldered 5 V regulator circuit was added to isolate the reference from supply voltage
variation. The final result was a bandgap reference with voltages that could be reliably
repeated to within ± 20 µV over the -40 ˚C to 85 ˚C temperature range, provided the
measurements took place in the late evening when external vibration was at a minimum.
116
Reference Output Voltage and Quiescent Current
The nominal reference voltage of the bandgap reference was determined through
the trial and error method of selecting a particular value of bias resistor, measuring the
temperature coefficient of the output voltage over the -40 ˚C to 85 ˚C range, and then
adjusting the R1B bias resistor until minimum temperature coefficient was obtained at 25
˚C. Preliminary simulations indicated that four ∆VBE summing subcircuit sections would
be required to generate the bandgap reference voltage. However, the fabricated circuit
required only three sections due to the additional PTAT voltage drops across the parasitic
layout resistances in the ∆VBE summing subcircuits. The on-chip R1B bias resistors were
too small to be used for trimming because of the resulting change in the DC bias values,
and external 1% tolerance metal film resistors were used instead.
A 784 Ω resistor was chosen for R1B after a series of temperature runs with a
randomly selected circuit. Given this bias resistor value, a nominal voltage reference
value of 1.13769 V with a standard deviation of 3.98 mV was obtained after measuring
sixteen chips. The standard deviation of the reference voltage is undoubtedly worsened
by process and packaging fluctuations in metal trace and contact resistances, and could be
reduced with lower quiescent currents and better layout techniques. (The quiescent
current of the circuit at room temperature was measured at 10.0 mA, which corresponds
very well with the simulated reference current value of 10.2 mA in Fig. 5-8.) In any case,
this circuit would almost certainly require individual trimming of the bias resistor value
to obtain the optimum reference voltage.
117
Fig. 5-8. Simulation of Quiescent Current versus Temperature for the BandgapReference
Temperature Coefficient
The optimum output voltage for minimum temperature coefficient in a bandgap
reference depends on the operating temperature range of interest. Average temperature
coefficients of bandgap references are generally specified over the commercial
temperature range (0 ˚C to 70 ˚C) at the minimum, and may be specified over the
extended ranges of 0 ˚C to 100 ˚C or -40 ˚C to 85 ˚C as well. Assuming the output
voltage versus temperature curve is symmetrical above and below the nominal reference
value, the middle of the operating temperature range is the obvious place to bias the
output voltage for minimum temperature coefficient (e.g., 35 ˚C for the commercial
temperature range or 22.5 ˚C for the -40 ˚C to 85 ˚C range). Fig. 5-9 is the measured
temperature coefficient for a ∆VBE summing bandgap reference with three values of bias
resistor. Each operating temperature point was maintained for a minimum of one hour in
118
the temperature chamber prior to taking the voltage measurement. At R1B = 784 Ω, the
circuit has a nominal reference voltage of 1.14097 V with an average temperature
coefficient of 34.0 ppm / ˚C over the -40 ˚C to 85 ˚C operating range. At R1B = 784 Ω
the nominal output voltage is 1.13642 V and the average temperature coefficient over the
commercial temperature range is 15.8 ppm / ˚C. With careful trimming, temperature
coefficients of approximately 15 ppm / ˚C over a 70 ˚C span can be obtained with this
circuit. However, trimming resolution is limited by the minimum practical increment of
available bias resistance, which in the case of the MOSIS 1.2 µm CMOS process would
be approximately 25 Ω (a single square of polysilicon), excluding some form of laser
trimming.
119
85756555453525155-5-15-25-35-45
1.136
1.138
1.140
1.142
1.144
1.146
1.148
784 Ω Bias
806 Ω Bias
768 Ω Bias
Low Noise Bandgap Reference Temperature Performance
Ref
eren
ce O
utpu
t Vol
tage
Temperature (˚C)
Fig. 5-9. Reference Output Voltage versus Temperature with Different Bias Resistors
Figs. 5-10 and 5-11 are simulations of temperature coefficient versus output
voltage for the bandgap reference. These simulations show the same concave voltage
curvature as predicted in Chapter III and verified experimentally. However, the
temperature coefficients in these simulations are approximately twice the value of the
corresponding measured temperature coefficients. For example, with R1B = 784 Ω, the
simulation gives VREF = 1.1575 V with an average temperature coefficient of 62.5 ppm /
˚C over the -40 ˚C to 85 ˚C temperature range. At R1B = 806 Ω, the simulation has VREF
= 1.1525 V with an average temperature coefficient of 37.2 ppm / ˚C over the 0 ˚C to 70
˚C temperature range. Attempts to reduce the simulation temperature coefficients while
maintaining proper DC bias levels were unsuccessful. However, the simulation does not
120
account for effects such as circuit self-heating, and the circuit lacks access to most
internal nodes for better characterization. On the other hand, it can be argued that the
poor model-to-hardware temperature correlation is relatively unimportant, since the
actual temperature coefficients are considerably better than the simulation results, and the
overall temperature coefficient in future versions of the bandgap reference can be
adjusted as desired using techniques described in the next chapter.
Fig. 5-10. Simulation of Reference Output Voltage versus Temperature with a 784 ΩBias Resistor
121
Fig. 5-11. Simulation of Reference Output Voltage versus Temperature with 768 Ω, 784Ω, and 806 Ω Bias Resistors
Fig. 5-12 is a plot of temperature versus reference voltage over the -40 ˚C to 85
˚C temperature range for four randomly picked bandgap reference circuits using identical
bias resistors of 784 Ω. Circuit #1 achieves a 28.7 ppm / ˚C temperature coefficient over
the full temperature range, and circuit #3 has a temperature coefficient of 11.4 ppm / ˚C
over the 15 ˚ C to 85 ˚C temperature range. Circuits #2 and #4 apparently are not biased
at a high enough quiescent current, and require a small reduction in their respective bias
resistances to achieve optimum temperature coefficient. These results demonstrate the
need for individual trimming of the circuits, and also tend to indicate that the nominal
reference voltage is approximately 1.14 V once this trimming has been achieved.
122
9080706050403020100-10-20-30-40
1.130
1.132
1.134
1.136
1.138
1.140
1.142
1.144
1.146
1.148
1.150
Circuit #1
Circuit #2
Circuit #3
Circuit #4
Reference Output Voltagewith 784 Ω Bias Resistor
Out
put V
olta
ge
Temperature (˚C)
Fig. 5-12. Reference Output Voltage versus Temperature for Four Test Circuits
Output Noise
Fig. 5-13 is a plot of measured output noise versus frequency for the ∆VBE
summing bandgap reference, averaged over four chips. The output noise spectrum has a
1/f noise corner of approximately 3 KHz, and the overall noise level is much lower than
that of the differential bandgap reference [10]. At 1 Hz, the 1/f noise dominates, but the
output level is only 1.26 µV / Hz . At 100 KHz, the white noise level is only 27.0 nV /
Hz , while the level at 1 MHz drops to 18.9 nV / Hz . In Fig. 5-14, the output noise
simulation for the low noise bandgap reference gives a level of 1.08 µV / Hz at 1 Hz
decreasing to 23.9 nV / Hz . The measured white noise levels are approximately 1 dB
123
higher than the simulated levels, but these differences are within the experimental error
normally encountered in noise measurements. The higher measured noise levels could
also be a result of substrate heating from the circuit's quiescent power dissipation.
Overall, the model-to-hardware correlation for output noise is excellent.
The total simulated output noise at 27 ˚C over a 500 KHz bandwidth is 19.0 µV
RMS (Fig. 5-15), or 16.7 µV RMS per regulated volt. In contrast, the output noise of the
differential bandgap reference is 129 µV RMS per regulated volt over the same
bandwidth, or 17.8 dB greater. The ∆VBE summing bandgap reference has nearly an
order of magnitude less output noise than the differential bandgap reference at a cost of
far less quiescent current than the 71.6 mA predicted by standard current / noise scaling
estimates.
By examining the PSpice output listing for the output noise simulation, the major
contributors of output noise in the ∆VBE summing bandgap reference were identified. At
a frequency of 1 Hz, the dominant 1/f noise contributors are NFETs M4 and M5 in the
PTAT bias circuit (Fig. 5-1), which generate a total noise voltage of 1.00 µV / Hz .
PMOS transistors M1 and M2 generate 300.4 nV / Hz for the next highest 1/f noise
contribution, and all other component 1 /f noise sources are essentially negligible. These
values indicate that the reference circuit's 1/f noise could be reduced by approximately 11
dB if the NMOS transistors M4 and M5 could be replaced or removed using a different
PTAT bias circuit topology.
At a frequency of 100 KHz, the reference output noise is dominated by several
white noise sources in the circuit. Once again, components in the PTAT bias circuit
generate the majority of the noise. Resistor R1B generates a noise voltage of 11.7 nV /
Hz at the output, PFETs M1 and M2 generate 12.4 nV / Hz , and NFETs M4 and M5
generate 10.5 nV / Hz . The bulk of the remaining noise is generated by the Q2 and Q3
LPNP input transistors of the buffer amplifers, which contribute a total of 15 nV / Hz at
124
the output. In turn, the majority of the LPNP input transistor noise is intrinsic base
resistance thermal noise, and this noise can be reduced by using larger geometry input
transistors in the buffer amplifiers.
106
105
104
103
102
101
100
10
100
1000
10000
Reference Output Noise versus Frequency
Frequency (Hz)
nV
Hz
Fig. 5-13. Output Noise of the ∆VBE Summing Bandgap Reference
125
Fig. 5-14. Simulation of Output Noise Spectral Density versus Frequency
Fig. 5-15. Simulation of Total RMS Output Noise versus Frequency
126
Minimum Operating Voltage and Power Supply Rejection
The ∆VBE summing bandgap reference was designed to function with a 5 V
power supply, but CMOS circuit designs are inevitably moving towards smaller power
supply voltages. At the very least, a minimum power supply voltage of 3.0 V or less
would be desirable for a production version of this bandgap reference. Unfortunately, the
cascoded PMOS devices used in an effort to increase power supply rejection also
increase the minimum supply voltage. Fig. 5-16 is a measurement of output voltage
versus power supply voltage over the range VDD = 5.2 V to 3.0 V. As the power supply
voltage is reduced from 5.2 V, the reference provides an average PSR of 42.5 dB until
VDD = 3.6 V. Below this voltage, the PSR dramatically worsens to 8.6 dB, rendering the
low noise bandgap reference useless. This behavior is the direct result of the failure of
the PTAT bias circuit to operate properly at lower supply voltages. The bias circuit fails
long before the ∆VBE summing subcircuit does. However, the PSR needs to be increased
to 60 dB or better regardless of the minimum supply voltage.
One obvious technique for improving power supply rejection in the PTAT bias
circuit while reducing the supply voltage requirement is to remove the cascoded PMOS
transistors in favor of very long channel length transistors for both the PFETs and
NFETs. If this method proves impractical, a different low voltage bias circuit topology
with high PSR and low minimum supply voltage can be used with the circuit.
Figs. 5-17 and 5-18 show simulations of the DC and AC power supply rejection
of the bandgap reference, respectively. The DC PSR results correlate quite well to give a
minimum supply voltage of approximately 3.6 V. The AC power supply rejection has a
simulated -3 dB frequency of 100 KHz, although this parameter was not measured in the
laboratory.
127
5.45.04.64.23.83.43.0
0.85
0.90
0.95
1.00
1.05
1.10
1.15
Supply Voltage
Ref
eren
ce V
olta
ge
Fig. 5-16. Reference Voltage versus Power Supply Voltage
Fig. 5-17. Simulation of Reference Voltage versus Power Supply Voltage
128
Fig. 5-18. Simulation of Power Supply Rejection versus Frequency
Table 5-1 summarizes the measurement results for the ∆VBE summing bandgap
reference. Despite the DC voltage errors introduced by the parasitic layout resistances,
the ∆VBE summing bandgap topology successfully demonstrates that a low noise
bandgap reference with low temperature coefficient is possible and practical in the
MOSIS 1.2 µm n-well CMOS process. Although the circuit area and quiescent current
are greater than desired for a practical circuit, both can be reduced by such methods as
removing duplicated bias circuits, redesigning the buffer amplifier, and trading slightly
higher output noise for reduced current in the ∆VBE summing subcircuits.
129
Table 5-1. A Summary of Measured Parameters for the ∆VBE Summing BandgapReference with 784 Ω Bias Resistor and VDD = 5 V
Circuit Area 1.70 mm2
Quiescent Current 10.0 mA
Average Reference Voltage (@ 27 ˚C, VDD = 5 V) 1.13769 V (σ = 3.98 mV)
Temperature Coefficient (0 ˚C to 70 ˚C) 15.8 ppm / ˚C
Temperature Coefficient (-40 ˚C to 85 ˚C) 34.0 ppm / ˚C
Output Noise (@ 1 Hz) 1.26 µV / Hz
Output Noise (@ 100 KHz) 27.0 nV / Hz
Output Noise per Regulated Volt (500 KHz BW) 16.7 µV RMS
DC Power Supply Rejection Ratio - 42.5 dB
Minimum Power Supply Voltage @ 27 ˚C 3.6 V
130
CHAPTER VI
FUTURE DIRECTIONS FOR THE LOW NOISE CMOS BANDGAP REFERENCE
An Improved ∆V BE Summing Subcircuit
The experimental results of the ∆VBE summing bandgap reference demonstrate
the practicality of a bandgap voltage reference with low output noise in a standard n-well
digital CMOS process. Unfortunately, the disadvantage of relatively high quiescent
current in the ∆VBE summing subcircuit would severely limit the application of the low
noise topology, especially in low power CMOS designs. In this section, the benefits of
replacing the original ∆VBE summing subcircuit with an improved subcircuit will be
examined. If current source IBIAS2 in Fig. 4-10 is changed to a current sink and placed
between the cathode of diode D2 and circuit ground, the DC characteristics of this
improved ∆VBE summing subcircuit will be almost identical to that of the original circuit
analyzed in Chapter III. In Fig. 6-1, the input voltage VIN is mirrored to the cathode of
diode D2, rises by the voltage VBE2, and falls by the voltage VBE3 at the output. In fact,
since amplifier A1 supplies the current IC3 that flows through D3 and R1, IC2 will be
exactly equal to IBIAS2. The reference voltage approximation of equation (3-26)
becomes
131
VREF = Vg0 + (η − m − pK) kT
q 1− ln
T
Tr
−kT
q Tr
j=1
K
∑ αT,j + α R,j[ ]
+ kTq
j=1
K
∑ ln1+ α R,j (T − T j )
1− α T,j (T − T j )
.
(6-1)
This is a more exact expression for the ideal output voltage of the ∆VBE summing
bandgap reference.
-
+
VIN
VIN
IBIAS2
R1
VIN + VBE 2
A1
VOUT = VIN + VBE2 − VBE3 = V IN + ∆VBE
IC2
IC3D2 D3
Fig. 6-1. An Improved ∆VBE Summing Subcircuit
The improved ∆VBE summing subcircuit has some advantages over the previous
design in terms of noise gain and minimum operating voltage. For the original ∆VBE
summing subcircuit, the exact expression for the impedance seen by the IBIAS1 current
source (Fig. 3-3) is
132
rload = rd2 +ro
1+ A(s)
|| rd3 + R1( ) ≈ rd2 (6-2)
if A(s) is very large and R1 is much greater than rd2. As frequency increases and the
magnitude of A(s) decreases, the value of rload will increase until A(s) = 0 and rload
reduces to
rload A(s)=0 = rd2 + ro( ) || rd3 + R1( ) . (6-3)
Now consider the simplified small-signal diagram of the improved ∆VBE
summing subcircuit in Fig. 6-2. The noninverting input of the buffer amplifier is set
equal to AC ground via superposition and the IBIAS2 current sink is replaced by a
transconductance multiplied by an equivalent input noise voltage Ebias2. Given a buffer
amplifier with an output resistance ro and a finite gain A(s), the noise gain from the
IBIAS2 current sink to the output of the buffer amplifier is
Eout
Ebias2=
A(s)rd2 − ro[ ] gm(bias2 )
A(s) +1+ rord3 + R1
(6-4)
for an equivalent bias circuit AC load impedance of
rload = A(s)rd2 − ro
A(s) +1+ rord3 + R1
. (6-5)
133
Assuming A(s) is very large, rload can be approximated as
rload ≈ rd2 . (6-6)
However, in contrast to the original ∆VBE summing subcircuit, the magnitude of rload in
equation (6-5) will be reduced as frequency increases and A(s) decreases, since the ro
term is subtracted from the numerator value. At the frequency where A(s) times rd2 is
equal to ro, the load resistance (and noise gain from the bias circuit) will become zero. At
higher frequencies, rload will rise until A(s) falls to zero and
rload A(s)=0 = ro | | rd3 + R1( ) (6-7)
which is a slightly smaller value than equation (6-3). Therefore, at any given frequency
the noise amplifier formed by the bias circuit and the IBIAS2 current sink will have an
equal or lower gain than the original summing subcircuit configuration, assuming all
component values are identical. Depending on the output resistance of the buffer
amplifier, the 1/f noise of the IBIAS2 NFET current sink, and the parameters of the MOS
transistors in the circuit, the improved ∆VBE summing subcircuit may generate less total
noise than the original subcircuit even when diode D2 is biased at currents below 1 mA.
134
+_
ro rd2
gm(bias2 )
∗Ebias2
V(-)
-A(s) V(-)
Eout2
rd3 + R1
Fig. 6-2. Small-Signal Diagram of the Improved ∆VBE Summing Subcircuit
If IC2 is reduced by a factor of ten and diode D2 is replaced with a 4 emitter dot
device rather than a 40 emitter dot device, the same ∆VBE drop through the summing
subcircuit can be obtained with much lower DC current. Similarly, the magnitude of IC2
could be reduced, the junction area of diode D2 kept the same, and the magnitude of IC3
decreased tenfold by increasing the value of R1. This strategy would minimize the
undesirable effects of emitter and layout resistances for diode-connected LPNP transistor
D2.
The other advantage of this new ∆VBE summing subcircuit topology is the
reduced minimum operating voltage of the circuit. Since IBIAS2 is now connected
between D2 and ground, the minimum output voltage VDD(min) is equal to
VDD(min) = VREF +V BE3 + VAO(min) (6-8)
where VAO(min) is the minimum difference between the supply voltage of the buffer
amplifier and the output voltage (VREF + VBE3). Given a properly designed operational
amplifier circuit, VAO(min) can be less than 200 mV. In this case, a minimum operating
135
voltage of 2.0 V is possible with this circuit, provided a low voltage bias circuit is
implemented as well. Since VIN will always be equal to 0.6 V or greater for each ∆VBE
summing subcircuit stage, the IBIAS2 NFET current sink should have ample voltage drop
for operation in the saturation region [3].
A New Method of High-Order Temperature Compensation
As previously described in Chapter II, several different methods of high-order
temperature compensation have been used in the past to reduce the average temperature
coefficient of bandgap voltage references. Most of these methods have drawbacks, either
in terms of increased circuit complexity or higher minimum operating voltages.
Although the ∆VBE summing bandgap reference has temperature performance
comparable to other CMOS bandgap references presented in recent years, an average
temperature coefficient of 15.8 ppm / ˚C over the commercial temperature range can still
be improved. The ∆VBE summing bandgap reference topology has the potential to
achieve much lower average temperature coefficients without complex circuitry simply
by varying the temperature coefficients of the bias currents for the individual subcircuits.
For example, consider the temperature coefficient curvature errors in each of the
subcircuits in Fig. 6-3, assuming all the bias currents are PTAT (as in the present circuit).
The VBE1 generator has a convex nonlinearity in its voltage versus temperature curve, as
is typical for any p-n junction. The ∆VBE summing subcircuits exhibit concave
temperature coefficient nonlinearities rather than purely PTAT behavior because the ratio
of currents between diodes D2 and D3 is not constant with respect to temperature (Fig. 6-
1). Instead, the current through D3 is set by the output voltage of the subcircuit and the
value of resistor R1, independent of IBIAS2. The cumulative error at the output of the
∆VBE summing bandgap reference is also concave because the summed concave
nonlinearities are greater than the convex nonlinearity of VBE1.
136
∑+
+
∑+
+K Summing Sections
VDD
VBE1
IBIAS1
∆VBE ∆VBE
D1
V REF =VBE1 +K * ∆VBE
Temp
VBE1
Temp
∆VBE
Temp
∆VBE
Fig. 6-3. Temperature Coefficient Errors in the ∆VBE Summing Bandgap Reference
As previously derived in Chapter III, both the concave and convex nonlinearities
have the same general form of
yx (T,Tr ) = Tr ′ f x (Tr )
f x (Tr )− ln
f x (T )
f x (Tr )
(6-9)
but with opposite amplitudes. This result implies that a precise cancellation of the
negative and positive error terms could result in very low average temperature
coefficients for the ∆VBE summing bandgap reference. However, such cancellation will
require some method of separately manipulating the individual nonlinearities in each part
of the circuit.
137
Equation (6-1) gives an approximation for the output voltage VREF with the
assumption that all the bias currents of the ∆VBE summing subcircuits have the same
temperature coefficient p. If the bias currents have different temperature coefficients, the
equation can be expanded to
VREF = Vg0 + (η − m) kTq
1− lnTTr
−kT
q pj 1− ln
T
Tr
j=1
K
∑
− kT q
Tr j=1
K
∑ αT,j + α R,j[ ]
+ kT
q
j=1
K
∑ ln1+ α R,j (T − T j )
1− α T,j (T − T j )
(6-10)
where m is the temperature coefficient for the IBIAS1 current source in the VBE1
generator subcircuit and pj is the IBIAS2 temperature coefficient for the jth summing
subcircuit. There are now (K+1) separate temperature coefficients in equation (6-10),
and each coefficient can be manipulated individually with a separate bias circuit. For
example, the temperature coefficient of VREF will be reduced if the curvature of VREF is
made less concave. If the VBE1 generator is biased with an IPTAT current source (Fig.
6-4) to obtain m ≈ -1 while the ∆VBE summing subcircuits are biased with a PTAT
current source for pj ≈ -1, the convex error term in equation (6-10) can be increased in
magnitude, resulting in greater cancellation of the concave error term. An IPTAT bias
current can also be applied to one or more of the ∆VBE summing subcircuits, changing
the respective temperature coefficient p j from 1 to -1 and decreasing the concave error
term further.
138
VDD VDD VDD
M1 M2 M3
M4 M5
ID4
Q1B
VBE1B VBE1B
R1B
W3L3
L2W2
∗ VBE1B
R1B
ID5 =VBE1B
R1B
Fig. 6-4. A Simple IPTAT Current Source
If necessary, the temperature coefficient nonlinearities of the ∆VBE summing
bandgap reference can be more precisely canceled by combining PTAT and IPTAT
current sources as shown in Fig. 6-5. By varying the ratio between the two currents, the
effective temperature coefficient m can be set over a range of approximately +1 to -1.
VDD
IPTAT PTAT
+1 ≥ m ≥ -1
Fig. 6-5. A Current Source with Adjustable Temperature Coefficient
139
An Improved ∆V BE Summing Bandgap Reference
Fig. 6-6 shows the block diagram for an improved ∆VBE summing bandgap
reference using the new ∆VBE summing subcircuit and the temperature coefficient
cancellation technique described in this chapter. The VBE1 generator uses an IPTAT
current source while the three ∆VBE summing subcircuits are biased with a PTAT current
source. The output voltage is trimmed by adjusting the bias resistors of the two current
sources to obtain a minimum temperature coefficient. Because high quiescent current
may limit the application of the low noise bandgap reference topology, the goal for this
new circuit was minimum output noise with a nominal supply current less than 2 mA. To
minimize the number of ∆VBE summing subcircuit stages, a D3 / D2 junction area ratio of
100 is used (i.e. ten 40 dot LPNP transistors with one 4 dot LPNP transistor). If this large
ratio creates problems due to device mismatch, an additional ∆VBE stage could be added
at the cost of higher output noise, quiescent current, and circuit area.
A detailed PSpice listing is shown in Appendix B. Figs. 6-7 through 6-11 are the
results of the simulation. Fig. 6-7 is the output voltage versus temperature over the -40
˚C to +85 ˚C temperature range. Due to the cancellation of the error terms, the average
temperature coefficient is less than 2 ppm / ˚C. The 1/f noise at 1 Hz is less than 1 µV /
Hz , which is comparable to the original circuit results, while midband white noise is 30
nV / Hz (Fig. 6-8) . The total output noise at 500 KHz is only 20 µV RMS per regulated
VDC (Fig. 6-9), which is less than 16% of the output noise produced by the differential
bandgap reference over the same bandwidth. The circuit's power supply rejection is
approximately 78 dB at DC with a -3 dB rolloff at 8 KHz (Fig. 6-10). This overall
excellent performance is achieved with less than 1.5 mA of total current at 27 ˚C (Fig. 6-
11), and the estimated area is only 1 mm2.
140
∑+
+
∑+
+
∑+
+
VDD
VBE1
∆VBE ∆VBE ∆VBE
D1
IPTAT
IIPTAT
Bias BiasBias
VREF =V BE1 +3 ∗ ∆VBE
Fig. 6-6. Block Diagram of the Improved ∆VBE Summing Bandgap Reference
Fig. 6-7. VREF versus Temperature for the Improved ∆VBE Summing BandgapReference
141
Fig. 6-8. Output Noise versus Frequency for the Improved ∆VBE Summing BandgapReference
Fig. 6-9. Total Output Noise for the Improved ∆VBE Summing Bandgap Reference
142
Fig. 6-10. Power Supply Rejection versus Frequency for the Improved ∆VBE SummingBandgap Reference
Fig. 6-11. Supply Current versus Temperature for the Improved ∆VBE SummingBandgap Reference
143
A Low Noise Fractional Bandgap Reference
As battery powered computing and telecommunications equipment becomes more
common, the demand for analog and digital CMOS circuits that operate at lower supply
voltages increases. The design of high performance CMOS circuits that operate at supply
voltages at 1 V or less is an area of considerable research at this time. With such small
power supply voltages, intrinsic circuit noise reduction becomes even more desirable for
applications such as data acquisition and analog-to-digital conversion.
A standard bandgap reference circuit with VREF = 1.2 V cannot be implemented
with a 1 V power supply. On the other hand, a "fractional" bandgap reference with an
output voltage of
VREF(FR) =VREF
K=
VBE
K+∆ VBE (6-11)
is certainly possible, and a circuit of this type has recently been implemented in a bipolar
process [45]. As equation (6-11) shows, a fractional bandgap reference achieves
minimum temperature coefficient by dividing the base-emitter voltage VBE by the factor
K instead of multiplying ∆VBE by K. The result is a nominal output reference voltage
less than 0.4 V.
Fig. 6-12 shows the proposed topology of a low noise fractional bandgap
reference using a single ∆VBE summing subcircuit stage. Resistors R2 and R3 act as a
simple voltage divider for voltage VBE1, which in turn is summed with a single ∆VBE
voltage. The drawback to this topology is the requirement for a buffer amplifier and
VBE1 voltage generator which can operate at VDD = 1.0 V. Low noise, low voltage
amplifier designs using LPNP bipolar transistors have already been tested in the MOSIS
144
1.2 µm CMOS process, and MOSFET transistors can be operated in the subthreshold
region [3], although circuit simulation at very low supply voltages is hampered by the
lack of good subthreshold region modeling in PSpice [44].
VDD
VBE1
IBIAS1
D1 -
+
VIN
IBIAS2
R1
A1D2 D3
~ 175 mV
~ 875 mV
~ 175 mV
VIN
VOUT ≈300 mV
R2
R3
Fig. 6-12. The Low Noise Fractional Bandgap Reference Topology
Figs. 6-13 and 6-14 show the PSpice simulation results for a simplified model of
the fractional bandgap reference. Since PSpice does a poor job of simulating
subthreshold behavior in MOSFETs, ideal circuit elements were used for the current
sources and buffer amplifier. As such, the simulated average temperature coefficient of
19 ppm / ˚C at the given bias current level is probably inaccurate, but the temperature
coefficient of the actual circuit could be easily adjusted using the techniques described in
this chapter. Similarly, the output noise level is artificially low (especially in the 1/f
region) because of the use of noiseless ideal elements in the simulation.
145
Fig. 6-13. Output Voltage versus Temperature (˚C) for the Fractional Bandgap Reference
Fig. 6-14. Output Noise versus Frequency for the Fractional Bandgap Reference
146
Despite the limitations of this simple simulation, the results indicate that a
fractional bandgap reference is almost certainly practical in the MOSIS 1.2 µm CMOS
process. In fact, given a working fractional bandgap circuit, one obvious application
would be to operate the circuit at higher power supply voltages and add a voltage
multiplier stage to obtain the reference voltage
VREF = VFB 1+RF1RF2
. (6-12)
Resistors RF1 and RF2 could be adjusted to generate any voltage greater than or equal to
VFB, the fractional reference voltage. Since the output noise of VFB and the offset
voltage of the output buffer would be multiplied by the the same resistor ratio, the end
result would be a circuit with reduced circuit size and current requirements at the expense
of higher output noise and component error sensitivity as compared to the standard ∆VBE
summing bandgap reference topology.
-
+FractionalBandgapVoltageReference
VREFVFB
RF1RF2
Fig. 6-15. A Fractional Bandgap Reference with a Voltage Multiplier Stage
147
CONCLUSIONS AND RECOMMENDATIONS
Conclusions
This dissertation demonstrates an original method of noise reduction for a
bandgap voltage reference constructed in a standard 1.2 µm n-well CMOS process.
Output noise is a significant source of error in CMOS bandgap references, and practical
noise reduction without the use of external filtering requires a reference circuit topology
that separates the desired DC performance from the undesired small-signal noise gain.
The original ∆VBE summing bandgap reference attacks this problem from two directions.
First, voltage summation gives lower output noise than direct voltage multiplication.
Second, bipolar diodes produce large DC voltage drops with lower small-signal dynamic
resistance than fixed load resistors.
Another significant contribution of this research is the development of a lateral
PNP bipolar transistor that can be fabricated in the MOSIS 1.2 µm n-well CMOS
process. The ∆VBE summing bandgap topology requires low noise buffer amplifiers and
floating bipolar diodes to function, and this parasitic LPNP transistor structure was the
key component for successful operation. Characterization of lateral PNP transistors over
six fabrication runs has shown them to be repeatable, reliable devices with low intrinsic
1/f noise and good ß and gain-bandwidth.
A low noise bandgap circuit was designed, tested, and fabricated in the MOSIS
1.2 um CMOS process. Although parasitic resistances in the original layout adversely
affected the circuit's performance, the reference generated output noise nearly an order of
magnitude less than previously reported CMOS bandgap references, while maintaining a
comparable temperature coefficient over the commercial temperature range. The major
148
drawback of the circuit was the excessively high quiescent current, but this current could
be significantly reduced using simple design changes in future versions of the reference.
Besides the successful construction and peformance of the reference circuit, a new
methodology of high-order temperature compensation for bandgap voltage references
was developed and simulated in this dissertation. By generating the circuit's ∆VBE
voltage using two diodes with a current ratio that is not constant with respect to
temperature, the temperature coefficient nonlinearity of a standard bipolar diode can be
canceled without the need for complicated circuit methods used in previous CMOS
bandgap reference designs.
In conclusion, this research makes three major new contributions in CMOS
analog design: (1) the design and characterization of a lateral PNP bipolar transistor in a
standard 1.2 µm digital CMOS technology, (2) the analysis, fabrication, and testing of a
functional low noise bandgap reference using a new circuit topology that reduces intrinsic
component noise by nearly an order of magnitude, and (3) the derivation and simulation
of a simple method for cancelling the second- and higher-order nonlinearities in the
temperature coefficients of standard bandgap voltage references.
Recommendations for Future Research
While the experimental results of the low noise bandgap reference have verified
the basic advantages of the new topology, enormous potential remains for extending the
concepts introduced by this dissertation in future designs. The improved ∆VBE summing
subcircuit of Chapter VI coupled with a new bias circuit will permit the fabrication of a
∆VBE summing bandgap reference with low output noise and reduced minimum supply
voltage while simultaneously reducing quiescent current and layout size to levels
competitive with standard CMOS bandgap references. A low noise fractional bandgap
reference that can operate with a 1 V power supply is also possible, although a low
149
voltage bias circuit and buffer amplifier must be designed to make the circuit practical.
An improved version of the ∆VBE summing bandgap reference and a fractional bandgap
reference are planned for fabrication through MOSIS in the coming year.
Another important area yet to be explored is the extension of the ∆VBE summing
bandgap topology to different integrated circuit processes. The MOSIS service offers a
standard CMOS 0.8 µm n-well process and a BiCMOS 2.0 µm n-well process. The 0.8
µm technology should enable a much smaller reference circuit to be fabricated, but lateral
PNP structures constructed in this process have only begun to be examined. On the other
hand, the 2.0 µm process offers a proven high-performance NPN bipolar transistor that
can be used to construct a true floating bipolar diode or replace a noisy NMOS transistor
in a low noise buffer amplifier or bias circuit. A ∆VBE summing bandgap reference
fabricated in a BiCMOS process would have even lower 1/f output noise than already
demonstrated by the CMOS version of the circuit. The bandgap reference could also be
fabricated in a true bipolar IC technology, although the output noise improvement in such
a process might be too small to be worth the effort, given the circuit overhead required by
the topology.
As a final recommendation, the application of the higher-order temperature
compensation method should be examined in greater detail. This compensation
technique can be used with any bandgap topology and is independent of output noise
performance. For example, a noisy but low-power bandgap reference design requiring
external filtering could still use this method to reduce the temperature coefficient.
150
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APPENDIX A
PSPICE LISTING FOR THE ∆VBE SUMMING BANDGAP REFERENCESIMULATION