A Low-Cost, Low-Power Wireless Receiver Shwetabh Verma Center for Integrated Systems Stanford University
A Low-Cost, Low-Power
Wireless Receiver
Shwetabh Verma
Center for Integrated SystemsStanford University
2
• Motivation
• Introduction to Specifications Design
• Signal Path Design and Experimental Verification
• Synthesizer Design and Experimental Verification
• Final Receiver Design and Measurements
Outline
3
GRAPHIC TO COME
Eliminate wires everywhere !
Motivation
4
• Data rate: 1 Mb/s.
• ISM band operation.
• A few channels (>5) for diversity/ multiple access.
• Robust modulation scheme.
• Range ~ 10 m.
• Implementable with very low-cost, low-power devices.
Basic System Requirements
5
• State-of-the-art CMOS Bluetooth Radio (Ericsson, ISSCC 2002)
Can we make some tradeoffs at the system level to lower
costs?
DIGITAL
RADIO
BASEBAND
Data Rate: 1 Mb/s
Active Receiver Current = 30 mA
Active Transmit Current = 35.5 mA
Technology: 0.18 µm CMOS
Supply Voltage ~ 2.5 - 3 V
Active Radio Area = 4.0 mm2
Offchip: Loop filter, SAW filter
One Solution: Bluetooth
6
• A new approach - concurrent design of circuits and system
specifications.
Bluetooth Zigbee Zero-G
Data Rate 1 Mb/s 250 kb/s 1 Mb/s
Spreading FHSS, 79 Chan. DSSS, 32-chipPN code
DSSS, 10-chipoffset code
Modulation BFSK O-QPSK DBPSK
Crystal Offset Tol. 20 ppm 80 ppm 200 ppm
Pulse Shaping Gaussian Half sine Gaussian
Sensitivity -70 dBm -85 dBm -75 dBm
Build a Simple System (I)
7
• Choose direct-sequence
spreading (DSSS): Frequency
Hopping (FHSS) places strict
requirements on PLL settling
time.
• Differential phase-shift key-
ing (DPSK) : robust to crystal
frequency offset.
frequencyt = 0 t = 1t = 2
Q
I
∆ωo*T
Build a Simple System (II)
8
• Choose channels: 2400 + 12n MHz, n = 1..6 .
• Relax oscillator phase noise requirement by using large inter-
channel spacing and guard bands.
BW=10 MHz
2412 2424 2436 2448 2460 2472f(MHz)
2483.52400
ISM Band
LGB = 7 MHz UGB = 6.5 MHz
Build a Simple System (III)
9
• Choose direct conversion : low-power, area-efficient radio
architecture.
• DC offset problem at output of mixer. Simple solution: Use large
DC-blocking capacitor.
Problem : large capacitor for low cutoff frequency, low noise .
LNA
DC offsetaccumulation
Spectrum Shaping: Offset Coding (I)
10
• A solution :
Shape the spectrum away
from DC using coding-
allows smaller capacitor size.
• Additionally, we must use differential encoding for robustness to
oscillator frequency offset.
HPF
Data
f(MHz)
Spectrum Shaping: Offset Coding (II)
11
• Example: 4-bit case DC-free spreading case
• Let (1101) and (0010) be spreading symbols for 0 and 1, resp.
If previous bit is 0
DC-free diff. encoded sequences: (1001) and (0011), resp.
If previous bit is 1
DC-free diff. encoded sequences: (0110) and (1100), resp.
• Independent of data, ... xxx 1xxx 0xxx 1xxx 0 ... pattern appears.
• Sharp tones - hard to meet FCC bandwidth requirement .
Spectrum Shaping: Offset Coding (III)
12
• Our solution - introduce periodicity in spreading sequence.
• Example: 4-bit DC-free spreading case
• Let (1010) and (0111) be spreading symbols for 0 and 1, resp.
If previous bit is 0
Diff. encoded sequences: (1100) and (0101), resp.
If previous bit is 1
Diff. encoded sequences: (0011) and (1010), resp.
• Find such codes which minimize power close to DC .
Spectrum Shaping: Offset Coding (IV)
13
• Chip rate = 10 Mchips/s, 500 kHz HPF, N = 1000 samples.
0 5 10 1510
−3
10−2
10−1
100
Relative Noise Level (dB/Hz)
BE
R15-bit PN
10-bit Offset
Offset Vs. PN codes : Simulated BER
14
• Front-end circuits:
- robust to strong out-of-band blockers
- acceptable noise performance with low power consumption
LNA
passiveLPF
1st-order passive
HPF
1st-order
strong blockersat mixer input
eliminate
AGC
SAW filter
passiveLPF
1st-order
MIXER
LNA/antennaco-design
Receive Signal Path
15
• Strong signals expected 500 MHz away (from Bluetooth spec.)
• Eliminate off-chip RF preselect filter: linearity and filtering hard.
Freq. (MHz)
30 2000 2364 2388 2498 2508 2520 3000
Min. Desired Signal = -72 dBm
-10 dBm-27 dBm
-32 dBm
-42 dBm
-72 dBm
2376
Blo
cker
Str
engt
h (d
Bm
)Receiver Out-of-band Blocking
16
Andreani et al., “Noise optimization of an inductively degenerated CMOS low noiseamplifier”, IEEE TCAS II, vol. 48, pp. 835-841, Sept. 2001.
∆I
∆V
ITAIL
-ITAILIN+
IN-
VB2
Inductanceof Antenna
Cextra :adds a degreeof freedom
elimination of ITAIL
for linearity at low curent
consumption
OUT
VB1
Low Noise Amplifier (I)
17
Qmin Qmax
Gain Requirement Bound
Linearity Bound ( α Ibudget )
Cextra = 0 T
rans
cond
uc. (
gm
)
Input Network Quality Factor ( Q)
Current ( I )Noi
se F
acto
r(
NF
)
(Ibudget , NF* )
NF*
Low Noise Amplifier (II)
18
• Need greater linearity in presence of strong blockers.
• Expensive to generate very large LO swings at RF.
IN
OUTPBIAS NBIAS
LO+ LO-
BIAS
BIAS
Our solution: a mixer with x-gates
X-Gate Mixer (I)
19
0.6 0.8 1 1.2 1.4 1.6 1.8−3
−2
−1
0
1
2
3x 10
−3
0.6 0.8 1 1.2 1.4 1.6−4
−3
−2
−1
0
1
2
3
4x 10
−3
NM
OS
& P
MO
SI D
S(A
)
VD (V)
OFF
ON
VGS = VTN
OFF
ON
VD (V)C
ombi
ned
Sw
itch
Cur
rent
(A
)
OFF
ON
VGS = VTP
PMOSNMOS Combined
1.2 V
VD
VGS = VT
X-Gate Mixer (II): DC Simulations
20
• Prototype mixer & filters built in 0.25 µm CMOS, tested at 1 GHz.
−50 −40 −30 −20 −10 0 10−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
1
7 dB
Nor
m. C
onve
rsio
n G
ain
(dB
)
Input Blocker Power (dBm)
X-GATE
NMOS ONLY
VLO: 250 mV
BLOCKER
DESIRED
H(s)
P-1dB,IN = 5 dBm
fLO = 1 GHz
Mixer Linearity: Measurements (I)
21
−60 −50 −40 −30 −20 −10 0 10 20−120
−100
−80
−60
−40
−20
0
20
1st &
3rd
Ord
er P
rods
. (dB
m)
7 dBVLO: 250 mV
H(s)
S1 S2
X-G
ATENM
OS
ONL
Y
Input Powers (dBm)
fLO = 1 GHz
IIP3 = 16 dBm
Mixer Linearity: Measurements (II)
22
104
105
106
107
108
109
−60
−50
−40
−30
−20
−10
0
Volta
ge G
ain
(dB
)
Frequency (Hz)
Expected
Measured1.5 dB
VLO: 250 mV
H(s)
fLO = 1 GHz
S1
Passive Chain: Measurements
23
• A direct conversion architecture with simple HPF is utilized.
• Offset coding is introduced with differential encoding for spectral
shaping.
• The expensive pre-LNA band-select filter is eliminated.
• The X-gate mixer is introduced for linear downconversion.
• A passive chain is utilized for filtering blocker signals post down-
conversion.
• The passive receive chain (including mixer) has been fabricated
and tested at 1 GHz.
Receive Path Design Summary
24
• A critical analog block ...
- spurs- phase noise
LNA FILTERS
MIXER
SYNTHESIZER
adjacent channels
channel of interest
downconverted spectrumspectrum of local oscillator
Low-Power Frequency Synthesis
25
• High frequency fO = N fIN generated because of prescaler.
• Loop filter determines the dynamics of the loop.
Σ Loop Filter
Prescaler
fO = N fIN+
-FrequencyReference
div-by- N
fINOutputFrequency
VCO
A Typical Frequency Synthesizer
26
• One major source of power consumption: high-frequency
prescaler in the synthesizer.•
• Regular CMOS digital gates: Power scales as fCVDD2 .
• How to deal with the high-frequency divider?
FromVCO
LowFrequencyM 1÷ M2÷ MN÷
Power in Prescaler
27
D Q
QCLK
D Q
QCLK
LATCH A LATCH B
CLK
CLK_DIV2
Q Q
D
D CLKCLK
Source - coupledD - latch
- lower power consumption
fCVDDVswing , but f remains.
Divide-by-2 in Low-Swing Logic
28
• Analog frequency dividers have power VDDIBIAS.
• If loop gain is sufficient without injection, feedback system oscil-
lates at ffree-run .
• Regenerative system tracks fI , the injection frequency/phase over
some locking range. fI must be close to ffree-run .
Filter OutputInject productsNon-
Linearity
Analog Regenerative Dividers
29
• A harmonic of ffree-run can also be injected : system is a phase-
locked divider.
fI = 2fO
fONonlinear
Block
Filter
δ
δ
free-running
injection-locked
excess phase
excess phase
τ
Injection-locked Frequency Divider
30
• Characteristic first-order time constant τ: determines the
dynamic response, locking range and phase noise of the ILFD.
1/τ
free-running phase noise
input PN
ILFD phase noise
Pha
se N
oise
(dB
c/H
z) 20log( M)
Frequency (Hz) - log scale
Phase Noise of ILFD
31
• We can do even better: eliminate a divide-by-3 circuit at the high-
frequency end.
• Oscillator has two outputs: one at 3fO, and one at fO.
Σ Loop Filter+
-
fIN
fO = N fIN
3fO
N÷
A New Oscillator
32
• Currents from all stages
of the ring are injected
into the LC tank and com-
bine to generate 3fO.
3fO
fO
A Multiply-by-3 Ring Oscillator
33
• Ideally, output spectrum
contains only 3fO and its
harmonics.
• Due to device mismatch,
spurious tones at fO and
its harmonics appear.
T/3 2T/3 T0
i A
3 pulses
iA RP VO
+
-
Injected Current from One Ring
34
• Single-ended, three stage
ring: Gaussian RV VT and
β for all NMOS devices900 MHz
300 MHz
Qtank = 3, RP = 600 Ω
3ωO 4ωO2ωO600MHz 900MHz 1200MHz
CSR
30 40 50 60 70 800
50
100
150
200
Carrier-to-Spur Ratio (dB)
No.
of O
ccur
renc
es
σ = 6 mVσβ,rel = 3%VT
N = 1000
Simulated Effect of Stage Mismatch
35
• Depends on sharpness of current injection, and DC current.
T/3
Inj.
Cur
rent
T/3
Inj.
Cur
rent
V mult 2I DCRP=
V mult4π---
2I DCRP=
δ = 0
δ = 0.25T/3
2δ
Output Amplitude
36
• Twice the voltage amplitude for twice the current consumption.
MultNodeA
MultNodeB
OutA
OutB
180o coupled rings
Oscillator: Differential Implementation
37
MultNodeA MultNodeB
From prev.stage of ring A
From prev.stage of ring B
VCONTROL VCONTROL
VDDRING A RING B
To next stageof ring B
To next stageof ring A
Interstage Coupling
38
• Get 100 mV voltage swing with IDC = 150 µA and RP = 600 Ω.
23 23.5 24 24.5 25 25.5 26−100
−50
0
50
100
23 23.5 24 24.5 25 25.5 260
0.05
0.1
0.15
0.2
0.25
Tank
Vol
t. (m
V)
Cur
rent
(m
A)
IVDDinjected currentsfrom both rings
time (ns)
Output Amplitude: Simulation at 900 MHz
39
• LC oscillator shown would ideally provide 115 mV voltage swing
with IDC = 150 µA and RP = 600 Ω.
V osc4π---I DCRP=
Vosc
IDC
∆I+IDC
-IDC
∆Iassuming complete
switching
t
Comparison: Ideal LC Oscillator
40
• Prototype oscillator built in 0.25 µm CMOS - providing 300 MHz
and 900 MHz output frequencies.
• Operates at voltages as low as 1.3 V, while consuming 210 µA.
40 dB
103
104
105
106
107
−130
−120
−110
−100
−90
−80
−70
−60
−50
−40
low freq. ( fO)
high freq. (3 fO)
Pha
se N
oise
(dB
c/H
z)
Frequency (Hz)
10 dB
-104 dBc/Hz @ 4 MHz
A Prototype VCO at 900 MHz
41
• The power consumption of the high-frequency prescaler is identi-
fied as critical.
• After studying various low-power prescaler design techniques, a
new multiplier VCO is introduced.
• A prototype design has been fabricated and tested for 900 MHz
operation. It trades off phase noise performance for lower power
consumption.
Synthesizer Design Summary
42
Synthesizer0.8 GHz 4 MHz2.4
GHzLO Buf.
0o
90o
Pass. Filt.
Pass. Filt.
BUF
BUF I
Q
RFIN
ChannelLNASelect Select
Ref.
BUF
BUF
LNA
0/20dB
A Fully-Integrated Receiver at 2.45 GHz
43
φdetect.
0.8 GHz
2.4 GHz 4 MHzChargePump
2nd-OrderFilter
Integer Divider
Q
I
Increase Miller capacitanceto generate 90 o
BUFA
BUFI
BUFQ
LO Generation Circuits
44
2.38 2.39 2.4 2.41 2.42
x 109
−80
−70
−60
−50
−40
−30
−20
−10
−30 −25 −20 −15 −10 −5 010
−4
10−3
10−2
10−1
100
35 dB45 dB
0 +4MHz
+8-4-8
Rel. Spur Level
Mea
sure
d P
ower
(dB
)
Sim
ulat
ed B
ER
Relative Spur Level (dB) Frequency (Hz)
Required:
- 4 MHz, 8 MHz spurs, 20 dB below carrier.
- 24 MHz spur, 40 dB below carrier.
3 dB diff. innoise floor
Eases charge pump design with 1.8 V supply.
Reference Spurs: Measurements
45
104
105
106
107
108
−130
−120
−110
−100
−90
−80
−70
−60
−50
Pha
se N
oise
(dB
c/H
z)
Frequency (Hz)
Phase NoiseRequired:-111 dBc/Hz
@ 24 MHz
Phase Noise Measurement
46
−40 −30 −20 −10 0 10−10
−8
−6
−4
−2
0
2
6 dB
X-GATE
NMOS ONLY
Nor
m. R
ecei
ver
Gai
n (d
B)
Input Blocker Power (dBm)
BLOCKER
DESIRED
H(s)
1.87 GHz
1.87 GHz
1.80 GHz
Synth.
P-1dB,IN =-15 dBm
Blocker Sensitivity
47
Performance Achieved Required
Passband Noise Fig. (@1.9 GHz) 8.8 dBa
a. VGA needed after passive chain - not included in design.
< 18 dB
1-dB Blocker Compress. Pt. -15 dBm -20 dBm ( Qin = 3)
LO Phase Noise @24 MHz < -115 dBc/Hz <-111 dBc/Hz
Ref. Spur @24 MHz -45 dBc < -40 dBc
Signal Path Current 3 mA
Synth. Current @2.45 GHz 2.5 mA
LO Buffer Current 4 mA
Total Current 9.5 mA
Supply Voltage 1.8 V
Active Chip Area 0.66 mm2
Off-chip Components Inductor (ant.), crystal
Technology 0.25 µm CMOS
Performance Summary
48
• Implemented in 0.25 µm CMOS.
RECEIVED SIGNAL
LO FREQUENCY
SYNTHESIZER
PATH
BUFFERS
Receiver Die Photo
49
0 20 40 60 80 100 120 1400
0.5
1
1.5
2
2.5E
stim
ated
Rec
eive
r C
ost (
$)
Receiver Power (mW)
Zero-G (projected)
Ericcson (‘02)0.18 µm CMOS
Transilica (‘02)0.25 µm CMOS
Mitsubishi (‘03)0.18 µm CMOS
Conexant (‘01)
0.5 µm SiGe BiCMOS
Silicon Wave (‘02)0.35 µm SiGe BiCMOS
0.25 µm CMOS
Receiver Cost-Power Comparison
50
• Contributed to the concurrent design of the system specifications
and circuits for the Zero-G system.
• Implemented a highly-integrated, low-power, low-cost receiver
frontend which:
- eliminates the band-select filter.
- linearly downconverts and filters strong blockers.
- implements a low-power synthesizer with a multiply-by-3
oscillator.
• Created and experimentally verified a unified model for injection-
locked frequency dividers.
Contributions
51
R. J. Betancourt-Zamora, S. Verma, T. H. Lee, "1-GHz and 2.8-GHz CMOS Injection-locked Ring Oscillator Prescalers ," Symposium on VLSI Circuits, June 14-16, 2001.
S. Verma, H. Rategh, and T. H. Lee, "A Unified Model for Injection-Locked FrequencyDividers ," IEEE Journal of Solid-State Circuits, Volume 38, Issue 6, June 2003, pp 1015-1027.
S. Verma, J. Xu, T.H. Lee, "A Multiply-by-3 Coupled-Ring Oscillator for Low-power Fre-quency Synthesis ," Symposium on VLSI Circuits, June 12-14, 2003, pp 189-192.
M. Hamada, S. Verma, J. Xu, T.H. Lee, "Completely DC-free Direct Sequence SpectrumSpreading Scheme for Low Power, Low Cost, Direct Conversion Transceiver ," WNCGWireless Networking Symposium, October 2003.
S. Verma, J. Xu, T.H. Lee, "A Multiply-by-3 Coupled-Ring Oscillator for Low-power Fre-quency Synthesis ," IEEE Journal of Solid-State Circuits, Volume 39, Issue 4, April 2004,pp 709-713
S. Verma, J. Xu, M. Hamada, T.H. Lee, "A Low-Cost, Low-Power Wireless Receiver ,"IEEE Journal of Solid-State Circuits, under preparation.
Publications
52
• Prof. Tom Lee
• Prof. Khuri-Yakub, Prof. Wooley, Prof. Wong
• Ann Guerra
• SMIrC group, Prof. Wooley’s group, Prof. Wong’s group
• Mototsugu Hamada and Junfeng Xu
• National Semiconductor, Stanford Graduate Fellowships
• Friends!
• Family
Acknowledgments
53
• Required SNR =
> 10 dB
• L(24 MHz) < -110.8 dBc/Hz
24 MHz
30 dB Max.
Chan. Spacing: 12 MHz
BW: 12 MHz
30–
Signal
10 12MHz( )log L 24MHz( )+[ ]–
Phase Noise from Interferer
Phase Noise Requirement
54
• Gain mismatch : for a gain mismatch of α, SNR degrades by α2.
-10% mismatch brings 0.9 dB of SNR degradation.
• Phase mismatch : for a phase mismatch of φ, signal power
reduced to 1/(1+φ) in the worst case.
- 10o mismatch brings 0.7 dB SNR degradation.
I-Q Mismatch
55
• Relaxed adjacent and alternate channel requirement.
• Eases phase noise and IIP3 required from the receiver.
0 dB
30 dB
0-12 +12 + 24
Relative Freq. (MHz)
Relative Power
- 24
Receiver In-band Blocking
56
• IIP3 required is -19 dBm, limited by end buffers.
• IIP2 required is +1 dBm, limited by input symmetry.
sine-39 dBm
modulated-39 dBm
modulated-69 dBm
f1 f2
>10 dBSNR
f0 = 2f1-f2
24 MHz
Second/Third-Order Intercept
57
• Woven structure of M1-M2-M3-M4-M5 lines on top of poly-poly
capacitors.
ABAB
A B A B
via
High-Density Capacitors
58
LNAMATCH
2.1 dBNF
GAV -2.1 dB
4 dB
9 dB
16 dB
-16 dB
BUF
1.5 dB
PASSIVE CHAIN
Cumulative NF = 13.9 dB
System NF = 8.8 dB
Receive Path Gain/Power Distribution
59
φdetect.
4 MHz
Integer Divider
3fO
fO
8/9N/N+1 P
24
S
1..20
fosc
MC
RESET
M = NP +S +1
M
flow
DN
UP
DN
UP
PLL Implementation
60
IN+
IN-
LNA1 LNA10
C1 C2
LNA Implementation
61
−60 −50 −40 −30 −20 −10 0 10−80
−60
−40
−20
0
20
40
VLO: 250 mV
S1 S2
fLO = 1.9 GHz
X-G
ATE
NMO
S O
NLY
Frontend
1st &
3rd
Ord
er P
rods
. (dB
m)
Input Powers (dBm)
1.925 1.949
IIP3 = -7 dBm
∆IIP3 = 6 dB
Alternate Channel IIP3 (External LO)
62
−50 −40 −30 −20 −10 0 10 20−80
−60
−40
−20
0
20
40
60
VLO: 250 mV
S1 S2
fLO = 1.9 GHz
Frontend
1st &
2nd
Ord
er P
rods
. (dB
m)
Input Powers (dBm)
1.902 1.90275
IIP2 = 10 dBm
IIP2 (External LO)
63
0.8 1 1.2 1.4 1.60
1
2
3
4
5
6x 10
−3
0.8 1 1.2 1.4 1.6 1.80
1
2
3
4
5
6x 10
−3
NM
OS
& P
MO
Sg
ds(A
/V)
VD (V)VD (V)
OFF
ON
Com
bine
dg
ds(A
/V)
OFF
ON
OFF
ON
VGS = VT
PMOSNMOS Combined
1.2 V
VD
VGS = VTNVGS = VTP
X-Gate Mixer (III): DC Simulations
64
• SAW filter after antenna = $0.30
• Crystal: +/- 10 ppm = $0.25; +/- 100 ppm = $0.15
• T/X Switch = $0.50
• RF Balun = $0.05
• Passives = $0.01 each (ignored)
• Cost of CMOS = $0.10/mm2, SiGe BiCMOS = 0.15/mm2
• Our work :
projected receiver power = 2*(9.5 mA*1.8) = 34.2 mW
projected Si area = 2*(0.66 mm2) = 1.3 mm2
No T/X switch, No SAW filter, +/- 100 ppm crystal.
Cost/Power Estimation Assumptions
65
Q
triangle approximation
2δ0
Q
T/N
Inje
cted
Cur
rent
c 1NQT--------- 2 Nπδ T⁄( )sin
Nπδ T⁄( )----------------------------------2
⋅=
V mult 2 Nπδ T⁄( )sinNπδ T⁄( )----------------------------------
2I DCRP=
Fourier coefficient at 2N π/T:
Using IDC = NQ/T and Ztank = RP ,
Output Amplitude: Calculation