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Measurement 46 (2013) 402410
Contents lists available at SciVerse ScienceDirect
Measurement
journal homepage: www.elsevier .com/ locate /measurement
A LabVIEW based automatic test system for sieving chips
Zhongyuan Wang a, Yongheng Shang b,, Jiarui Liu b, Xidong Wu aa
School of Information Science and Electronic Engineering, ZheJiang
University, Chinab School of Aeronautics and Astronautics, ZheJiang
University, China
a r t i c l e i n f o
Article history:Received 26 April 2012Received in revised form
14 June 2012Accepted 19 July 2012Available online 27 July 2012
Keywords:LabVIEWPXIDAQCMOS chipDAC testingAutomatic testing
system
0263-2241/$ - see front matter 2012 Elsevier
Ltdhttp://dx.doi.org/10.1016/j.measurement.2012.07.01
Corresponding author. Tel.: +86 (0)571 8795(0)18257146541.
E-mail addresses: [email protected]@gmail.com (Y.
Shang), [email protected] (X. Wu).
a b s t r a c t
The present trend for Complementary Metal Oxide Semiconductor
(CMOS) chip designs issmaller in size and power consumption with
multifunction. This results the difficulty forthe testing engineer,
especially for small amount production without an automatic
probestation, to complete such task. In order to reduce the
workload of the engineer, improvethe testing efficiency and
accuracy, a LabVIEW based automatic test system for such CMOSchip
has been designed in this paper. The details of the overall system
which includes thesetup of the testing by using a PXI (PCI
extensions for instrumentation) system with DataAcquisition (DAQ)
and Source Measure Units (SMUs) module, and the LabVIEW based
auto-matic testing program has been introduced in this paper. The
testing results have shownthat this system is able to improve the
testing efficiency with great accuracy, at the sametime to evaluate
the testing results in real-time. Due to the software is built on
differentmodules, and it is therefore easy to be extended for
different applications.
2012 Elsevier Ltd. All rights reserved.
1. Introduction
As the interface between the digital processing and ana-log
signals, the Digital-to-Analog Converter (DAC) is widelyutilized in
Integrated Circuit (IC). And the testing of DAC isstudied by
numbers of researchers. An Analog-to-DigitalConverter (ADC) is
always used in the testing of DAC inmost case [13]. Therefore, many
algorithms based onthe use of ADC have been raised for the signal
processingin recent years [46]. However, with the fast
developmentof the technology and the testing instruments related
toData Acquisition (DAQ), the testing of DAC becomes moreconvenient
and accurate than ever before. And certainattention should be paid
to the architecture of the testingsystem.
In this project, a highly integrated multifunction
Com-plementary Metal Oxide Semiconductor (CMOS) chip has
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(Z. Wang), banylora.n (J. Liu), xwu@zju.
been designed for the application of a transmit-receive(TR)
system. It consists two sets of functions. One is to con-trol the
working states of the system with the designedlogical functions.
The second is to provide the bias voltagesfor all the active
devices such as switches and poweramplifiers (PAs) by using its
build-in DACs. Therefore,the logic function of the chip must be
verified to ensurethe control flow of the chip in designed working
order. Atthe same time, the voltage levels provided by the
DACswithin the chip have to be evaluated, in order to guaranteethe
bias voltages supplied to the active devices are in thedesigned
accuracy range. This is because the different biasvoltage affects
the performance of the active devices suchas the gain of the PAs,
which further affects the overall per-formance of the whole system.
In general, the testingsystem for such chip involves a power
supply, signal gen-erator, data acquisition system, testing bench,
real-timeanalysis system and testing engineer watching over
theprocessing of the testing. This requires many connectionsbetween
instruments which lead to a messy testing sta-tion. The most
important is that it makes the calibrationof the system error
becomes difficult, and also introducesextra testing error to the
final results. Besides, due to the
http://dx.doi.org/10.1016/j.measurement.2012.07.015mailto:[email protected]:banylora.
[email protected]:banylora.
[email protected]:[email protected]:xwu@zju.
edu.cnmailto:xwu@zju.
edu.cnhttp://dx.doi.org/10.1016/j.measurement.2012.07.015http://www.sciencedirect.com/science/journal/02632241http://www.elsevier.com/locate/measurement
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Fig. 2. PXI platform of NI.
Fig. 3. Probe card on the probe station.
Z. Wang et al. / Measurement 46 (2013) 402410 403
huge amount of data has to be acquired, stored and pro-cessed in
real-time, therefore, an automatic test systemmust be designed to
cope with the measurement timeand the data processing time, at the
same time reducethe errors brought by manual operation and the
workloadof the testing engineer.
The PCI extensions for instrumentation (PXI) platformtogether
with Laboratory Virtual Instrument EngineeringWorkbench (LabVIEW)
programming environment devel-oped by National Instruments (NIs) is
adopted as the cor-nerstone piece of equipment to construct the
automatictest system.
2. System configuration
The system configuration is shown in Fig. 1. The systemcontains
three parts: a PXI platform, a Field ProgrammableGate Array (FPGA)
board and a probe station with a probecard.
The PXI platform is used as the main control part of
theautomatic test system. It is responsible for test control,power
supply, and data acquisition, processing and stor-age. The PXI of
NI is a PC-based platform for measurementand automation. A typical
PXI platform is shown in Fig. 2. Ithas four components: chassis,
controller, modules andsoftware [7].
The chassis is the backbone of the PXI system. It pro-vides the
power, cooling, and communication buses ofPeripheral Component
Interface (PCI) and PCI Express forthe controller and modules [8].
In the chassis, there is acontroller slot with an operation system
such as MicrosoftWindows for users to operate with display screen.
Themodules inserted to the chassis act as a whole systemwithout any
other connection which reduces the systemerror produced by the
connections between instruments.Different module has its specified
function and can be usedwith other modules or independently. In
this paper, the NIX Series DAQ module PXIe 6363 is used for data
acquisi-tion. Its resolution is 16 bits, which guarantees
theaccuracy of the testing results. It offers 32 single
endedchannels, and that means 32 voltages could be acquiredat the
same time. A Source Measure Units (SMUs) modulePXIe 4140 is
utilized for power supply and currentmonitor.
A FPGA board is designed as the sub-control part of theautomatic
test system which communicates between thePXI and the chip on the
probe station. First, it receives com-mands from the PXI through
RS232, and then forwards thecorresponding outputs to the CMOS chip
through Serial
PXI Chassis
DAQ module
SMU module
FPGARS232 CMOS Chip
Probe Station
SPI
Fig. 1. System configuration.
Peripheral Interface (SPI). The outputs contain powersupply
signals and control commands to the CMOS chip.The control commands
allow the DACs of the CMOS pro-duce the corresponding voltage
levels and working statesof registers in the chip.
In general, a CMOS chip without pins cannot be con-nected to the
test equipments directly without contami-nate its pins. In order to
do so, a probe station is utilizedfor holding the chip, and
connects the pads of the chip tothe corresponding signal channels
of the PXI platformand the FPGA board with a custom-made probe
card. Thepins of the probe card are connected to the PXI
signalchannels, and its probes are connected to the pads of
thechip. Using a probe station in the test system makes it
con-venient to exchange chips, keeps the chip from contamina-tion
(especially the chip is assembled to a module forfurther using),
and improves the accuracy. A typical probecard in the probe station
is illustrated in Fig. 3
3. Software system
The software level of this testing system is based on theLabVIEW
platform. LabVIEW is a graphical programmingenvironment which helps
engineers quickly to developpowerful test software with beautiful
and convenientGraphical User Interface (GUI). A LabVIEW
programconsists of numbers of Virtual Instrument (VI). A VI
con-sists of a front panel, a block diagram and an icon that
rep-
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Fig. 4. Software flow chart.
404 Z. Wang et al. / Measurement 46 (2013) 402410
resents the VI. The front panel displays controls and
indica-tors for the users, while the block diagram contains thecode
of the VI. LabVIEW contains many basic VIs which al-lows the
programmer to construct a GUI in a much shortertime than other
conventional programming languagessuch as C/C++, Visual Basic, and
Matlab. Its graphical nat-ure makes it ideal for measurement and
automation [9,10].
To meet the testing requirements, the software is di-vided into
three parts. The first part is to verify the logicfunctions of the
CMOS chip. The second part is to test theperformances of DACs in
the chip. And the third part is to
Fig. 5. Block diagram o
evaluate the testing results, which includes data acquisi-tion,
storage and processing. Then the results are shownin the form of
associated waveform. The software flowchart is shown in Fig. 4.
First, the hardware related should be configured asintroduced in
the previous section. In this system, theCOM port of PXI is used to
communicate with FPGA, andtheir parameters about communication must
be consistentwith each other. The five parameters related are
configuredas follows:
Baud rate: 115200 bit per second. Data bit: 8. Stop bit: 2.
Parity bit: odd. Flow control: none.
The configuration can be achieved through the VI VISAConfigure
Serial Port in the Virtual Instrumentation Soft-ware Architecture
(VISA) library. VISA regulates the rulesand principles between the
modules of the virtualinstruments, which leads to the reducing the
number ofinstruments needed in the overall system and the
connec-tions between those instruments [11]. At the same time,
iteliminates some system errors.
At the same time, the physical addresses of the DAQ andSMU
module need to be configured as well. The drivers ofDAQ and SMU are
installed to ensure the right address con-figuration within the
testing system. The CMOS chip undertesting has nine voltage
outputs. Therefore, nine DAQchannel addresses have to be configured
to cope with. Inhere, a VI DAQmx Create Virtual Channel is
utilized. Inthe case of logical level testing, seven DAQ channels
areused. There are also two more channels used for DAC test-ing.
The SMU used in here contains four channels and twoof them are
selected to provide the +3.3 V and 3.3 Vpower supply
independently.
Then, it goes to logic test. In this paper, eight workingstates
of the chip should be tested. A while loop structureis used to
realize the cycle test. Seven output voltages
f logic level test.
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Fig. 6. Block diagram of DAC test.
Fig. 7. Calculation of INL and DNL.
Z. Wang et al. / Measurement 46 (2013) 402410 405
should be measured in each state and the currents shouldbe
monitored throughout all the states. If one of the sevenvoltages
acquired by the DAQ is out of the range or thecurrents monitored by
the SMU are beyond 10 mA (a max-imum designed error margin), it
means the chip is notworking properly, such as the connection
between the nee-dles of the probes and the pads of the chips are
loosen, thechip is damaged before has been put on the probe
card.Then the software exits and testing is over. The blockdiagram
of logic test is shown in Fig. 5.
If the voltages and currents from the output of the DAQand SMU
are normal, the automatic test system performsthe evaluations of
the DACs in the CMOS chip. There arethree 8 bit and two 12 bit DACs
in the CMOS chip. Two 8bit DACs are chosen for this paper. The
designed range ofthe output voltage of the eight bit DACs is from 2
V to0 V. The eight bit DAC has 256 codes, and each codecorresponds
to a voltage output. 256 voltages should bemeasured to attain the
transfer function of the DAC. Theblock diagram of DAC test is shown
in Fig. 6.
A while loop structure is adopted to change codes ofDACs in
order to complete the cycle test. Two voltages ofthe two DACs are
measured and acquired by the DAQ mod-ule in each cycle. Meanwhile,
the currents of the CMOSchip are monitored by the SMU. If the
currents are beyondthe range which is set as an error limit before
stating theprogram, the testing ends immediately.
If the test is completed successfully, 256 voltages willbe
acquired and stored for each DAC. The data could be dis-played
directly to attain the transfer function. Besides, theIntegral
Nonlinearity (INL) and Differential Nonlinearity(DNL) error of DAC
should be displayed as well.
For a DAC, DNL is the difference between the measuredchange and
the ideal 1 Least Significant Bit (LSB) changebetween any two
adjacent codes [12]. For the eight bitDAC used in here, 1 LSB
equals to 2
281 V. Usually, DNL iscalculated in LSB, and that means the
difference shouldbe divided by 1 LSB. The calculation of the DNL is
given by
DNLi xi xi 1 1LSB1LSB
1
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Fig. 8. Main user test interface.
Fig. 9. DNL and INL display interface.
406 Z. Wang et al. / Measurement 46 (2013) 402410
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Fig. 10. Transfer function of the DAC_A.
Fig. 11. DNL of the DAC_A.
Z. Wang et al. / Measurement 46 (2013) 402410 407
where x[i] represents the measured voltage correspondingto the
code of number i [13,14].
INL is a measurement of the maximum deviation from astraight
line passing through the endpoints of the DACtransfer function
[12]. INL can be calculated from the accu-mulation of DNL [13]. In
this paper, INL is given by
INLi xi x0 i 1LSB1LSB
2
which is derived from definition introduced in [12]. Theblock
diagram of the calculation of DNL and INL is shownin Fig. 7.
According to Eqs. (1) and (2), the calculation canbe conveniently
performed in LabVIEW by using itsarithmetic VIs.
The graphical nature of LabVIEW makes it convenient todisplay
the result through the waveform control. And theuser interface
could be designed friendly, clearly and beau-tifully. In this
program, a tab control is used in the front
panel of the software. The using of the tab control allowsall
the controls can be managed clearly with respect totheir usage. Two
option cards are created in the tab control.One option card is used
to show the main user interfaceand the transfer function of the
DACs as shown in Fig. 8,and the other is to show the DNL and INL
errors of theDACs as shown in Fig. 9.
4. Test results
In this project, the first group of 150 chips has beentested by
using the proposed automatic test system. Thetesting time for each
chip can be done within half a minutewhich includes the evaluation
of the logic functions andassessment of the performances of the
DACs within thechip. In order to demonstrate the results of the
DACs, oneset of results for a single chip is illustrated as
follows.
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Fig. 12. INL of the DAC_A.
Fig. 13. Transfer function of the DAC_B.
Fig. 14. DNL of the DAC_B.
408 Z. Wang et al. / Measurement 46 (2013) 402410
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Fig. 15. INL of the DAC_B.
Z. Wang et al. / Measurement 46 (2013) 402410 409
The two tested DACs are represented by the name ofDAC_A and
DAC_B.
The transfer function of the DAC_A is shown in Fig. 10.As shown,
the vertical axis is the voltage level and the hor-izontal axis is
the code number of the DAC. The designedvoltage level is from 2 V
to 0 V, and the test result showsthere are small deviations from
the designed values, butthe slop of the transfer function is a
smooth line. In orderto know the details of the error from the
designed transferfunction, the DNL and INL are given in Figs. 11
and 12.
As shown in Fig. 11, the DNL of the DAC_A is within1LSB at the
preceding half of the codes. The absolutevalue of DNL reaches to
almost 3LSB with the increase ofthe code, which means the output of
the DAC is gettingworse with respect to the increase of the code.
The INL iswithin 2LSB as shown in Fig. 12, but the points of theINL
are all scattered around the zero lines, which indicatesthat the
change of the DNL is spread around the center lineas well.
Fig. 13 shows the transfer function of the DAC_B whichis also a
smooth line with small deviations from designedvalues. The DNL and
INL are shown in Figs. 14 and 15.
As illustrated in Fig. 14, the DNL of the DAC_B is within2LSB,
which is better than the DNL of the DAC_A shown inFig. 11. This
indicates the performance of DAC_B is betterthan DAC_A. On the
other hand, the plot of the INL forDAC_B suggests that the changes
of the DNL are towardthe negative axis. This is demonstrated that
the most ofthe DNL points are in the negative sate.
5. Conclusions
In this paper, an advanced automatic test system basedon a NIs
PXI and LabVIEW programming environment for aCMOS chip has been
introduced. It has the properties ofincreasing the testing accuracy
by reducing the connectioninduced system error and illuminating the
human interac-tion error; improving the testing efficiency by using
auto-matic testing software; and reducing the workload for
the testing engineer during the sieving process. The auto-matic
test system completes the whole test of the CMOSchip within 5 min
and the testing time is more than 2 hwith the normal automatic test
system. The test resultshave shown that the proposed automatic
testing systemis able to perform the chip logical function
evaluationand verify its DACs output in a short time with great
accu-racy. It also demonstrated that the testing system can workin
real time. Besides, the modularization structure of thesystem makes
it convenient to be extended or modifiedfor different applications.
Only a little change to the pro-gram can help to test some more
parameters withoutchanging the connections of the hardware.
However, the automatic testing system still has room tobe
optimized with respect to the testing time. Such as thetrigger
function within the NI PXI which allows furtheringreduce the
processing time and improve the sieving effi-ciency. On the other
hand, the automatic testing systemcan be used for device with ADCs
with a few modificationof the system.
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http://www.analog.comhttp://www.analog.comA LabVIEW based automatic
test system for sieving chips1 Introduction2 System configuration3
Software system4 Test results5 ConclusionsReferences