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A Hybrid Wind-Solar Energy System: A NewRectifier Stage Topology
Abstract
Environmentally friendly solutions are becoming more prominent than ever
as a result of concern regarding the state of our deteriorating planet. This paper
presents a new system configuration of the front-end rectifier stage for a hybrid
wind/photovoltaic energy system. This configuration allows the two sources to
supply the load separately or simultaneously depending on the availability of the
energy sources. The inherent nature of this Cuk-SEPIC fused converter, additional
input filters are not necessary to filter out high frequency harmonics. Harmonic
content is detrimental for the generator lifespan, heating issues, and efficiency.
The fused multi input rectifier stage also allows Maximum Power Point Tracking
(MPPT) to be used to extract maximum power from the wind and sun when it is
available. An adaptive MPPT algorithm will be used for the wind system and a
standard perturb and observe method will be used for the PV system. Operational
analysis of the proposed system will be discussed in this paper. Simulation results
are given to highlight the merits of the proposed circuit.
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INTRODUCTION
W ith increasing concern of global warming and the depletion of fossil fuel
reserves, many are looking at sustainable energy solutions to preserve the earth
for the future generations. Other than hydro power, wind and photovoltaic
energy holds the most potential to meet our energy demands. Alone, wind energy
is capable of supplying large amounts of power but its presence is highly
unpredictable as it can be here one moment and gone in another. Similarly, solar
energy is present throughout the day but the solar irradiation levels vary due to
sun intensity and unpredictable shadows cast by clouds, birds, trees, etc. The
common inherent drawback of wind and photovoltaic systems are their
intermittent natures that make them unreliable. However, by combining these
two intermittent sources and by incorporating maximum power point tracking
(MPPT) algorithms, the system s power transfer efficiency and reliability can be
improved significantly.
W hen a source is unavailable or insufficient in meeting the load demands,
the other energy source can compensate for the difference. Several hybrid
wind/PV power systems with MPPT control have been proposed and discussed in
works [1]- [5]. Most of the systems in literature use a separate DC/DC boost
converter connected in parallel in the rectifier stage as shown in Figure 1 to
perform the MPPT control for each the renewable energy power sources [1]-[4].
A simpler multiinput structure has been suggested by [5] that combine the
sources from the DC-end while still achieving MPPT for each renewable source.
The structure proposed by [5] is a fusion of the buck and buck-boost converter.
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The systems in literature require passive input filters to remove the high
frequency current harmonics injected into wind turbine generators [6].
The harmonic content in the generator current decreases its lifespan and
increases the power loss due to heating [6]. In this paper, an alternative multi-
input rectifier structure is proposed for hybrid wind/solar energy systems. The
proposed design is a fusion of the Cuk and SEPIC converters. The features of the
proposed topology are: 1) the inherent nature of these two converters eliminates
the need for separate input filters for PFC [7]-[8]; 2) it can support step up/down
operations for each renewable source (can support wide ranges of PV and wind
input); 3) MPPT can be realized for each source; 4) individual and simultaneous
operation is supported.
.
Figure 1: Hybrid system with multi-connected boost converter
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PROPOSED MULTI-INPUT RECTIFIER STAGE
A system diagram of the proposed rectifier stage of a hybrid energy system
is shown in Figure 2, where one of the inputs is connected to the output of the PV
array and the other input connected to the output of a generator. The fusion of
the two converters is achieved by reconfiguring the two existing diodes from each
converter and the shared utilization of the Cuk output inductor by the SEPIC
converter. This configuration allows each converter to operate normally
individually in the event that one source is unavailable. Figure 3 illustrates the
case when only the wind source is available. In this case, D1 turns off and D2 turns
on; the proposed circuit becomes a SEPIC converter and the input to output
voltage relationship is given by (1). On the other hand, if only the P source is
available, then D2 turns off and D1 will always be on and the circuit becomes a
Cuk converter as shown in Figure 4 The input to output voltage relationship is
given by (2). In both cases, both converters have step-up/down capability, which
provide more design flexibility in the system if duty ratio control is utilized to
perform MPPT control.
Figure 5 illustrates the various switching states of the proposed converter.
If the turn on duration of M1 is longer than M2, then the switching states will be
state I,II, IV. Similarly, the switching states will be state I, III, IV if the switch
conduction periods are vice versa. To provide a better explanation, the inductor
current waveforms of each switching state are given as follows assuming that d 2 >
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d 1; hence only states I, III, IV are discussed in this example. In the following, Ii,PV
is the average input current from the PV source; Ii,W is the RMS input current
after the rectifier (wind case); and Idc is the average system output current. The
key waveforms that illustrate the switching states in this example are shown in
Figure 6. The mathematical expression that relates the total output voltage and
the two input sources will be illustrated in the next section.
State I (M1 on, M2 on):
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State III (M1 off, M2 on):
State IV (M1 off, M2 off):
Figure 2: Proposed rectifier stage for a Hybrid wind/PV system
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Figure 3: Only wind source is operational (SEPIC)
Figure 4: Only PV source is operation (Cuk)
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Figure 5 (I-IV): switching states within a switching cycle
Figure 6: Proposed circuit inductor waveforms
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find an expression for the output DC bus voltage, Vdc, the volt-balance of the
output inductor, L2, is examined according to Figure 6 with d 2 > d 1. Since the net
change in the voltage of L2 is zero, applying volt-balance to L2 results in (3). The
expression that relates the average output DC voltage ( Vdc) to the capacitor
voltages ( vc1 and vc2) is then obtained as shown in (4), where vc1 and vc2 can
then be obtained by applying volt-balance to L1 and L3 [9]. The final expression
that relates the average output voltage and the two input sources ( VW and VPV )
is then given by (5). It is observed that Vdc is simply the sum of the two output
voltages of the Cuk and SEPIC converter. This further implies that Vdc can be
controlled by d 1 and d 2 individually or simultaneously.
The switches voltage and current characteristics are also provided in this
section. The voltage stress is given by (6) and (7) respectively. As for the current
stress, it is observed from Figure 6 that the peak current always occurs at the end
of the on-time of the MOSFET. Both the Cuk and SEPIC MOSFET current consists
of both the input current and the capacitors ( C 1 or C 2) current. The peak current
stress of M1 and M2 are given by (8) and (10) respectively. Leq1 and Leq2, given
by (9) and (11), represent the equivalent inductance of Cuk and SEPIC converter
respectively. The PV output current, which is also equal to the average input
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current of the Cuk converter is given in (12). It can be observed that the average
inductor current is a function of its respective duty cycle ( d 1). Therefore by
adjusting the respective duty cycles for each energy source, maximum power
point tracking can be achieved.
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MPP T CONTROL OF P ROP OSED CIRCUITA common inherent drawback of wind and PV systems is the intermittent
nature of their energy sources. W ind energy is capable of supplying large amountsof power but its presence is highly unpredictable as it can be here one moment
and gone in another. Solar energy is present throughout the day, but the solar
irradiation levels vary due to sun intensity and unpredictable shadows cast by
clouds, birds, trees, etc. These drawbacks tend to make these renewable systems
inefficient. However, by incorporating maximum power point tracking (MPPT)
algorithms, the systems power transfer efficiency can be improved significantly.To describe a wind turbine s power characteristic, equation (13) describes the
mechanical power that is generated by the wind [6].
The power coefficient (Cp) is a nonlinear function that represents the
efficiency of the wind turbine to convert wind energy into mechanical energy. It is
dependent on two variables, the tip speed ratio (TSR) and the pitch angle. The
TSR, , refers to a ratio of the turbine angular speed over the wind speed. The
mathematical representation of the TSR is given by (14) [10]. The pitch angle, ,
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refers to the angle in which the turbine blades are aligned with respect to its
longitudinal axis.
Figure 7 and 8 are illustrations of a power coefficient curve and power
curve for a typical fixed pitch ( =0) horizontal axis wind turbine. It can be seen
from figure 7 and 8 that the power curves for each wind speed has a shape similar
to that of the power coefficient curve. Because the TSR is a ratio between the
turbine rotational speed and the wind speed, it follows that each wind speed
would have a different corresponding optimal rotational speed that gives the
optimal TSR. For each turbine there is an optimal TSR value that corresponds to a
maximum value of the power coefficient (Cp,max) and therefore the maximum
power. Therefore by controlling rotational speed, (by means of adjusting
theelectrical loading of the turbine generator) maximum power can be obtained
for different wind speeds.
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Figure 7: Power Coefficient Curve for a typical wind turbine
Figure 8: Power Curves for a typical wind turbine A solar cell is comprised of a P-N junction
semiconductor
that produces currents via the photovoltaic effect. PV arrays are constructed by
placing numerous solar cells connected in series and in parallel [5]. A PV cell is a
diode of a large-area forward bias with a photovoltage and the equivalent circuit
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is shown by Figure 9 [11]. The current-voltage characteristic of a solar cell is
derived in [12] and [13] as follows:
Where
Iph = photocurrent,
ID = diode current,I0 = saturation current,
A = ideality factor,
q = electronic charge 1.6x10-9,
kB = Boltzmann s gas constant (1.38x10-23),
T = cell temperature,
Rs = series resistance,Rsh = shunt resistance,
I = cell current,
V = cell voltage
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Figure 9: PV cell equivalent circuit
Typically, the shunt resistance (Rsh) is very large and the series resistance
(Rs) is very small [5]. Therefore, it is common to neglect these resistances in order
to simplify the solar cell model. The resultant ideal voltage-current characteristic
of a photovoltaic cell is given by (17) and illustrated by Figure 10. [5]
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The typical output power characteristics of a PV array under various
degrees of irradiation is illustrated by Figure 11. Itcan be observed in Figure 11
that there is a particular optimal voltage for each irradiation level that
corresponds to maximum output power. Therefore by adjusting the output
current (or voltage) of the PV array, maximum power from the array can be
drawn.
Figure 11: PV cell power characteristics
Due to the similarities of the shape of the wind and PV array power curves,
a similar maximum power point tracking scheme known as the hill climb search
(HCS) strategy is often applied to these energy sources to extract maximum
power. The HCS strategy perturbs the operating point of the system and observesthe output. If the direction of the perturbation (e.g an increase or decrease in the
output voltage of a PV array) results in a positive change in the output power,
then the control algorithm will continue in the direction of the previous
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perturbation. Conversely, if a negative change in the output power is observed,
then the control algorithm will reverse the direction of the pervious perturbation
step. In the case that the change in power is close to zero (within a specified
range) then the algorithm will invoke no changes to the system operating point
since it corresponds to the maximum power point (the peak of the power
curves).
The MPPT scheme employed in this paper is a version of the HCS strategy.
Figure 12 is the flow chart that illustrates the implemented MPPT scheme.
Figure 12: General MPPT Flow Chart for wind and PV
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DRIVER CIRCUIT:
It is used to pr ov ide 9 to 20 volt s to swi tch th e MOSFET Swi tch es
of th e in v er ter. Dri v er amp lif ies th e volt age f r o m mi c r oco ntr oll er w h ich is
5volt s. A lso it h as an o ptoco up ler fo r isol at ing purp o se . S o damage to
MOSFET is pre v en ted.
Fig 2.5:Driver circuit .
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COMPONENTS:
1.IRFP460
2.Diode N4007
3.Capacitors
1000uF/50V
1000uF/25V
1000uF/250V
4.Optocoupler MCT2E
5.Transistors
2N2222
CK100
6.Resistors
1k
100ohm
]
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DRIVER CIRCUIT OPERATION:
The driver circuit forms the most important part of the hardware unit
because it acts as the backbone of the inverter because it gives the triggering
pulse to the switches in the proper sequence. The diagram given above gives the
circuit operation of the driver unit. The driver unit contains the following
important units.
A. Optocoupler
B. Totem pole
C. Capacitor
D. Supply
E. Diode
F. Resistor
2.13. OPTOCOUPLER:
Optocoupler is also termed as optoisolator. Optoisolator a device which
contains a optical emitter, such as an LED, neon bulb, or incandescent bulb, and
an optical receiving element, such as a resistor that changes resistance with
variations in light intensity, or a transistor, diode, or other device that conducts
differently when in the presence of light. These devices are used to isolate the
control voltage from the controlled circuit.
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TRIGGERING UNIT:
PIC 16F877A MICROCONTROLLER
3.1. INTRODUCTION :
W e are using PIC 16F877A for producing switching pulses to multilevel
inverter. so as to use those vectors which do not generate any common
mode voltage at the inverter poles. .This eliminates common mode
voltageAlso it is used to eliminate capacitor voltage unbalancing. The
microcontroller are driven via the driver circuit so as to boost the voltage
triggering signal to 9V.To avoid any damage to micro controller due to direct
passing of 230V supply to it we provide an isolator in the form of optocoupler in
the same driver circuit.
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3.2. FEATURES OF PIC MICROCONTROLLER :
Th e mi c r oco ntr oll er h as th e follo wing f ea tures:
1.High- Performance RISC CPU:
Only 35 single- word instructions to learn .Hence it is user friendly.easy
to use
All single - cycle instructions except for program branches, which are
two-cycle
Operating speed: DC 20 MHz clock input DC 200 ns instruction
cycle
Up to 8K x 14 words of Flash Program Memory, Up to 368 x 8 bytes of Data
Memory(RAM), Up to 256 x 8 bytes of EEPROM Data Memory. It is
huge one
2.Per iph eral Features :
Timer0: 8-bit timer/counter with 8 bit prescaler. It is used for
synchronisation
Timer1: 16-bit timer/counter with prescaler, can be incremented during
Sleep
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Timer2:8-bit timer/counter with 8-bit period register, prescaler and
postscaler
Two Capture , Compare and some P W M modules, having following
features
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max . resolution is 200 ns
- PW M maximum resolution that is 10-bit
Synch ronous Ser ial Port ( SSP) w ith SPI (Master mode) andI2C(Master/ Slave)
y Universal Synchronous Asynchronous Receiver Transmitter with 9 bit
address
y Parallel Slave Port (PSP) 8 bits wide with external RD, W R and CS
controls
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B lock d iagram of P IC 16 F877A:
Fig 3.1: Block diagram of PIC 16F877A
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PIN DIAGRAM OF PIC 16 F877A
Fig 3.2: Pin diagram of 40 pin dua l inl ine pa ck age of PIC 16F877A
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TRIGEERING CIRCUIT:
Fig 3.3: Triggering circuit.
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y VREF+.
y RA4/T0CKI/C1OUT.
y T0CKI.
y C1OUT.
y RA5/AN4/SS/C2OUT/SS/C2OUT.
I/O PO RTS:
Some pins for these I/O ports are multiplexed with an alternate function for
the peripheral features on the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin.
PORTA AND THE TRISA REGISTER:
PORTA is a 6-bit wide, bidirectional port. The corresponding data direction
register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a High Impedance mode).
Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin). Reading the PORTA
register reads the status of the pins, whereas writing to it will write to the portlatch. All write operations are read-modify-write operations. Therefore, a write to
a port implies that the port pins are read; the value is modified and then written
to the port data latch.
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Pin RA4 is multiplexed with the Timer0 module clock input to become the
RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open-drain
output. All other PORTA pins have TTL input levels and full CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs and the analog VREF input
for both the A/D converters and the comparators. The operation of each pin is
selected by clearing/setting the appropriate control bits in the ADCON1 and/or
CMCON registers. The TRISA register controls the direction of the port pins even
when they are being used as analog inputs. The user must ensure the bits in the
TRISA register are maintained set when using them as analog inputs.
PORT B AND THE TRISB REGISTER:
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction
register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin). Three pins of PORTB are
multiplexed with the In-Circuit Debugger and Low-Voltage Programming function:
RB3/PGM, RB6/PGC and RB7/PGD.
Four of the PORTB pins, RB7:RB4, have an interruption- change feature.
Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4pin configured as an output is excluded from the interruption- change
comparison). The input pins (of RB7:RB4) are compared with the old value latched
on the last read of PORTB. The mismatch outputs of RB7:RB4 are OR ed
together to generate the RB port change interrupt with flag bit RBIF (INTCON).
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make a pin an output, while other peripherals override the TRIS bit to make a pin
an input. Since the TRIS bit override is in effect while the peripheral is enabled,
read-modify write instructions (BSF, BCF, XOR W F) with TRISC as the destination,
should be avoided. The user should refer to the corresponding peripheral section
for the correct TRIS bit settings.
PORTD AND TRISD REGISTERS:
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is
individually configurable as an input or output. PORTD can be configured as an 8-
bit wide microprocessor port (Parallel Slave Port) by setting control bit, PSP MODE
(TRISE). In this mode, the input buffers are TTL.
PORTE AND TRISE REGISTER:
PORTE has three pins (RE0/RD/AN5, RE1/ W R/AN6 and RE2/CS/AN7) which
are individually configurable as inputs or outputs. These pins have Schmitt Trigger
input buffers. The PORTE pins become the I/O control inputs for the
microprocessor port when bit PSPMODE (TRISE) is set. In this mode, the user
must make certain that the TRISE bits are set and that the pins are
configured as digital inputs. Also, ensure that ADCON1 is configured for digital
I/O. In this mode, the input buffers are TTL. Register 4-1 shows the TRISE register
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which also controls the Parallel Slave Port operation. PORTE pins are multiplexed
with analog inputs.
W hen selected for analog input, these pins will read as 0 s. TRISE controls.
The direction of the RE pins, even when they are being used as analog inputs. The
user must make sure to keep the pins configured as inputs when using them as
analog inputs.
TIMER0 INTERRUPT:
The TMR0 interrupt is generated when the TMR0 register overflows from
FFh to 00h. This overflow sets bit TMR0IF (INTCON). The interrupt can be
masked by clearing bit TMR0IE (INTCON). Bit TMR0IF must be cleared in
software by the Timer0 module Interrupt Service Routine before re-enabling this
interrupt. The TMR0 interrupt cannot awaken the processor from Sleep since the
timer is shut-off during Sleep.
TIMER1 MODULE:
The Timer1 module is a 16-bit timer/counter consisting of two 8-bit
registers (TMR1H and TMR1L) which are readable and writable. The TMR1
register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to
0000h. The TMR1 interrupt, if enabled, is generated on overflow which is latched
in interrupt flag bit, TMR1IF (PIR1). This interrupt can be enabled/disabled by
setting or clearing TMR1 interrupt enable bit, TMR1IE (PIE1). Timer1 can
operate in one of two modes:
As a Timer
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As a Counter
The operating mode is determined by the clock select bit, TMR1CS (T1CON).
In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it
increments on every rising edge of the external clock input. Timer1 can be
enabled/disabled by setting/clearing control bit, TMR1ON (T1CON).Timer1
also has an internal Reset input . This Reset can be generated by either of the
two CCP modules. Shows the Timer1 Control register. W hen the
Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and
RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC value is ignored
and these pins read as 0 .
TIMER2 MODULE:
Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as
the P W M time base for the P W M mode of the CCP module(s). The TMR2 register
is readable and writable and is cleared on any device Reset. The input clock(FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON). The Timer2 module has an 8-bit period register,
PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on
the next increment cycle. PR2 is a readable and writable register. The PR2 register
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is initialized to FFh upon Reset. The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2
interrupt (latched in flag bit, TMR2IF (PIR1)). Timer2 can be shut-off by
clearing control bit, TMR2ON (T2CON), to minimize power consumption.
3. 4 . PULSE WIDTH MODULATION TECHNIQ UE :
The advent of the transformerless multilevel inverter topology has brought
forth various pulse width modulation (P W M) schemes as a means to control the
switching of the active devices in each of the multiple voltage levels in the
inverter. The most efficient method of controlling the output voltage is to
incorporate pulse width modulation control (P W M control) within the inverters.
In this method, a fixed d.c. input voltage is supplied to the inverter and a
controlled a.c. output voltage is obtained by adjusting the on and off periods of
the inverter devices. Voltage-type P W M inverters have been applied widely to
such fields as power supplies and motor drivers. This is because: (1) such inverters
are well adapted to high-speed self turn-off switching devices that, as solid-state
power converters, are provided with recently developed advanced circuits; and
(2) they are operated stably and can be controlled well.
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The P W M control has the following advantages:
(i) The output voltage control can be obtained without any additionalcomponents.
(ii) W ith this type of control, lower order harmonics can be eliminated or
minimized along with its output voltage control. The filtering
requirements are minimized as higher order harmonics can be filtered
easily.
The commonly used P W M control techniques are:
(a) Sinusoidal pulse width modulation (sin P W M)
(b) Space vector P W M
The performance of each of these control methods is usually judged based
on the following parameters: a) Total harmonic distortion (THD) of the voltageand current at the output of the inverter, b) Switching losses within the inverter,
c) Peak-to-peak ripple in the load current, and d) Maximum inverter output
voltage for a given DC rail voltage.
From the above all mentioned P W M control methods, the Sinusoidal pulse
width modulation (sinP W M) is applied in the proposed inverter since it has
various advantages over other techniques. Sinusoidal P W M inverters provide an
easy way to control amplitude, frequency and harmonics contents of the output
voltage.
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technique, which is based on the principle of comparing a triangular carrier signal
with a sinusoidal reference waveform (natural sampling).
The figure below gives the sinusoidal pulse width modulation.
(a)
(b)
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(a) Modulating/reference and carrier waveform .
(b) Line-to-neutral switching pattern.
(c) Line-to-line output waveform.
Graph. 3.1 (a), (b), (c) Sinusoidal Pulse W idth Modulation (SP W M).
By varying the modulation index M, the RMS output voltage can be varied.
It can be observed that the area of each pulse corresponds approximately to the
area under the sine-wave between the adjacent midpoints of off periods on the
gating signals.
The phase voltage can be described by the following expressions:
(c)
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where w m is the angular frequency of modulating or sinusoidal signal.
w c is the angular frequency of the carrier signal.
M is modulation index.
E is the dc supply voltage.
f is the displacement angle between modulating and carrier signals.
and Jo and Jn are Bessel functions of the first kind.
The amplitude of the fundamental frequency components of the output is
directly proportional to the modulation depth. The second term of the equationgives the amplitude of the component of the carrier frequency and the harmonics
of the carrier frequency. The magnitude of this term decreases with increased
modulation depth. Because of the presence of sin( m T /2), even harmonics of the
carrier are eliminated. Term 3 gives the amplitude of the harmonics in the
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sidebands around each multiple of the carrier frequency. The presence of
sin((m+n ) T / 2) indicated that, for odd harmonics of the carrier, only even-order
sidebands exist, and for even harmonics of the carrier only oddorder sidebands
exist. In addition, increasing carrier or switching frequency does not decrease the
amplitude of the harmonics, but the high amplitude harmonic at the carrier
frequency is shifted to higher frequency. Consequently, requirements of the
output filter can be improved. However, it is not possible to improve the total
harmonic distortion without using output filter circuits. In multilevel case, SP W M
techniques with three different disposed triangular carriers were proposed as
follows:
1. All the carriers are alternatively in opposition (APO disposition)
2. All the carriers above the zero value reference are in phase among
them, but in opposition with those below (PO disposition)
3. All the carriers are in phase (PH disposition)4. Multi carrier modulation technique
In the proposed inverter circuit the multi carrier modulation technique is
employed.
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3.5. PROPOSED MODULATION TECHNIQ UE
3.5.1 Mult icar ier Modulat ion
Th is tech nique in volv es th e c arrier based PWM
3.5.2 Carr ier B ased PWM
These are the classical and most widely used methods of pulse width
modulation. They have as common characteristic subcycles of constant time
duration, a subcycle being defined as the total duration Ts during which an active
inverter leg assumes two consecutive switching states of opposite voltage
polarity. Operation at subcycles of constant duration is reflected in the harmonic
spectrum by two salient sidebands, centered around the carrier frequency, and
additional frequency bands around integral multiples of the carrier.
The multi carrier modulation technique is very suitable for a multilevel invertercircuit. By employing this technique along with the multilevel topology, thelow THD output waveform without any filter circuit is possible. Switchingdevices, in addition, turn on and off only one time per cycle. That canovercome the switching loss problem, as well as EMI problem. The P W Mswitching pattern developed for the proposed inverter is given below.
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SIMULATION RESULTS
In this section, simulation results from PSIM 8.0.7 is given to verify that
proposed multi-input rectifier stage can support individual as well as
simultaneous operation. Thespecifications for the design example are given in
TABLE I. Figure 13 illustrates the system under the condition where the wind
source has failed and only the PV source (Cuk converter mode) is supplying power
to the load. Figure 14 illustrates the system where only the wind turbine
generates power to the load (SEPIC converter mode). Finally, Figure 15 illustrates
the simultaneous operation (Cuk-SEPIC fusion mode) of the two sources where
M2 has a longer conduction cycle (converter states I, IV and III see Figure 5).
TABLE I. Design Specifications
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Figure 13 : Individual operation with only PV source (Cuk operation) Top: Output power,
Bottom: Switch currents (M1 and M2)
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Figure 14 : Individual operation with only wind source (SEPIC operation) (I) The injected three
phase generator current; (II) Top: Output power, Bottom: Switch currents (M1 and M2)
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Figure 15 : Simultaneous operation with both wind and PV source (Fusion mode with Cuk and
SEPIC)(I) The injected three phase generator current; (II) Top: Output power, Bottom: Switch
currents (M1 and M2)
Figure 16 and 17 illustrates the MPPT operation of the PV component of
the system (Cuk operation) and the W ind component of the system (SEPIC
operation) respectively.
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Figure 16 : Solar MPPT PV output current and reference current signal (Cuk operation)
Figure 17 : W ind MPPT Generator speed and reference speed signal (SEPIC operation)
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CONCLUSION
In this paper a new multi-input Cuk-SEPIC rectifier stage for hybridwind/solar energy systems has been presented. The features of this circuit are: 1)
additional input filters are not necessary to filter out high frequency harmonics; 2)
both renewable sources can be stepped up/down (supports wideranges of PV and
wind input); 3) MPPT can be realized for each source; 4) individual and
simultaneous operation is supported. Simulation results have been presented to
verify the features of the proposed topology.
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