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576 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH
2005
A High-Voltage Output Driver in a 2.5-V 0.25-mCMOS
Technology
Bert Serneels, Student Member, IEEE, Tim Piessens, Michiel
Steyaert, Fellow, IEEE, andWim Dehaene, Senior Member, IEEE
AbstractThe design of a high-voltage output driver in a
digital0.25- m 2.5-V technology is presented. The use of stacked
deviceswith a self-biased cascode topology allows the driver to
operateat three times the nominal supply voltage. Oxide stress and
hotcarrier degradation is minimized since the driver operates
withinthe voltage limits imposed by the design rules of a
mainstreamCMOS technology. The proposed high-voltage architecture
uses aswitching output stage.
The realized prototype delivers an output swing of 6.46 V to
a50- load with a 7.5-V supply and an input square wave of 10 MHz.A
PWM signal with a dual-tone sinusoid at 70 kHz and 250 kHzresults
in an IM3 of 65 dB and an IM2 of 67 dB. The on-resis-tance is 5.9
.
Index TermsBuffer circuits, CMOS integrated circuits,
high-voltage techniques.
I. INTRODUCTION
DRIVEN by the ever-growing demand for more computa-tional power,
deep-submicron and even nanometer tech-nologies become more and
more prominent for digital circuits.Deep-submicron and nanometer
CMOS technologies provide asolution for the growing integration
density of VLSI circuits andthe low-power requirements of complex
signal processing appli-cations. Since these technologies require
low supply voltages,the design of analog circuits with high output
power demands isrunning into its limits.
The objective is to tolerate the high supply voltage
withsufficient lifetime. Two approaches can be used to
designhigh-voltage tolerant output drivers. The first approach is
theuse of customized silicon technologies. These technologiesresult
in high-voltage tolerant transistors at the cost of a moreexpensive
process and a degraded performance. Examplesare lightly doped drain
(LDD) CMOS technologies and thickgate-oxide transistors. In a LDD
transistor, the electric fieldacross the channel is lowered by
reducing the doping gradientat the gate edge. The use of a thick
gate-oxide transistor can beseen as a device from a previous
generation implemented in amore advanced technology. The second
approach is the use ofalternative circuit topologies and
drain-source engineering in astandard CMOS technology to reliably
tolerate the high supplyvoltage. An advantage of this approach is
that it can be fully
Manuscript received July 28, 2004; revised September 27, 2004.B.
Serneels, M. Steyaert, and W. Dehaene are with the ESAT-MICAS
Laboratory, Katholieke Universiteit Leuven, B-3001 Leuven,
Belgium (e-mail:[email protected]).
T. Piessens is with ICsence, B-3001 Leuven, Belgium
(e-mail:[email protected]).
Digital Object Identifier 10.1109/JSSC.2005.843599
Fig. 1. Block diagram of the high-voltage output driver.
integrated within a digital technology without extra
processcosts. The goal is to find the correct operating point such
thatthe voltage across the terminals of the transistors is
limited.Examples of this approach can be found in [1][3]. These
I/Ocircuits use the concept of two stacked devices, with a
fixedbias voltage to tolerate the high supply voltage. However,
twostacked transistors limit the maximum operating voltage, to
twotimes the nominal supply voltage, . Ref. [4] presents anI/O
buffer operating at 2.5 times . This topology usesstacked
transistors with a variable bias voltage. A disadvantageof this
circuit is the large number of stacked devices.
This paper describes a high-voltage output driver in a stan-dard
2.5-V 0.25- m CMOS technology. The presented driveruses stacked
devices with a self-biasing technique [5]. This tech-nique allows
the driver to run on three times the nominal supplyvoltage with a
minimum number of stacked devices. The driveroperates within the
electrical design rules of a commerciallyavailable CMOS technology
without the use of extra processsteps. Section II gives a system
description of the driver. InSection III, the self-biasing cascode
technique is explained forstatic and transient operation of the
driver. Section IV describesthe design of a high-voltage output
driver. Measurement resultsare shown in Section V. Finally, in
Section VI, conclusions aregiven.
II. SYSTEM DESCRIPTIONFig. 1 shows the block diagram of the
high-voltage output
driver. One can distinguish three major parts: a level-shifter,
a0018-9200/$20.00 2005 IEEE
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SERNEELS et al.: A HIGH-VOLTAGE OUTPUT DRIVER IN A 2.5-V 0.25- m
CMOS TECHNOLOGY 577
p-switch block, and its complementary n-switch block. The p-and
n-switch blocks consist of a dynamic bias voltage circuit,stacked
output transistors, and a tapered buffer. This structurecan also be
seen as a self-biased cascode topology where thebias voltage of the
transistors closest to the output depend onthe output voltage.
Since it is a switching type output driver,all stacked output
transistors are either in the cut-off or in thetriode region. To
guarantee a minimal lifetime of ten years as de-scribed by the
electrical design rules of the technology used, themaximum voltage
across the terminals of any transistor is equalto the nominal
supply voltage. This limitation prevents oxidebreakdown and
minimizes hot carrier degradation. Since eachswitch block consists
of three stacked devices the maximum al-lowable supply voltage of
the circuit is three times the nominalsupply voltage. However,
transient events prevent having such alarge output voltage. The new
high-voltage driver topology of-fers a significant area reduction
compared to a similar outputdriver [4] with respect to the output
stacked transistors. In [4]not all of the output stacked
transistors are switched from trioderegion to cut-off and vice
versa. Instead, they are switched fromtriode region to a state in
which they act as a diode. Therefore,the voltage drop over these
transistors is lower than if they werein cut-off. This means that
more stacked transistors are neededto tolerate the same supply
voltage. Moreover, the width of theoutput transistors needs to be
increased to achieve a comparableon-resistance as the presented
output driver.
One can derive a simplified formula for the efficiency of
thedriver:
(1)
in which represents the load resistance driven by theoutput
driver and represents the combined on-resistance ofthe stacked
transistors. No dynamic power consumption is takeninto account.
This is a reasonable assumption when the on-resis-tance is rather
large. However, for a higher efficiency, dynamicpower consumption
becomes a real issue and the efficiency mustbe checked after
design. For a desired value of , the ratio ofthe width and the
length of the stacked output transistors is de-termined through the
simplified formula of the resistance of atransistor in triode
region:
(2)
where is the number of stacked transistors per switch-block.In
this work, is three.
III. SELF-BIASED CASCODE TOPOLOGYFig. 2 shows the schematic of
the self-biased cascode
topology of the n-switch block. The analysis and operation
arethe same for the p-switch block since it is the complement ofthe
n-block. This topology sets the bias voltage of transistorin two
ways: through a resistive division comprised of and
, triggered on by , or by the gate voltage of whichpasses
through . For the analysis of the self-biased cascodetopology, two
operating regimes must be considered: static andtransient.
Fig. 2. Schematic of the self-biased cascode topology.
Fig. 3. Transfer characteristic of an NMOS switch and the I V
curve fora fixed drainsource voltage.
A. Static OperationIn this section the two static states of the
high-voltage
driver (high and low) and the transitions between them will
bediscussed. Fig. 3 shows a transfer characteristic of an
NMOStransistor used as a switch and its curve for a
fixeddrainsource voltage. Since in this topology, all transistors
areused as switches, the different regions stated in this figure
areused to clarify the following analysis. A transistor in the
cut-offregion corresponds to an open circuit and a transistor in
thetriode region corresponds to a short circuit.
First, consider the case in which the output voltage
switchesfrom low to high. In the previous state when the output was
low,the transistors , and were in the triode region andthe internal
nodes and were discharged. Initially, tran-sistor is in the cut-off
region. As a consequence, node ischarged to and then slowly rises
to due to thesubthreshold current. To prevent oxide breakdown inis
set at a fixed voltage of . is now in the cut-offregion.
Consequently, node is charged to . Thesubthreshold current is again
responsible for further chargingup to . To prevent oxide breakdown,
now in , the max-imum voltage on is . is now in the cut-off
re-gion. Since and both have a voltage drop offrom drain to source,
the theoretical maximum output voltagewill be . During operation
however, the drainsourcevoltage of will be lower than the nominal
supply voltage inthe high-output state. In this state, the output
voltage is given by
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578 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH
2005
Fig. 4. Transient simulation of the voltage on the terminals of
the stackedoutput transistors. (a) Drain voltages of M ;M ; and M ,
(b) Gate voltagesofM ;M ; andM .
the resistive division of the on-resistance of the PMOS
outputstacked transistors, which are in the triode region and the
loadresistance, . This headroom will become useful for tran-sient
operation as will be seen later on. Fig. 4(a) shows a tran-sient
simulation of the drain voltages of the output transistors.The
voltage on is, in this state, given by a resistive divisionbetween
the output and the fixed bias voltage of . This resis-tive division
of and is triggered on by which is in thetriode region. The
resistive division and sets in thecut-off region.
Next, consider the case in which the output switches fromhigh to
low. In the previous state and were in thecut-off region and the
output was high. First, transistor is setin the triode region. As a
consequence, node is discharged.Since the gate bias of was set at
enters thetriode region and its gatesource voltage remains within
limits.Node is now discharged through and . Finally, thegatesource
voltage of will be larger than its and theoutput is discharged. To
reduce the oxide stress in , its gatevoltage must be lowered from
to . The gatevoltage of is now directly given by the fixed bias
voltage of
which passes through . is in the triode region. isnow in the
cut-off region and consequently breaks the resistive
division and . Fig. 4(b) shows a transient simulation ofthe gate
voltages of the output transistors.
B. Transient OperationThis section describes the problems and
solutions during tran-
sient switching of the high-voltage output driver. The most
crit-ical transition for the n-switch block is the high-to-low
transitionof the output. A low-to-high transition of node
switchesfrom cut-off to the triode region. The faster the
transition of ,the faster enters the triode region and the faster
gets dis-charged. Since the gate voltage of is fixed, its
gatesourcevoltage, and as a consequence, its state, is completely
deter-mined by the voltage on node . To avoid hot carrier effects
in
, resulting from a large drainsource voltage, node mustbe
discharged with the same speed as node . This is possiblefor a
relatively slow transition of . But, for a fast transition,the
delay of for entering from cut-off to the triode regionresults in
an overshoot on its drainsource voltage. Therefore,a low-pass
filter comprised of and is added to soften thetransitions at . The
same problem also occurs with transistor
. The transient event on the terminals of is solved in twoways.
First, the voltage headroom, originating from the resis-tive
division of the on-resistance with the output load, coversthe delay
of for the transition into the triode region. Second,an extra
capacitor is added on top of the already quite largegatedrain
capacitance of . During a high-to-low transitionof the output, the
voltage on node switches fromdown to . Therefore, the switching of
node helpsto discharge the output node due to the strong capacitive
cou-pling. However, during a low-to-high transition of the
output,the increased gatedrain capacitance of acts together withthe
resistances and as a high-pass filter. This results inan overshoot
on the steady-state voltage of node . Therefore,capacitance is
added which acts as a low-pass filter for thetransient overshoot on
. The necessary capacitance value of
can be calculated in two ways: the time-domain approachand the
frequency-domain approach.
1) Time Domain: For the time-domain approach, considerFig. 5,
which shows a model of the bias circuit of for thelow-to-high
transition. The assumption is made that the PMOSstacked output
transistors are already in the triode region and,as a consequence,
they can be represented by their accumula-tive on-resistance. The
same assumption is made for the NMOSstacked output transistors
which are in the cut-off region.is the voltage across and is the
voltage across .These two voltages define the gate voltage of (node
).The electrical network can then be described by the
followingsystem of differential equations:
(3)
(4)
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SERNEELS et al.: A HIGH-VOLTAGE OUTPUT DRIVER IN A 2.5-V 0.25- m
CMOS TECHNOLOGY 579
Fig. 5. Model of the bias circuit ofM for the low-to-high
transition.
with , and and with thefollowing starting conditions: .In matrix
form:
(5)
or
(6)
The steady-state solution of this system of differential
equationsis the solution of (7):
(7)
Therefore, the steady-state solution is
(8)
Assume and are the eigenvalues of matrix with theiraccompagning
eigenvectors and . The global solution of(6) can then be described
by the following equation:
(9)
With, after some simplification, :
(10)
(11)and
(12)
(13)
From (8), (9), (12), and the initial conditions, the
constantsand can be found:
(14)
The voltage on node corresponds with in this model.For a
positive step function, the exponential terms in the solutionof (9)
can lead to an overshoot if the signs of the productsand are
positive. One can see that the exponential termcorresponding with
always has a negative sign. This meansthat the contribution of this
term in the solution of in (9)can never lead to an overshoot on the
steady-state solution. Theexponential term of corresponding with
has a negativesign if the following condition for holds:
(15)
Which results in
(16)
One can see from (14) that the exponential term of
cor-responding with can even be completely cancelled out if
is chosen.2) Frequency Domain: For the frequency-domain
approach,
consider the transfer function (TF) from out to in Fig. 5:
(17)
For dc-operation this becomes
(18)
which is the same as the steady-state solution from the
time-do-main approach. For the frequency behavior, one must
considerthe following pole and zero:
(19)
(20)
A small results in which leads to the bode plotof Fig. 6(a). In
this graph, one can see that the gain for highfrequencies is larger
than the dc-gain which can lead to voltageovershoots during
transients. On the other hand, if is largeenough, the situation as
shown in Fig. 6(b) is applicable. Thehigh-frequency gain is now
lower than the dc-gain, which resultsin a suppression of
high-frequency transients. The requirementfor a stable voltage on
can be rewritten as . Aftersome calculation, this results in
(21)
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580 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH
2005
Fig. 6. Bode plot of the transfer function from out to g . (a) f
> f . (b) f