A Framework for Efficient Rapid Prototyping by Virtually Enlarging FPGA Resources Shinya Takamaeda-Yamazaki † , Kenji Kise ‡ † Nara Institute of Science and Technology (NAIST), Japan ‡ Tokyo Institute of Technology (Tokyo Tech), Japan ReConFig2014 Session 4B (PE) 10:15-10:40, Dec 9, 2014
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A Framework for Efficient Rapid Prototyping by Virtually Enlarging FPGA Resources (ReConFig2014@Cancun, Mexico)
A Framework for Efficient Rapid Prototyping by Virtually Enlarging FPGA Resources (ReConFig2014@Cancun, Mexico) flipSyrup, a new framework for rapid prototyping is proposed.
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A Framework for Efficient Rapid Prototyping by Virtually Enlarging FPGA Resources
Shinya Takamaeda-Yamazaki†, Kenji Kise‡
†Nara Institute of Science and Technology (NAIST), Japan ‡Tokyo Institute of Technology (Tokyo Tech), Japan
ReConFig2014 Session 4B (PE) 10:15-10:40, Dec 9, 2014
Abstract n flipSyrup: A framework for FPGA-based rapid prototyping
with abstract memory blocks and inter-FPGA interfaces
l Available at PyPI (https://pypi.python.org/pypi/flipsyrup)
2 ReConFig2014 Shinya T-Y. NAIST
Read Write
Syrup Memory
Syrup Memory
Syrup Channel
Syrup Channel
Read Write
User-logic Dat
a to
/from
O
ther
Cha
nnel
s
BRAMs w/o Capacity Limit
Contents
n Background l FPGA-based rapid prototyping
n New framework: flipSyrup l Design flow with flipSyrup
l Abstract objects for memory and inter-FPGA interface
l Automatic RTL conversion by static analysis
n Evaluation l Multicore on a single FPGA platform
l Manycore on a multi-FPGA platform
n Conclusion
ReConFig2014 Shinya T-Y. NAIST 3
Contents
n Background l FPGA-based rapid prototyping
n New framework: flipSyrup l Design flow with flipSyrup
l Abstract objects for memory and inter-FPGA interface
l Automatic RTL conversion by static analysis
n Evaluation l Multicore on a single FPGA platform
l Manycore on a multi-FPGA platform
n Conclusion
ReConFig2014 Shinya T-Y. NAIST 4
Background: Multicores to Manycores
5
TILERA TILE-Gx100
(100-core, MIPS) Intel Xeon Phi (54-core, x86)
Now: Multicore (2~8 cores per chip)
(Now and) Future: Many-core (32+ cores per chip)
Intel Corei7 (8-core, x86)
ARM Cortex-A9 (4-core, ARM)
ReConFig2014 Shinya T-Y. NAIST
FPGA-based Hardware Prototyping n A major way for evaluating a new architectural idea
l JFast simulation speed: x100~x1000 faster than SW simulators
l LVery difficult and complicated to develop the system
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Architectural Idea�
Problem Lack of abstractions for FPGA resources
Problems for Prototyping on FPGAs
7
Memory
Target Processor
Host Computer
ReConFig2014 Shinya T-Y. NAIST
Problems for Prototyping on FPGAs
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Memory
Target Processor
Host Computer
Inter-FPGA communication
Small on-chip memory Complex off-chip DRAM
Cycle-level accuracy
Capacity limitation of FPGAs
Partition for multiple FPGAs
Long synthesis time
ReConFig2014 Shinya T-Y. NAIST
Problems for Prototyping on FPGAs
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Memory
Target Processor
Host Computer
Inter-FPGA communication
Small on-chip memory Complex off-chip DRAM
Cycle-level accuracy
Capacity limitation of FPGAs
Partition for multiple FPGAs
Long synthesis time
Lack of Scalability Lack of Abstraction
ReConFig2014 Shinya T-Y. NAIST
Goal of This Research
n Abstraction for Memory System l For comprehensive management for entire memory systems of
on-chip SRAM and off-chip DRAM • Just combining off-chip memory can expand the memory capacity,
but also increase the system complexity
n Abstraction for Inter-FPGA Communication l For cycle-accuracy management on multiple FPGAs
• Just using Multiple FPGAs can expand the logic capacity, but it requires design partitioning and synchronization mechanism for cycle-accuracy
ReConFig2014 Shinya T-Y. NAIST 10
To provide efficient abstractions for simplifying development of FPGA-based prototypes
Contents
n Background l FPGA-based rapid prototyping
n New framework: flipSyrup l Design flow with flipSyrup
l Abstract objects for memory and inter-FPGA interface
l Automatic RTL conversion by static analysis
n Evaluation l Multicore on a single FPGA platform
l Manycore on a multi-FPGA platform
n Conclusion
ReConFig2014 Shinya T-Y. NAIST 11
flipSyrup n A framework for FPGA-based rapid prototyping with
abstract memory blocks and inter-FPGA interfaces l Syrup Memory: Ideal abstracted memory system for processor
RTL implementation to user design • For easy memory system implementation
l Syrup Channel: Ideal inter-FPGA communication for multi-FPGA prototyping to user design
• For easy design partitioning of simulated processor RTL
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Read Write
Syrup Memory
Syrup Memory
Syrup Channel
Syrup Channel
Read Write
User-logic Dat
a to
/from
O
ther
Cha
nnel
s
BRAMs w/o Capacity Limit ReConFig2014 Shinya T-Y. NAIST
Development Flow with flipSyrup
13 ReConFig2014 Shinya T-Y. NAIST
Control Signal
Insertion IP-core Packing
(RTL and
Setting file)
IP-core Integration
on EDK
Synthesis by EDA
Memory/Channel System
Synthesis
Simulation System Bit Files
Manual RTL Modification Framework Tool-chain
Vendor EDA Tool-chain
FPGA Memory Specifications
BRAM size = 128K DRAM width = 128
Pure RTL Design
Partitioned Design with
Abstract Objects
Instance Hierarchy Analysis
IP-cores for Simulation
Simulation on FPGAs
Simulation Result
FPGA-based Hardware Simulation
RTL Modeling with Abstract Objects n In advance, RAM objects and logic segments are
identified by using abstract objects of flipSyrup
ReConFig2014 Shinya T-Y. NAIST 14
Read Write
RAM
1-cycle RAMs w/o Capacity Limits
RAM RAM
Logic
Read Write
Sub-logic 0
Syrup Memory
Syrup Memory
Syrup Channel
Syrup Channel
Read Write
Virtual Connection
Region 0
Sub-logic N-1
Syrup Memory
Syrup Channel
Region N-1
= Entire Original Logic Replacing RAMs and I/Os with abstract objects
(a) Original Target Design (b) RTL Design with Abstract Objects
Complete Cycle-Accurate Simulation System n The tool-chain generates a complete IP-core for cycle-