A FPGA Design of AES Core Architectu re for Portable Hard DiskAIM: The main aim of the project is to design and implement “A FPGA Design of AES Core Architecture for Portable Hard Disk! A"S#$AC#: This paper describes a high effective AES core hardware architecture for implementing it to encrypt/decrypt the data in portable hard disk drive system that apply to effectively in the terms of speed, scale size and power consumption to comply with minimum speed of !bps "#S$%&'(& )e proposed the *+bits data path of two different AES ar chitectures design, $asic -terative AES, which reuses the same hardware for all the ten iterations and , .ne Stage Sub ipelined AES, with one stage of outer pipelining in the data blocks that both of them are purely *+bits data path architecture that different from the previous public paper& The implementation result on the targeted 0!A, the basic iterative AES encryption can offer the throughput of %&!bps at %'' 12z and one stage sub pipelined AES can offer the throughput to increase the efficiency of 3&+ !bps at 4* 12z clock speed& V.Mallikarjun a (Project manager) Mobile No: +91-8297578555. ISO: 9001- 2008 CERTIFIEDCOMPANYBranch!: "#$ra%a$ & Na'()r
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A FPGA Design of AES Core Architecture for Portable Hard Disk.doc
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8/14/2019 A FPGA Design of AES Core Architecture for Portable Hard Disk.doc