A Flexible SystemC Simulator for Multiprocessor Systems- on-Chip Luca Benini Davide Bertozzi Francesco Menichelli Mauro Olivieri DEIS - Università di Bologna DEIS - Università di Bologna DIE - Università di Roma “La Sapienza” DIE - Università di Roma “La Sapienza”
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A Flexible SystemC Simulator for Multiprocessor … Flexible SystemC Simulator for Multiprocessor Systems-on-Chip Luca Benini Davide Bertozzi Francesco Menichelli Mauro Olivieri DEIS
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A Flexible SystemC Simulatorfor Multiprocessor Systems-
- Multiple master bus (AMBA) SystemC implementation- RedHat Linux 7.2 and gcc 2.95.3- UClinux single processor 2.4.0 kernel- gcc 3.0.4 ARM cross-compiler
Why SystemC based design?- re-use of C/C++ code- modularity- standard interface between modules (SystemC)
Outlines of the AMBA bus
Figure: AHB and APB in a typical AMBA system.
AMBA (Advanced Microcontroller Bus Architecture) is an on-chip communicationstandard for high-performance embedded microcontroller supporting multiple unitsable to initiate read and write operations (bus masters)
- AHB: high performance, high clock frequency system modules- APB: low power peripherals
Full SystemC AMBA AHB bus implementation- clycle accurate bus transactions- internal multiplexers support up to seven bus masters (ampliable)- internal arbiter resolve bus contention through round robin policy
SystemC modules (masters and slaves)- complete SystemC description (lower abstraction level)- encapsulation of C/C++ code (higher abstraction level)
System architecture – Overview
Can coexistin the samesimulation
environment
AMBAAHB
multimasterunit
masterdevice #1
masterdevice #2
masterdevice #N
slavedevice #1
slavedevice #2
slavedevice #N
System architecture – Processing module
Processing module (master)- include CPU, cache memory and peripherals (C++ class derived fromopen source SWARM simulator)- a wrapper realizes the interface and synchronization layer betweenthe instruction simulator and the SystemC simulation framework
ARM7core
InterruptController
Timer
InstructionandData
Cache
UART
LocalBus
AMBAAHB I/F(SystemC)
C++ class
SystemC module (wrapper)
SystemCsignals
C++ classproperties
and methods
System architecture – AMBA AHB BUS modules
mast[ ]
hmaster
address[ ]
haddr
ctrl_sign
Address and control mux
N
N
mast[ ]
hmaster
hwdata[ ]
hwdataout
Write data mux
N
N
selector
hready
hsel[ ]
readdata[ ]
hrdata
N
N
Read data mux
hsel
[ ]
hadd
r
decoder
N
hre
q[ ]
ctr
l_si
gn
hre
ady
sel
ecto
r
hm
aste
r
hgr
ant[
]
NN
arbiter
ctrl_sign
haddrhwdataout
readdata
hmaster
ready
hsel
mastaddresshwdata
hrdatahgranthready
hreq
AHB I/F mastermodule
AHB I/F slavemodule
AHB mux - arbiter – decoder module
System architecture – Test configuration
ARM7 core
Interrupt Controller
Timer
Instruction and Data
Cache
UART
Local Bus
C++ class
SystemC module (wrapper)
AMBA MASTER #1
AMBAAHB I/F
AMBAAHB I/F
AMBA SLAVE #1
Memory
ARM7 core
Interrupt Controller
Timer
Instruction and Data
Cache
UART
Local Bus
C++ class
SystemC module (wrapper)
AMBA MASTER #2
AMBAAHB I/F
AMBAAHB I/F
AMBA SLAVE #2
Memory
Arbiter
Decoder
AMBA AHB
AMBAAMBA
AMBA AMBA
Shared memory dual processor – dual memory system
Modules declaration and connection//instantiation of the first processing modulearmsystem soc0("Arm_System0");
Two identicalmodules areinstantiated andconnected to theAMBA interface
Slave memorymodules:
Two identicalmodules areinstantiated andconnected to theAMBA interface
Simulator Test – Processing units and bus contentions
Screen capture of our dual processor simulator booting multipleparallel UClinux kernels. The two CPU work independently, contendingthe bus for memory access.
Collateral developing activities and tests:- Manual binding at compilation time of programfunctions to each processor- Dual processor startup and initialization code- Dual processor linker script
Simulation - AMBA burst access timings example
Through SystemC tracing capabilities, cycle accurate signal activitycan be visualized
Conclusion and Future Works
We have implemented a multiprocessor simulation environment inSystemC 1.0, containing an AMBA bus model, along with masters (CPUs)and slaves (memories) SystemC modules. The AMBA bus model itself iscomposed by several SystemC modules (arbiter, decoders,multiplexers). AMBA master devices (processors) are represented byinstruction-level models of cached ARM cores.
• Characteristics- Easily scalable through multiple instantiation of modules- Easily expandable through new modules implementation- Standard and well defined interface for modules interoperability
• Future works- Multiprocessor operating system, currently under development (RTEMS)- Expansion of the simulator with new master and slave modules