1 A A Dynamically Dynamically Reconfigurable Reconfigurable Platform Platform for for Channel Channel Coding Coding in Wireless in Wireless Communication Communication Norbert Norbert Wehn Wehn Timo Vogt, Matthias Alles Timo Vogt, Matthias Alles DFG SPP DFG SPP „Rekonfigurierbare Rekonfigurierbare Rechensysteme Rechensysteme“ September 2009, Karlsruhe September 2009, Karlsruhe PA LA MA WA Wide Area networks Metropolitan Area networks Local Area networks Personal Area networks any information, any where, any time, any one GSM GPRS UMTS EGDE HSDPA 3GPP-LTE WLAN WiMAX DVB DAB UWB Consumer application Time-to-Market NRE-costs Silicon-costs Low-Power Communication Centric World Communication Centric World
15
Embed
A Dynamically Reconfigurable Platform for Channel Coding in … · 2009-09-29 · 1 A Dynamically Reconfigurable Platform for Channel Coding in Wireless Communication Norbert Wehn
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
1
A A DynamicallyDynamically ReconfigurableReconfigurable PlatformPlatform forforChannelChannel CodingCoding in Wireless in Wireless CommunicationCommunication
Norbert Norbert WehnWehnTimo Vogt, Matthias AllesTimo Vogt, Matthias Alles
Mobile Phone Trends Mobile Phone Trends –– Channel DecodingChannel Decoding
gprs
wcdmacdma2000
td-scdma
td-scdma
lteumts hsdpaumts
gsm
lte-a
dmb-t
dab dvb-t
dvb-sdvb-h dvb-c
uwb
802.16e
802.11b
802.11n
802.11a
bluetooth
dvd
blueray
wimax
1
10
100
1000
10000
0.01 0.1 1 10 100 1000
bit rate [Mbps]
oper
atio
ns/b
it 0.1 GOPS 10 GOPScellular decodersbroadcast decodersconnectivity decoders
100 x Mops/Mw
Source: Kees van Berkel, DATE2009
ChallengesChallenges
Up to 60 GOPS digital radio processing within a power budget Up to 60 GOPS digital radio processing within a power budget of about < 500 of about < 500 mWmWFlexibility: multiFlexibility: multi-- and evolving standardsand evolving standards
What is the right architectural approach ?What is the right architectural approach ?Cost of flexibilityCost of flexibility versus versus Value of flexibilityValue of flexibilityHeterogeneous or homogeneous architecturesHeterogeneous or homogeneous architectures
Large diversity in operations and data typesLarge diversity in operations and data types
Inner ReceiverInner ReceiverTechniquesTechniques in in standards arestandards are differentdifferentStandard signal processing but complex Standard signal processing but complex algorithms algorithms FFT, correlator, filter, matrix calculationFFT, correlator, filter, matrix calculation……..((channel estimation, channel estimation, equalizationequalization, demodulation, , demodulation, synchronization..)synchronization..)SoftwareSoftware flexibilityflexibility brings large benefitbrings large benefit
4
Architectural ApproachArchitectural Approach
Programmable (reconfigurable) SIMD/Vector EnginesProgrammable (reconfigurable) SIMD/Vector EnginesSANDBLASTERSANDBLASTER ((SandbridgeSandbridge), MUSIC (Infineon), EVP (NXP), SODA ), MUSIC (Infineon), EVP (NXP), SODA (Arm/(Arm/UnivUniv. Michigan), ADRES (IMEC), . Michigan), ADRES (IMEC), MONTIUMMONTIUM ((TwenteTwente))……..
NonNon--standard signal standard signal processing algorithmsprocessing algorithmsNonNon--standard arithmeticstandard arithmeticNonNon--standard standard wordword--widthwidth
Flexibility required Flexibility required but limited value of highbut limited value of high--level level softwaresoftwareSIMD/Vector engines of inner receiver not suitedSIMD/Vector engines of inner receiver not suited
Exploit programmabilityExploit programmabilityInstruction level flexibilityInstruction level flexibilityDecoding algorithms e.g. LogDecoding algorithms e.g. Log--MAP, MAP, ViterbiViterbi
Exploit hardware Exploit hardware reconfigurability at runreconfigurability at run--timetimeEfficient data Efficient data management/shufflingmanagement/shufflingCode structureCode structureFast context switching and multi context Fast context switching and multi context instructionsinstructions
DesignDesign--time and runtime and run--time configurabilitytime configurability
6
Design Time Design Time ConfigurationConfiguration
74391
88966
106762
109320
Area[mm2]
SynthesisStandard cells
(65nm)
450
415
400
400
Frequency[MHz]
FPGA (Xilinx xc4vlx80-12)
1354207bTC
1175494bTC, dbTC (dbTC only 8 states)
1126683bTC, dbTC, CC (H VA)
1097012bTC, dbTC, CC (H/S VA)
Frequency[MHz]
SlicesFunctionality
VariousVarious ASIP ASIP instancesinstances withwith different different functionalityfunctionality withoutwithout memoriesmemories
OnlyOnly reusereuse of of memoriesmemories and and pipelinepipeline stagesstagesAdditional Additional logiclogic necessarynecessaryTwoTwo reconfigurablereconfigurable barrelbarrel shiftersshifters
LDPC IP LDPC IP CoreCore: : 0.10 mm0.10 mm22 logiclogic + + 0.20mm0.20mm²² memorymemory = 0.30mm= 0.30mm²²
LDPC LDPC ThroughputThroughput: : up to 257up to 257 Mbit/sMbit/s @ 400 MHz @10@ 400 MHz @10--20 20 iterationsiterations
9
65nm low power technology
Die size \wo interface 0,69 mm2
385MHz
~100 mW
4* S
D m
em20
48 x
82
x SM
M12
8 x
96
2 * CV mem4096 x 12
IL m
em61
44 x
13
PRO
G m
em51
2 x
24
HD mem +LIFO
ASIP ASIP Layout (CC/TC)Layout (CC/TC)
DuoDuo--binary Turbobinary Turbo--Code Assembler ProgramCode Assembler Program
……setPCFsetPCF AP(1) SOM(1) INT(1) ESF(1) ; set control flagsAP(1) SOM(1) INT(1) ESF(1) ; set control flagsstst 3,CVA3,CVA ; ; \\ set memory addressset memory addressstst 0,RDA0,RDA ; / pointer; / pointerstst (SMMA=66),SMR(SMMA=66),SMR ; load PII state; load PII statestst SMR,(SMMA=0)SMR,(SMMA=0) ; copy it to state ; copy it to state metrmetr. . MemMem..RPT RPT --> R1> R1 ; single instr. loop:; single instr. loop:
fwdrecfwdrec (CVA)+=4 #CVs=1>>,(SMMA+=1)(CVA)+=4 #CVs=1>>,(SMMA+=1) ; forward recursion; forward recursionfwdrecfwdrec (CVA)+=4 #CVs=1>>,(SMMA+=3)(CVA)+=4 #CVs=1>>,(SMMA+=3) ; inherently store end state; inherently store end state
ASIP C++ software ASIP C++ software simulation (LISATek@CoWare)simulation (LISATek@CoWare)TC PerformanceTC Performance: 75 bit decoding per second on standard PC: 75 bit decoding per second on standard PCUMTS TurboUMTS Turbo--decoding 6100 bit decoding 6100 bit blocklengthblocklength
100.00100.00 Monte Carlo simulation runs necessary / SNR pointMonte Carlo simulation runs necessary / SNR point~ 37 hours per SNR point on standard PC ~ 37 hours per SNR point on standard PC UMTS standard: 10 cases specified, per case 10 SNR points necessUMTS standard: 10 cases specified, per case 10 SNR points necessaryary
Validation/Simulation ProblemValidation/Simulation Problem
CompleteComplete FEC FEC communication chaincommunication chain on on XilinxXilinx ML507 ML507 platformplatform
[1] M. Alles, T. [1] M. Alles, T. LehnigLehnig--EmdenEmden, C. Brehm, and N. , C. Brehm, and N. WehnWehn. A Rapid . A Rapid PrototypingPrototypingEnvironmentEnvironment forfor ASIP Validation in Wireless Systems. In ASIP Validation in Wireless Systems. In ProceedingsProceedings of of EDAEDAWorkshop 2009Workshop 2009, , pagespages 4343––48. Dresden, Germany, May 2009.48. Dresden, Germany, May 2009.
[2] T. Vogt and N. [2] T. Vogt and N. WehnWehn. A . A ReconfigurableReconfigurable ASIP ASIP forfor Convolutional and TurboConvolutional and TurboDecodingDecoding in a SDR in a SDR EnvironmentEnvironment. . IEEE IEEE TransactionsTransactions on on VeryVery Large Large ScaleScaleIntegration SystemsIntegration Systems, , pagespages 13091309––1320, 1320, OctoberOctober 2008.2008.
[3] M. Alles, T. Vogt, and N. [3] M. Alles, T. Vogt, and N. WehnWehn. . FlexiChaPFlexiChaP: A : A ReconfigurableReconfigurable ASIP ASIP forfor Convolutional,Convolutional,Turbo, and LDPC Code Turbo, and LDPC Code DecodingDecoding. In . In ProcProc. . 5th International Symposium5th International Symposiumon Turbo Codes and on Turbo Codes and RelatedRelated TopicsTopics, , pagespages 8484––89. Lausanne, 89. Lausanne, SwitzerlandSwitzerland,,September 2008.September 2008.
[4] T. Vogt and N. [4] T. Vogt and N. WehnWehn. A . A ReconfigurableReconfigurable ApplicationApplication SpecificSpecific InstructionInstruction SetSetProcessorProcessor forfor Convolutional and Turbo Convolutional and Turbo DecodingDecoding in a SDR in a SDR EnvironmentEnvironment. In. InProcProc. . Design, Automation and Test in Europe (DATE Design, Automation and Test in Europe (DATE ’’08), 08), pagespages 3838––43. Munich,43. Munich,Germany, Germany, MarchMarch 2008.2008.
[5] N. [5] N. WehnWehn. An . An OuterOuter Modem ASIP Modem ASIP forfor Software Software DefinedDefined Radio. In Radio. In 8th International 8th International Forum on Forum on EmbeddedEmbedded MPSoCMPSoC (MPSoC(MPSoC’’0808), Aachen, ), Aachen, JuneJune, 2008, 2008
15
PublicationsPublications
[6] N. [6] N. WehnWehn. . Flexibility/ReconfigurabiltyFlexibility/Reconfigurabilty TradeTrade--OffsOffs in SDR in SDR ArchitecturesArchitectures. In . In FridayFridayWorkshopnWorkshopn ReconfigurableReconfigurable ComputingComputing, , Design, Automation and Test in Europe Design, Automation and Test in Europe (DATE (DATE ’’08), 08), Munich, Germany, Munich, Germany, MarchMarch 2008.2008.
[7] T. Vogt and N. [7] T. Vogt and N. WehnWehn. A . A ReconfigurableReconfigurable ApplicationApplication SpecificSpecific InstructionInstruction SetSetProcessorProcessor forfor ViterbiViterbi and Logand Log--MAP MAP DecodingDecoding. In . In ProcProc. . IEEE Workshop onIEEE Workshop onSignal Signal ProcessingProcessing (SIPS(SIPS’’06),06), pagespages 142142––147. 147. BanffBanff, Canada, , Canada, OctoberOctober 2006.2006.
[8] T. Vogt, C. [8] T. Vogt, C. NeebNeeb, and N. , and N. WehnWehn. A . A ReconfigurableReconfigurable OuterOuter Modem Modem PlatformPlatform forforFuture Future CommunciationsCommunciations Systems. In Systems. In DagstuhlDagstuhl Seminar, Seminar, DynamicallyDynamically ReconfigurableReconfigurableArchitecturesArchitectures, , DagstuhlDagstuhl Seminar Seminar ProceedingsProceedings 0614106141. . DagstuhlDagstuhl, Germany,, Germany,April 2006.April 2006.
[9] T. Vogt, C. [9] T. Vogt, C. NeebNeeb, and N. , and N. WehnWehn. A . A ReconfigurableReconfigurable MultiMulti--ProcessorProcessor PlatformPlatform forforConvolutional and Turbo Convolutional and Turbo DecodingDecoding. In . In ReconfigurableReconfigurable CommunicationCommunication--centriccentricSoCsSoCs ((ReCoSoCReCoSoC).). Montpellier, France, 2006.Montpellier, France, 2006.
Thank you for attention!Thank you for attention!
For more information please visitFor more information please visit