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A Dual-Loop Injection-Locked PLL with All-Digital PVT
Calibration SystemWei Deng, Ahmed Musa, Teerachot Siriburanon,
Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa
Tokyo Institute of Technology, Japan
Matsuzawa& Okada Lab.
Matsuzawa Lab.Tokyo Institute of TechnologyMatsuzawa
& Okada Lab.Matsuzawa Lab.Tokyo Institute of Technology
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Outline• Introduction• Issues of Conventional Injection-
Locked PLLs (IL-PLLs)• Proposed Dual-loop IL-PLL
• PVT Tracking Capability by Replica Loop• Low Jitter by Main Loop
• Measurement Results• Conclusion
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Introduction• Why High Performance PLL
– Clock generation/distribution• Key Specifications for SoC Clocking
– Small area– Low power consumption– Low jitter– Scalable with technology advancement– Insensitive over environment variations
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Injection-locking Technique
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Injection-locked PLL
• Reference is injected into VCO through the pulse generator
[J. Lee, et al., JSSC 2009]
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Issue of Injection-locked PLL
Conventional PLL
Conventional IL-PLL
Cannot track frequency drift
Can track frequency drift
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Proposed Dual-loop Architecture
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Proposed Dual-loop IL-PLL
FCW: Frequency Control Word
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Calibration Algorithm
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Phase I: Coarse Freq. Calibration
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Phase II: Freq. Offset Calibration
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Phase III: Maintaining Operation
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Injection-locked Ring Oscillator
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Chip Microphotograph
Synthesized Logics
DAC DACMainVCO
ReplicaVCO
Pulse Generator
80 m
m
270 mm
Pulse Generator (Dummy)
• Fabricated in CMOS 65nm technology
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Phase Noise
Free Run
Locked
Offset Frequency [Hz]
Phas
e N
oise
[dB
c/H
z]
10k 100k 1M 10M
-120
-80
-40
0
Ref.: 300MHz (40MHz-300MHz) Freq.: 1.2GHz (0.5-1.6GHz)Integrated jitter: 0.7ps (10kHz-40MHz) Pdc: 0.97mW (1.2GHz)
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Measured Spectrum
Free-running Locked
1.08GHz 1.32GHz 1.199GHz 1.201GHz
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Spurious at 1.2GHz (Worst Case)
N=24 N=12
N=6 N=4
Spurious: -31 dBc Spurious: -38 dBc
Spurious: -43 dBc Spurious: -49 dBc
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Measured Jitter over Temp.peak-to-peak jitterRMS jitter
Mea
sure
d Pe
ak-to
-Pea
k an
d R
MS
Jitte
r [ps
]
50
40
30
20
10
Temperature [oC]20 40 60 80
Free-running freq. drifts tothe border of locking range
peak-to-peak jitterRMS jitter
Mea
sure
d Pe
ak-to
-Pea
k an
d R
MS
Jitte
r [ps
]
50
40
30
20
10
Temperature [oC]20 40 60 80
Single loop Dual loop
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Performance Summary
This work [1] [2] [5]
IL-PLL DMDLL DPLL MDLL IL-PLL
Freq. [GHz] 1.2(0.5-1.6)
1.5(0.8-1.8)
1.5(0.8-1.8) 1.6 0.216
Ref. [MHz] 300(40-300) 375 375 50 27
Power [mW] 0.97 0.89 1.35 12 6.9Area [mm2] 0.022 0.25 0.25 0.058 0.03
Integ. Jitter [ps] 0.7 0.4 3.2 0.68 2.4Jitter RMS/PP
[ps]1.81/19.410M hits
0.92/9.25M hits
4.2/335M hits
0.93/11.130M hits N.A.
FOM [dB] -243 -248.46 -228.59 -233.76 -225CMOS Tech. 65nm 130nm 130nm 130nm 55nm
[1] A. Elshazly, et al., ISSCC 2012 [2] B. Helal, et al., JSSC 2008 [5] C. Liang, et al., ISSCC 2011
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Conclusion• Dual-loop IL-PLL is suited for SoC
clocking• Low jitter
• Low power consumption
• Small chip area
• Scalability with process
• Insensitivity over PVT
Injectionlocking
All-Digital FLLDual-loop
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AcknowledgementThis work was partially supported by SCOPE, STARC, NEDO, MIC, MEXT, Canon Foundation, Huawei, and VDEC in collaboration with Cadence Design Systems, Inc., and Agilent Technologies Japan, Ltd.
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Intermit.Calib. at Phase III (1/2)
1 2 1 2 1 2
10us 990us
Step 1: Enable calibration & Replica VCOStep 2: Disable calibration & Replica VCO
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Intermit. Calib. at Phase III (2/2)Step 1: Enable calibration & Replica VCOStep 2: Disable calibration & Replica VCO
W/O Intermittent 1.6mW
W/ Intermittent 1mW
1 2 1 2 1 2
10us 990us
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Behavior of Non-ideal InjectionWhen f0 ≠ N· fref
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Spur LevelLocked state: flocked=N · fref
Free-running: ffree-running=(1+a) · flocked
Spur power = -20log10((ffree-running- flocked)/(2 ·fref))= -20log10(a ·N/2)
e.g. N=20, a=0.001 -60dBc spur[R.B. Staszewski, et al., All-Digital Frequency Synthesizer in Deep-Submicron CMOS, Wiley, 2006]
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FOM over Area
[1] A. Elshazly, et al., ISSCC 2012 [2] B. Helal, et al., JSSC 2008 [3] J. Lee, et al., JSSC 2009[4] G. Xiang, et al., ISSCC 2009 [5] C. Liang, et al., ISSCC 2011
VLSI 2010SS-PLL
ISSCC 2009SS-PLL[4]
ISSCC 2011MDLL
ISSCC 2011SS-IL-PLL[5]
ISSCC 2002IL-PLL
JSSC 2008MDLL[2]
ISSCC 2012IL-AD-PLL
ISSCC 2012DPLL[1]
ISSCC 2012DMDLL[1] ISSCC 2009
IL-PLL[3]
JSSC 2009IL-PLL
JSSC 2009IL-PLL+DDLL
This WorkIL-PLL
Area [mm2]
FOM
[dB
]
-220
-230
-240
-250
0.01 0.1 1
FOM=, where is the integrating jitter
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PVT Tracking Capability
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IL-PLL with Dual VCOs
Frequency offset between main & replica oscillator
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[D. Park, et al., ISSCC 2012]
Injection Timing (Conventional)
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Injection Timing (Proposed)
• Injection timing calibration is obliterated
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Proposed Concept• Dual-loop Topology
– PVT tracking capability– Compensate for main & replica VCO
frequency offset– No calibration for injection timing required
• Reduce area & power overhead• All-digital Frequency-locked Loop
– Compact chip area– Low power consumption– Scalable with process advancement