a DSP Microcomputer Family ADSP-2106x SHARC ADSP-21060 ...

REV. B

Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

a ADSP-2106x SHARC®

DSP Microcomputer FamilyADSP-21060/ADSP-21060L

IEEE JTAG Standard 1149.1 Test Access Port and

On-Chip Emulation

240-Lead Thermally Enhanced PQFP Package

32-Bit Single-Precision and 40-Bit Extended-Precision

IEEE Floating-Point Data Formats or 32-Bit Fixed-

Point Data Format

Parallel Computations

Single-Cycle Multiply and ALU Operations in Parallel

with Dual Memory Read/Writes and Instruction Fetch

Multiply with Add and Subtract for Accelerated FFT

Butterfly Computation

4 Mbit On-Chip SRAM

Dual-Ported for Independent Access by Core Processor

and DMA

Off-Chip Memory Interfacing

4 Gigawords Addressable

Programmable Wait State Generation, Page-Mode

DRAM Support

SHARC is a registered trademark of Analog Devices, Inc.

SERIAL PORTS(2)

LINK PORTS(6)

4

6

6

36

IOPREGISTERS

(MEMORY MAPPED)

CONTROL,STATUS &

DATA BUFFERS

I/O PROCESSOR

TIMER INSTRUCTIONCACHE

32 x 48-BIT

ADDR DATA DATA

DATA

ADDR

ADDR DATA ADDR

TWO INDEPENDENTDUAL-PORTED BLOCKS

PROCESSOR PORT I/O PORT

BLO

CK

0

BLO

CK

1 JTAG

TEST &EMULATION

7

HOST PORT

ADDR BUSMUX

IOA17

IOD48

MULTIPROCESSORINTERFACE

DUAL-PORTED SRAM

EXTERNALPORT

DATA BUSMUX

48

3224PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

BUSCONNECT

(PX)

DATAREGISTER

FILE16 x 40-BIT BARREL

SHIFTER ALUMULTIPLIER

DAG18 x 4 x 32

32

48

40/32

CORE PROCESSOR

DMACONTROLLER

PROGRAMSEQUENCER

DAG28 x 4 x 24

Figure 1. Block Diagram

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 1998

SUMMARY

High Performance Signal Processor for Communica-

tions, Graphics, and Imaging Applications

Super Harvard Architecture

Four Independent Buses for Dual Data Fetch,

Instruction Fetch, and Nonintrusive I/O

32-Bit IEEE Floating-Point Computation Units—

Multiplier, ALU, and Shifter

Dual-Ported On-Chip SRAM and Integrated I/O

Peripherals—A Complete System-On-A-Chip

Integrated Multiprocessing Features

KEY FEATURES

40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction

Execution

120 MFLOPS Peak, 80 MFLOPS Sustained Performance

Dual Data Address Generators with Modulo and Bit-

Reverse Addressing

Efficient Program Sequencing with Zero-Overhead

Looping: Single-Cycle Loop Setup

–2–

ADSP-21060/ADSP-21060L

REV. B

DMA Controller

10 DMA Channels for Transfers Between ADSP-2106x

Internal Memory and External Memory, External

Peripherals, Host Processor, Serial Ports, or Link

Ports

Background DMA Transfers at 40 MHz, in Parallel with

Full-Speed Processor Execution

Host Processor Interface to 16- and 32-Bit Microprocessors

Host Can Directly Read/Write ADSP-2106x Internal

Memory

Multiprocessing

Glueless Connection for Scalable DSP Multiprocessing

Architecture

Distributed On-Chip Bus Arbitration for Parallel Bus

Connect of Up to Six ADSP-2106xs Plus Host

Six Link Ports for Point-to-Point Connectivity and Array

Multiprocessing

240 Mbytes/s Transfer Rate Over Parallel Bus

240 Mbytes/s Transfer Rate Over Link Ports

Serial Ports

Two 40 Mbit/s Synchronous Serial Ports with

Companding Hardware

Independent Transmit and Receive Functions

TABLE OF CONTENTSGENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 3ADSP-21000 FAMILY CORE ARCHITECTURE . . . . . . . 4ADSP-21060/ADSP-21060L FEATURES . . . . . . . . . . . . . . 4DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . 7PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 8TARGET BOARD CONNECTOR FOR EZ-ICE®

PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11RECOMMENDED OPERATING CONDITIONS (5 V) . 13ELECTRICAL CHARACTERISTICS (5 V) . . . . . . . . . . . 13POWER DISSIPATION ADSP-21060 (5 V) . . . . . . . . . . . . 14RECOMMENDED OPERATING CONDITIONS (3.3 V) 15ELECTRICAL CHARACTERISTICS (3.3 V) . . . . . . . . . . 15POWER DISSIPATION ADSP-21060L (3.3 V) . . . . . . . . . 16ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 17TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 17

Memory Read—Bus Master . . . . . . . . . . . . . . . . . . . . . . . 20Memory Write—Bus Master . . . . . . . . . . . . . . . . . . . . . . 21Synchronous Read/Write—Bus Master . . . . . . . . . . . . . . 22Synchronous Read/Write—Bus Slave . . . . . . . . . . . . . . . . 24Multiprocessor Bus Request and Host Bus Request . . . . . 25Asynchronous Read/Write—Host to ADSP-2106x . . . . . . 27Three-State Timing—Bus Master, Bus Slave,

HBR, SBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Link Ports: 1 × CLK Speed Operation . . . . . . . . . . . . . . 32Link Ports: 2 × CLK Speed Operation . . . . . . . . . . . . . . 33Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35JTAG Test Access Port and Emulation . . . . . . . . . . . . . . . 38

OUTPUT DRIVE CURRENTS . . . . . . . . . . . . . . . . . . . . . 39POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 39TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 42240-LEAD METRIC PQFP PIN CONFIGURATIONS . . 43PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 44ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

FIGURESFigure 1. ADSP-21060/ADSP-21060L Block Diagram . . . . 1Figure 2. ADSP-2106x System . . . . . . . . . . . . . . . . . . . . . . . 4Figure 3. Shared Memory Multiprocessing System . . . . . . . . 6Figure 4. ADSP-21060/ADSP-21060L Memory Map . . . . . 7Figure 5. Target Board Connector For ADSP-2106x

EZ-ICE Emulator (Jumpers in Place) . . . . . . . . . . . . . . . 11Figure 6. JTAG Scan Path Connections for Multiple

ADSP-2106x Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7. JTAG Clocktree for Multiple ADSP-2106xSystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 8. Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 9. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 10. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 11. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 12. Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 13. Memory Read—Bus Master . . . . . . . . . . . . . . . . 20Figure 14. Memory Write—Bus Master . . . . . . . . . . . . . . . 21Figure 15. Synchronous Read/Write—Bus Master . . . . . . . 23Figure 16. Synchronous Read/Write—Bus Slave . . . . . . . . . 24Figure 17. Multiprocessor Bus Request and Host Bus

Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 18a. Synchronous REDY Timing . . . . . . . . . . . . . . 27Figure 18b. Asynchronous Read/Write—Host to

ADSP-2106x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Figure 19a. Three-State Timing (Bus Transition Cycle,

SBTS Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 19b. Three-State Timing (Host Transition Cycle) . . 29Figure 20. DMA Handshake Timing . . . . . . . . . . . . . . . . . 31Figure 21. Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 22. Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Figure 23. External Late Frame Sync . . . . . . . . . . . . . . . . . 37Figure 24. IEEE 11499.1 JTAG Test Access Port . . . . . . . 38Figure 25. Output Enable/Disable . . . . . . . . . . . . . . . . . . . 40Figure 26. Equivalent Device Loading for AC Measurements

(Includes All Fixtures) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Figure 27. Voltage Reference Levels for AC Measurements

(Except Output Enable/Disable) . . . . . . . . . . . . . . . . . . . 40Figure 28. ADSP-2106x Typical Drive Currents

(VDD = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Figure 29. Typical Output Rise Time (10%–90% VDD)

vs. Load Capacitance (VDD = 5 V) . . . . . . . . . . . . . . . . . . . 41Figure 30. Typical Output Rise Time (0.8 V–2.0 V)

vs. Load Capacitance (VDD = 5 V) . . . . . . . . . . . . . . . . . . . 41Figure 31. Typical Output Delay or Hold vs. Load Capacitance

(at Maximum Case Temperature) (VDD = 5 V) . . . . . . . . . 41Figure 32. ADSP-2106x Typical Drive Currents

(VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Figure 33. Typical Output Rise Time (10%–90% VDD)

vs. Load Capacitance (VDD = 3.3 V) . . . . . . . . . . . . . . . . . 41Figure 34. Typical Output Rise Time (0.8 V–2.0 V) vs. Load

Capacitance (VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 35. Typical Output Delay or Hold vs. Load Capacitance

(at Maximum Case Temperature) (VDD = 3.3 V) . . . . . . . . 42

EZ-ICE is a registered trademark of Analog Devices, Inc.


–3–REV. B

GENERAL DESCRIPTIONThe ADSP-21060 SHARC—Super Harvard Architecture Com-puter—is a signal processing microcomputer that offers newcapabilities and levels of performance. The ADSP-2106xSHARCs are 32-bit processors optimized for high performanceDSP applications. The ADSP-2106x builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding adual-ported on-chip SRAM and integrated I/O peripherals sup-ported by a dedicated I/O bus.

Fabricated in a high speed, low power CMOS process, theADSP-2106x has a 25 ns instruction cycle time and operatesat 40 MIPS. With its on-chip instruction cache, the processorcan execute every instruction in a single cycle. Table I showsperformance benchmarks for the ADSP-2106x.

The ADSP-2106x SHARC represents a new standard of inte-gration for signal computers, combining a high performancefloating-point DSP core with integrated, on-chip system featuresincluding a 4 Mbit SRAM memory host processor interface,DMA controller, serial ports, and link port and parallel busconnectivity for glueless DSP multiprocessing.

Figure 1 shows a block diagram of the ADSP-2106x, illustratingthe following architectural features:

Computation Units (ALU, Multiplier and Shifter) with a Shared Data Register File

Data Address Generators (DAG1, DAG2)Program Sequencer with Instruction CacheInterval TimerOn-Chip SRAMExternal Port for Interfacing to Off-Chip Memory and

PeripheralsHost Port and Multiprocessor InterfaceDMA ControllerSerial Ports and Link PortsJTAG Test Access Port

Figure 2 shows a typical single-processor system. A multi-processing system is shown in Figure 3.

Table I. ADSP-21060/ADSP-21060L Benchmarks (@ 40 MHz)

1024-Pt. Complex FFT 0.46 ms 18,221 cycles(Radix 4, with Digit Reverse)

FIR Filter (per Tap) 25 ns 1 cycleIIR Filter (per Biquad) 100 ns 4 cyclesDivide (y/x) 150 ns 6 cyclesInverse Square Root (1/√x) 225 ns 9 cyclesDMA Transfer Rate 240 Mbytes/s

S

–4–


REV. B

ADSP-21000 FAMILY CORE ARCHITECTUREThe ADSP-2106x includes the following architectural featuresof the ADSP-21000 family core. The ADSP-21060 is code- andfunction-compatible with the ADSP-21061 and ADSP-21062.

Independent, Parallel Computation UnitsThe arithmetic/logic unit (ALU), multiplier and shifter all per-form single-cycle instructions. The three units are arranged inparallel, maximizing computational throughput. Single multi-function instructions execute parallel ALU and multiplier opera-tions. These computation units support IEEE 32-bit single-precision floating-point, extended precision 40-bit floating-point, and 32-bit fixed-point data formats.

3

4

RESET JTAG

7

ADSP-2106xBMS

ADDR31-0

DATA47-0

CO

NT

RO

L

AD

DR

ES

S

DA

TA

CS

ADDR

DATA

BOOTEPROM

(OPTIONAL)

ADDR

ACKCS

MEMORYAND

PERIPHERALS(OPTIONAL)

OEWE

DATA

DMA DEVICE(OPTIONAL)

DATA

ADDR

DATA

HOSTPROCESSORINTERFACE(OPTIONAL)

1x CLOCK

LINKDEVICES

(6 MAXIMUM)(OPTIONAL)

SERIALDEVICE

(OPTIONAL)

CSHBRHBG

REDY

RDWR

PAGE

ADRCLK

ACKMS3-0

SBTSSW

BR1-6

CPA

DMAR1-2DMAG1-2

SERIALDEVICE

(OPTIONAL)

CLKINEBOOTLBOOT

IRQ2-0FLAG3-0TIMEXP

LxCLKLxACKLxDAT 3-0

TCLK0RCLK0TFS0RSF0DT0DR0

TCLK1RCLK1TFS1RFS1DT1DR1

RPBAID2-0

Figure 2. ADSP-2106x System

Data Register FileA general purpose data register file is used for transferring databetween the computation units and the data buses, and forstoring intermediate results. This 10-port, 32-register (16 pri-mary, 16 secondary) register file, combined with the ADSP-21000 Harvard architecture, allows unconstrained data flowbetween computation units and internal memory.

Single-Cycle Fetch of Instruction and Two OperandsThe ADSP-2106x features an enhanced Harvard architecture inwhich the data memory (DM) bus transfers data and the pro-gram memory (PM) bus transfers both instructions and data(see Figure 1). With its separate program and data memorybuses and on-chip instruction cache, the processor can simulta-neously fetch two operands and an instruction (from the cache),all in a single cycle.

Instruction CacheThe ADSP-2106x includes an on-chip instruction cache thatenables three-bus operation for fetching an instruction and twodata values. The cache is selective—only the instructions whosefetches conflict with PM bus data accesses are cached. Thisallows full-speed execution of core, looped operations such asdigital filter multiply-accumulates and FFT butterfly processing.

Data Address Generators with Hardware Circular BuffersThe ADSP-2106x’s two data address generators (DAGs) imple-ment circular data buffers in hardware. Circular buffers allowefficient programming of delay lines and other data structuresrequired in digital signal processing, and are commonly used indigital filters and Fourier transforms. The two DAGs of theADSP-2106x contain sufficient registers to allow the creation ofup to 32 circular buffers (16 primary register sets, 16 second-ary). The DAGs automatically handle address pointer wrap-around, reducing overhead, increasing performance, andsimplifying implementation. Circular buffers can start and endat any memory location.

Flexible Instruction SetThe 48-bit instruction word accommodates a variety of paralleloperations, for concise programming. For example, the ADSP-2106x can conditionally execute a multiply, an add, a subtractand a branch, all in a single instruction.

ADSP-21060/ADSP-21060L FEATURESAugmenting the ADSP-21000 family core, the ADSP-21060adds the following architectural features:

Dual-Ported On-Chip MemoryThe ADSP-21060 contains four megabits of on-chip SRAM,organized as two blocks of 2 Mbits each, which can be config-ured for different combinations of code and data storage.Each memory block is dual-ported for single-cycle, independentaccesses by the core processor and I/O processor or DMA con-troller. The dual-ported memory and separate on-chip busesallow two data transfers from the core and one from I/O, all in asingle cycle.

On the ADSP-21060, the memory can be configured as a maxi-mum of 128K words of 32-bit data, 256K words of 16-bit data,80K words of 48-bit instructions (or 40-bit data), or combina-tions of different word sizes up to four megabits. All of thememory can be accessed as 16-bit, 32-bit, or 48-bit words.

A 16-bit floating-point storage format is supported that effec-tively doubles the amount of data that may be stored on-chip.Conversion between the 32-bit floating-point and 16-bit floating-point formats is done in a single instruction.

While each memory block can store combinations of code anddata, accesses are most efficient when one block stores data,using the DM bus for transfers, and the other block storesinstructions and data, using the PM bus for transfers. Using theDM bus and PM bus in this way, with one dedicated to eachmemory block, assures single-cycle execution with two datatransfers. In this case, the instruction must be available in thecache. Single-cycle execution is also maintained when one of thedata operands is transferred to or from off-chip, via the ADSP-2106x’s external port.


–5–REV. B

Serial PortsThe ADSP-2106x features two synchronous serial ports thatprovide an inexpensive interface to a wide variety of digital andmixed-signal peripheral devices. The serial ports can operate atthe full clock rate of the processor, providing each with a maxi-mum data rate of 40 Mbit/s. Independent transmit and receivefunctions provide greater flexibility for serial communications.Serial port data can be automatically transferred to and fromon-chip memory via DMA. Each of the serial ports offers TDMmultichannel mode.

The serial ports can operate with little-endian or big-endiantransmission formats, with word lengths selectable from 3 bits to32 bits. They offer selectable synchronization and transmitmodes as well as optional µ-law or A-law companding. Serialport clocks and frame syncs can be internally or externallygenerated.

MultiprocessingThe ADSP-2106x offers powerful features tailored to multi-processing DSP systems. The unified address space (seeFigure 4) allows direct interprocessor accesses of each ADSP-2106x’s internal memory. Distributed bus arbitration logic isincluded on-chip for simple, glueless connection of systemscontaining up to six ADSP-2106xs and a host processor. Masterprocessor changeover incurs only one cycle of overhead. Busarbitration is selectable as either fixed or rotating priority. Bus lockallows indivisible read-modify-write sequences for semaphores. Avector interrupt is provided for interprocessor commands. Maxi-mum throughput for interprocessor data transfer is 240 Mbytes/sover the link ports or external port. Broadcast writes allow simulta-neous transmission of data to all ADSP-2106xs and can be usedto implement reflective semaphores.

Link PortsThe ADSP-2106x features six 4-bit link ports that provide addi-tional I/O capabilities. The link ports can be clocked twice percycle, allowing each to transfer eight bits per cycle. Link portI/O is especially useful for point-to-point interprocessor commu-nication in multiprocessing systems.

The link ports can operate independently and simultaneously,with a maximum data throughput of 240 Mbytes/s. Link portdata is packed into 32- or 48-bit words, and can be directly readby the core processor or DMA-transferred to on-chip memory.

Each link port has its own double-buffered input and outputregisters. Clock/acknowledge handshaking controls link porttransfers. Transfers are programmable as either transmit orreceive.

Program BootingThe internal memory of the ADSP-2106x can be booted atsystem power-up from either an 8-bit EPROM, a host proces-sor, or through one of the link ports. Selection of the bootsource is controlled by the BMS (Boot Memory Select),EBOOT (EPROM Boot), and LBOOT (Link/Host Boot) pins.32-bit and 16-bit host processors can be used for booting.

Off-Chip Memory and Peripherals InterfaceThe ADSP-2106x’s external port provides the processor’s inter-face to off-chip memory and peripherals. The 4-gigaword off-chip address space is included in the ADSP-2106x’s unifiedaddress space. The separate on-chip buses—for PM addresses,PM data, DM addresses, DM data, I/O addresses, and I/Odata—are multiplexed at the external port to create an externalsystem bus with a single 32-bit address bus and a single 48-bit(or 32-bit) data bus.

Addressing of external memory devices is facilitated by on-chipdecoding of high-order address lines to generate memory bankselect signals. Separate control lines are also generated for sim-plified addressing of page-mode DRAM. The ADSP-2106xprovides programmable memory wait states and externalmemory acknowledge controls to allow interfacing to DRAMand peripherals with variable access, hold, and disable timerequirements.

Host Processor InterfaceThe ADSP-2106x’s host interface allows easy connection tostandard microprocessor buses, both 16-bit and 32-bit, withlittle additional hardware required. Asynchronous transfers atspeeds up to the full clock rate of the processor are supported.The host interface is accessed through the ADSP-2106x’s exter-nal port and is memory-mapped into the unified address space.Four channels of DMA are available for the host interface; codeand data transfers are accomplished with low software overhead.

The host processor requests the ADSP-2106x’s external buswith the host bus request (HBR), host bus grant (HBG), andready (REDY) signals. The host can directly read and write theinternal memory of the ADSP-2106x, and can access the DMAchannel setup and mailbox registers. Vector interrupt support isprovided for efficient execution of host commands.

DMA ControllerThe ADSP-2106x’s on-chip DMA controller allows zero-overhead data transfers without processor intervention. TheDMA controller operates independently and invisibly to theprocessor core, allowing DMA operations to occur while thecore is simultaneously executing its program instructions.

DMA transfers can occur between the ADSP-2106x’s internalmemory and either external memory, external peripherals or ahost processor. DMA transfers can also occur between theADSP-2106x’s internal memory and its serial ports or linkports. DMA transfers between external memory and externalperipheral devices are another option. External bus packing to16-, 32-, or 48-bit words is performed during DMA transfers.

Ten channels of DMA are available on the ADSP-2106x—twovia the link ports, four via the serial ports, and four via theprocessor’s external port (for either host processor, otherADSP-2106xs, memory or I/O transfers). Four additional linkport DMA channels are shared with serial port 1 and the exter-nal port. Programs can be downloaded to the ADSP-2106xusing DMA transfers. Asynchronous off-chip peripherals cancontrol two DMA channels using DMA Request/Grant lines(DMAR1-2, DMAG1-2 ). Other DMA features include inter-rupt generation upon completion of DMA transfers and DMAchaining for automatic linked DMA transfers.

–6–


REV. B

ADDR31-0

DATA47-0

CPA

BR2-6

BR1

BMS

CONTROL

ADSP-2106x #1

5

CPA

BR1, BR3-6BR2

CONTROL

ADSP-2106x #2

ADDR31-0

DATA47-0

CPA

BR1-2, BR4-6

BR3

CONTROL

ADSP-2106x #3

5

3011 ID2-0

RESET

RPBA

CLKIN

ADSP-2106x #6ADSP-2106x #5ADSP-2106x #4

CO

NT

RO

L

AD

DR

ES

S

DA

TA

1xCLOCK

RESET

ADDR

DATA

HOSTPROCESSORINTERFACE(OPTIONAL)

ACKCS

GLOBALMEMORY

ANDPERIPHERALS

(OPTIONAL)

OEWE

ADDR

DATA

CS

ADDR

DATA

BOOTEPROM

(OPTIONAL)

RDWR

MS3-0

SBTSSW

ADRCLK

CSHBRHBG

REDY

ACK

ADDR31-0

DATA47-0

5

3010 ID2-0

RESET

RPBA

CLKIN

ID2-0

RESET

RPBA

CLKIN

3001

CO

NT

RO

L

AD

DR

ES

S

DA

TA

PAGE

Figure 3. Shared Memory Multiprocessing System


–7–REV. B

IOP REGISTERS

NORMAL WORD ADDRESSING

0x0000 0000

0x0002 0000

0x0004 0000

0x0008 0000

0x0010 0000

0x0018 0000

0x0020 0000

0x0028 0000

0x0030 0000

0x0038 0000

INTERNALMEMORY

SPACE

0x003F FFFF

SHORT WORD ADDRESSING

INTERNAL MEMORY SPACEOF ADSP-2106x

WITH ID=010


WITH ID=001


WITH ID=011


WITH ID=100


WITH ID=101


WITH ID=110

BROADCAST WRITETO ALL

ADSP-2106xs

MULTIPROCESSORMEMORY SPACE

NORMAL WORD ADDRESSING: 32-BIT DATA WORDS 48-BIT INSTRUCTION WORDSSHORT WORD ADDRESSING: 16-BIT DATA WORDS

MS0

BANK 0

0x0040 0000

0xFFFF FFFF

BANK 1

BANK 2

DRAM(OPTIONAL)

BANK 3

NONBANKED

MS1

MS2

MS3

BANK SIZE ISSELECTED BYMSIZE BIT FIELD OFSYSCONREGISTER.

EXTERNALMEMORY

SPACE

Figure 4. ADSP-21060/ADSP-21060L Memory Map

CBUG and SHARCPAC are trademarks of Analog Devices, Inc.EZ-LAB is a registered trademark of Analog Devices, Inc.

DEVELOPMENT TOOLSThe ADSP-21060 is supported with a complete set of softwareand hardware development tools, including an EZ-ICE In-Circuit Emulator, EZ-Kit, and development software. TheSHARC EZ-Kit is a complete low cost package for DSP evalua-tion and prototyping. The EZ-Kit contains a PC plug-in card(EZ-LAB®) with an ADSP-21062 (5 V) processor. The EZ-Kitalso includes an optimizing compiler, assembler, instructionlevel simulator, run-time libraries, diagnostic utilities and acomplete set of example programs.

The same EZ-ICE hardware can be used for the ADSP-21061/ADSP-21062, to fully emulate the ADSP-21060, with the excep-tion of displaying and modifying the two new SPORTS registers.The emulator will not display these two registers, but yourcode can use them.

Analog Devices ADSP-21000 Family Development Softwareincludes an easy to use Assembler based on an algebraic syntax,Assembly Library/Librarian, Linker, instruction-level Simulator,an ANSI C optimizing Compiler, the CBug™ C Source—LevelDebugger and a C Runtime Library including DSP and math-ematical functions. The Optimizing Compiler includes Numeri-cal C extensions based on the work of the ANSI Numerical CExtensions Group. Numerical C provides extensions to the Clanguage for array selections, vector math operations, complexdata types, circular pointers and variably dimensioned arrays.

The ADSP-21000 Family Development Software is available forboth the PC and Sun platforms.

The ADSP-21061 EZ-ICE Emulator uses the IEEE 1149.1JTAG test access port of the ADSP-21061 processor to monitorand control the target board processor during emulation. TheEZ-ICE provides full-speed emulation, allowing inspection andmodification of memory, registers, and processor stacks. Nonin-trusive in-circuit emulation is assured by the use of theprocessor’s JTAG interface—the emulator does not affect targetsystem loading or timing.

Further details and ordering information are available in theADSP-21000 Family Hardware and Software Development Toolsdata sheet (ADDS-210xx-TOOLS). This data sheet can berequested from any Analog Devices sales office or distributor.

In addition to the software and hardware development toolsavailable from Analog Devices, third parties provide a widerange of tools supporting the SHARC processor family. Hard-ware tools include SHARC PC plug-in cards multiprocessorSHARC VME boards, and daughter and modules with multipleSHARCs and additional memory. These modules are based onthe SHARCPAC™ module specification. Third Party softwaretools include an Ada compiler, DSP libraries, operating systemsand block diagram design tools.

ADDITIONAL INFORMATIONThis data sheet provides a general overview of the ADSP-21060architecture and functionality. For detailed information on theADSP-21000 Family core architecture and instruction set, referto the ADSP-2106x SHARC User’s Manual, Second Edition.

–8–


REV. B

Pin Type Function

ADDR31-0 I/O/T External Bus Address. The ADSP-2106x outputs addresses for external memory and peripherals onthese pins. In a multiprocessor system the bus master outputs addresses for read/writes of the internalmemory or IOP registers of other ADSP-2106xs. The ADSP-2106x inputs addresses when a hostprocessor or multiprocessing bus master is reading or writing its internal memory or IOP registers.

DATA47-0 I/O/T External Bus Data. The ADSP-2106x inputs and outputs data and instructions on these pins. 32-bitsingle-precision floating-point data and 32-bit fixed-point data is transferred over bits 47–16 of thebus. 40-bit extended-precision floating-point data is transferred over bits 47–8 of the bus. 16-bit shortword data is transferred over bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred overbits 23–16. Pull-up resistors on unused DATA pins are not necessary.

MS3-0 O/T Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks ofexternal memory. Memory bank size must be defined in the ADSP-2106x’s system control register(SYSCON). The MS3-0 lines are decoded memory address lines that change at the same time as theother address lines. When no external memory access is occurring the MS3-0 lines are inactive; they areactive however when a conditional memory access instruction is executed, whether or not the conditionis true. MS0 can be used with the PAGE signal to implement a bank of DRAM memory (Bank 0). In amultiprocessing system the MS3-0 lines are output by the bus master.

RD I/O/T Memory Read Strobe. This pin is asserted (low) when the ADSP-2106x reads from external memorydevices or from the internal memory of other ADSP-2106xs. External devices (including other ADSP-2106xs) must assert RD to read from the ADSP-2106x’s internal memory. In a multiprocessing systemRD is output by the bus master and is input by all other ADSP-2106xs.

WR I/O/T Memory Write Strobe. This pin is asserted (low) when the ADSP-2106x writes to external memorydevices or to the internal memory of other ADSP-2106xs. External devices must assert WR to write tothe ADSP-2106x’s internal memory. In a multiprocessing system WR is output by the bus master andis input by all other ADSP-2106xs.

PAGE O/T DRAM Page Boundary. The ADSP-2106x asserts this pin to signal that an external DRAM pageboundary has been crossed. DRAM page size must be defined in the ADSP-2106x’s memory controlregister (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE signal canonly be activated for Bank 0 accesses. In a multiprocessing system PAGE is output by the bus master.

ADRCLK O/T Clock Output Reference. In a multiprocessing system ADRCLK is output by the bus master.

SW I/O/T Synchronous Write Select. This signal is used to interface the ADSP-2106x to synchronousmemory devices (including other ADSP-2106xs). The ADSP-2106x asserts SW (low) to provide anearly indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g., in aconditional write instruction). In a multiprocessing system, SW is output by the bus master and isinput by all other ADSP-2106xs to determine if the multiprocessor memory access is a read or write.SW is asserted at the same time as the address output. A host processor using synchronous writes mustassert this pin when writing to the ADSP-2106x(s).

ACK I/O/S Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an externalmemory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold offcompletion of an external memory access. The ADSP-2106x deasserts ACK as an output to add waitstates to a synchronous access of its internal memory. In a multiprocessing system, a slave ADSP-2106x deasserts the bus master’s ACK input to add wait state(s) to an access of its internal memory.The bus master has a keeper latch on its ACK pin that maintains the input at the level it was lastdriven to.

PIN FUNCTION DESCRIPTIONSADSP-21060 pin definitions are listed below. All pins are iden-tical on the ADSP-21060 and ADSP-21060L. Inputs identifiedas synchronous (S) must meet timing requirements with respectto CLKIN (or with respect to TCK for TMS, TDI). Inputsidentified as asynchronous (A) can be asserted asynchronouslyto CLKIN (or to TCK for TRST).

Unused inputs should be tied or pulled to VDD or GND,except for ADDR31-0, DATA47-0, FLAG3-0, SW, and inputs thathave internal pull-up or pull-down resistors (CPA, ACK, DTx,

DRx, TCLKx, RCLKx, LxDAT3-0, LxCLK, LxACK, TMSand TDI)—these pins can be left floating. These pins have alogic-level hold circuit that prevents the input from floatinginternally.

A = Asynchronous G = Ground I = InputO = Output P = Power Supply S = Synchronous(A/D) = Active Drive (O/D) = Open DrainT = Three-State (when SBTS is asserted, or when theADSP-2106x is a bus slave)


–9–REV. B

Pin Type Function

SBTS I/S Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address,data, selects and strobes in a high impedance state for the following cycle. If the ADSP-2106xattempts to access external memory while SBTS is asserted, the processor will halt and the memoryaccess will not be completed until SBTS is deasserted. SBTS should only be used to recover from hostprocessor/ADSP-2106x deadlock, or used with a DRAM controller.

IRQ2-0 I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive.

FLAG3-0 I/O/A Flag Pins. Each is configured via control bits as either an input or output. As an input, it can betested as a condition. As an output, it can be used to signal external peripherals.

TIMEXP O Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements tozero.

HBR I/A Host Bus Request. Must be asserted by a host processor to request control of the ADSP-2106x’sexternal bus. When HBR is asserted in a multiprocessing system, the ADSP-2106x that is bus masterwill relinquish the bus and assert HBG. To relinquish the bus, the ADSP-2106x places the address,data, select and strobe lines in a high impedance state. HBR has priority over all ADSP-2106x busrequests (BR6-1) in a multiprocessing system.

HBG I/O Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may takecontrol of the external bus. HBG is asserted (held low) by the ADSP-2106x until HBR is released. In amultiprocessing system, HBG is output by the ADSP-2106x bus master and is monitored by all others.

CS I/A Chip Select. Asserted by host processor to select the ADSP-2106x.

REDY (O/D) O Host Bus Acknowledge. The ADSP-2106x deasserts REDY (low) to add wait states to an asynchro-nous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; canbe programmed in ADREDY bit of SYSCON register to be active drive (A/D). REDY will only beoutput if the CS and HBR inputs are asserted.

DMAR1 I/A DMA Request 1 (DMA Channel 7).

DMAR2 I/A DMA Request 2 (DMA Channel 8).

DMAG1 O/T DMA Grant 1 (DMA Channel 7).

DMAG2 O/T DMA Grant 2 (DMA Channel 8).

BR6-1 I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-2106xs to arbitrate for bus master-ship. An ADSP-2106x only drives its own BRx line (corresponding to the value of its ID2-0 inputs) andmonitors all others. In a multiprocessor system with less than six ADSP-2106xs, the unused BRx pinsshould be pulled high; the processor’s own BRx line must not be pulled high or low because it is anoutput.

ID2-0 I Multiprocessing ID. Determines which multiprocessing bus request (BR1 – BR6) is used by ADSP-2106x. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 in single-processorsystems. These lines are a system configuration selection which should be hardwired or only changedat reset.

RPBA I/S Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessorbus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system con-figuration selection which must be set to the same value on every ADSP-2106x. If the value of RPBA ischanged during system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x.

CPA (O/D) I/O Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-2106x bus slaveto interrupt background DMA transfers and gain access to the external bus. CPA is an open drainoutput that is connected to all ADSP-2106xs in the system. The CPA pin has an internal 5 kΩ pull-upresistor. If core access priority is not required in a system, the CPA pin should be left unconnected.

DTx O Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.

DRx I Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.

TCLKx I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.

RCLKx I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.

–10–


REV. B

Pin Type Function

TFSx I/O Transmit Frame Sync (Serial Ports 0, 1).

RFSx I/O Receive Frame Sync (Serial Ports 0, 1).

LxDTA3-0 I/O Link Port Data (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down resistor that isenabled or disabled by the LPDRD bit of the LCOM register.

LxCLK I/O Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down resistor that isenabled or disabled by the LPDRD bit of the LCOM register.

LxACK I/O Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kΩ internal pull-down resistorthat is enabled or disabled by the LPDRD bit of the LCOM register.

EBOOT I EPROM Boot Select. When EBOOT is high, the ADSP-2106x is configured for booting from an 8-bit EPROM. When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See tablebelow. This signal is a system configuration selection that should be hardwired.

LBOOT I Link Boot. When LBOOT is high, the ADSP-2106x is configured for link port booting. WhenLBOOT is low, the ADSP-2106x is configured for host processor booting or no booting. See tablebelow. This signal is a system configuration selection that should be hardwired.

BMS I/O/T* Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indi-cates that no booting will occur and that ADSP-2106x will begin executing instructions from externalmemory. See table below. This input is a system configuration selection that should be hardwired.

*Three-statable only in EPROM boot mode (when BMS is an output).

EBOOT LBOOT BMS Booting Mode

1 0 Output EPROM (Connect BMS to EPROM chip select.)0 0 1 (Input) Host Processor0 1 1 (Input) Link Port0 0 0 (Input) No Booting. Processor executes from external memory.0 1 0 (Input) Reserved1 1 x (Input) Reserved

CLKIN I Clock In. External clock input to the ADSP-2106x. The instruction cycle rate is equal to CLKIN.CLKIN may not be halted, changed, or operated below the minimum specified frequency.

RESET I/A Processor Reset. Resets the ADSP-2106x to a known state and begins execution at the programmemory location specified by the hardware reset vector address. This input must be asserted (low) atpower-up.

TCK I Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.

TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-upresistor.

TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internalpull-up resistor.

TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST I/A Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-2106x. TRST has a 20 kΩ internal pull-up resistor.

EMU (O/D) O Emulation Status. Must be connected to the ADSP-2106x EZ-ICE target board connector only.

ICSA O Reserved, leave unconnected.

VDD P Power Supply; nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices. (30 pins).

GND G Power Supply Return. (30 pins).

NC Do Not Connect. Reserved pins which must be left open and unconnected.


–11–REV. B

TARGET BOARD CONNECTOR FOR EZ-ICE PROBEThe ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1JTAG test access port of the ADSP-2106x to monitor and controlthe target board processor during emulation. The EZ-ICE proberequires the ADSP-2106x’s CLKIN, TMS, TCK, TRST, TDI,TDO, EMU, and GND signals be made accessible on the targetsystem via a 14-pin connector (a 2 row × 7 pin strip header) suchas that shown in Figure 5. The EZ-ICE probe plugs directly ontothis connector for chip-on-board emulation. You must add thisconnector to your target board design if you intend to use theADSP-2106x EZ-ICE. The total trace length between the EZ-ICE connector and the furthest device sharing the EZ-ICEJTAG pins should be limited to 15 inches maximum for guaran-teed operation. This length restriction must include EZ-ICEJTAG signals that are routed to one or more ADSP-2106xdevices, or a combination of ADSP-2106x devices and otherJTAG devices on the chain.

TOP VIEW

13 14

11 12

9 10

9

7 8

5 6

3 4

1 2EMU

CLKIN (OPTIONAL)

TMS

TCK

TRST

TDI

TDO

GND

KEY (NO PIN)

BTMS

BTCK

BTRST

BTDI

GND

Figure 5. Target Board Connector For ADSP-2106x EZ-ICEEmulator (Jumpers in Place)

EM

U

TR

ST

TR

ST

EM

U

TR

ST

ADSP-2106x#1

JTAGDEVICE

(OPTIONAL)

ADSP-2106xn

TDI

EZ-ICEJTAG

CONNECTOR

OTHERJTAG

CONTROLLER

OPTIONAL

TC

K

TM

S

EMUTMS

TCK

TDO

CLKIN

TRST

TC

K

TM

S

TC

K

TM

S

TDI TDO TDI TDO TDOTDI

Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems

The 14-pin, 2-row pin strip header is keyed at the Pin 3 location —Pin 3 must be removed from the header. The pins must be0.025 inch square and at least 0.20 inch in length. Pin spacingshould be 0.1 × 0.1 inches. Pin strip headers are available fromvendors such as 3M, McKenzie and Samtec.

The BTMS, BTCK, BTRST and BTDI signals are provided sothe test access port can also be used for board-level testing.When the connector is not being used for emulation, placejumpers between the Bxxx pins and the xxx pins. If the testaccess port will not be used for board testing, tie BTRST to GNDand tie or pull BTCK up to VDD. The TRST pin must beasserted after power-up (through BTRST on the connector) orheld low for proper operation of the ADSP-2106x. None of theBxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE probe.

The JTAG signals are terminated on the EZ-ICE probe asfollows:

Signal Termination

TMS Driven through 22 Ω Resistor (16 mA Driver)TCK Driven at 10 MHz through 22 Ω Resistor (16 mA

Driver)TRST* Active Low Driven through 22 Ω Resistor (16 mA

Driver) (Pulled Up by On-Chip 20 kΩ Resistor)TDI Driven by 22 Ω Resistor (16 mA Driver)TDO One TTL Load, Split Termination (160/220)CLKIN One TTL Load, Split Termination (160/220)EMU Active Low 4.7 kΩ Pull-Up Resistor, One TTL Load

(Open-Drain Output from the DSP)

*TRST is driven low until the EZ-ICE probe is turned on by the emulator atsoftware start-up. After software start-up, TRST is driven high.

Figure 6 shows JTAG scan path connections for systems thatcontain multiple ADSP-2106x processors.

–12–


REV. B

SYSTEMCLKINEMU

5kV*

TDI TDO

5kV*

TDI

EMU

TMS

TCK

TDO

TRST

CLKIN

*OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,

TDI TDO TDI TDO

TDI TDO TDI TDO TDI TDO

Figure 7. JTAG Clocktree for Multiple ADSP-2106x Systems

Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.The emulator only uses CLKIN when directed to performoperations such as starting, stopping and single-stepping mul-tiple ADSP-21061 in a synchronous manner. If you do not needthese operations to occur synchronously on the multiple proces-sors, simply tie Pin 4 of the EZ-ICE header to ground.

If synchronous multiprocessor operations are needed andCLKIN is connected, clock skew between the multiple ADSP-21061/ADSP-21061L processors and the CLKIN pin on theEZ-ICE header must be minimal. If the skew is too large, syn-chronous operations may be off by one or more cycles betweenprocessors. For synchronous multiprocessor operation TCK,

TMS, CLKIN and EMU should be treated as critical signals interms of skew, and should be laid out as short as possible onyour board. If TCK, TMS and CLKIN are driving a large num-ber of ADSP-21061 (more than eight) in your system, thentreat them as a clock tree using multiple drivers to minimizeskew. (See Figure 7, JTAG Clock Tree, and Clock Distributionin the High Frequency Design Considerations section of theADSP-2106x User’s Manual, Second Edition.)

If synchronous multiprocessor operations are not needed (i.e.,CLKIN is not connected), just use appropriate parallel termina-tion on TCK and TMS. TDI, TDO, EMU and TRST are notcritical signals in terms of skew.

For complete information on the SHARC EZ-ICE, see the ADSP-2100 Family JTAG EZ-ICE User’s Guide and Reference.

ADSP-21060–SPECIFICATIONSRECOMMENDED OPERATING CONDITIONS (5 V)

K GradeParameter Test Conditions Min Max Units

VDD Supply Voltage 4.75 5.25 V

TCASE Case Operating Temperature 0 +85 °C

VIH1 High Level Input Voltage1 @ VDD = max 2.0 VDD + 0.5 V


VIL Low Level Input Voltage1, 2 @ VDD = min –0.5 0.8 V

NOTES1Applies to input and bidirectional pins: DATA 47-0, ADDR31-0, RD, WR, SW, ACK, SBTS, IRQ2-0, FLAG3-0, HBG, CS, DMAR1, DMAR2, BR6-1, ID2-0, RPBA,CPA, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.

2Applies to input pins: CLKIN, RESET, TRST.

ELECTRICAL CHARACTERISTICS (5 V)Parameter Test Conditions Min Max Units

VOH High Level Output Voltage1 @ VDD = min, IOH = –2.0 mA2 4.1 V

VOL Low Level Output Voltage1 @ VDD = min, IOL = 4.0 mA2 0.4 V

IIH High Level Input Current3, 4 @ VDD = max, VIN = VDD max 10 µA

IIL Low Level Input Current3 @ VDD = max, VIN = 0 V 10 µA

IILP Low Level Input Current4 @ VDD = max, VIN = 0 V 150 µA

IOZH Three-State Leakage Current5, 6, 7, 8 @ VDD = max, VIN = VDD max 10 µA

IOZL Three-State Leakage Current5, 9 @ VDD = max, VIN = 0 V 10 µA

IOZHP Three-State Leakage Current9 @ VDD = max, VIN = VDD max 350 µA

IOZLC Three-State Leakage Current7 @ VDD = max, VIN = 0 V 1.5 mA

IOZLA Three-State Leakage Current10 @ VDD = max, VIN = 1.5 V 350 µA

IOZLAR Three-State Leakage Current8 @ VDD = max, VIN = 0 V 4.2 mA

IOZLS Three-State Leakage Current6 @ VDD = max, VIN = 0 V 150 mA

CIN Input Capacitance11, 12 fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V 4.7 pF

NOTESS11Applies to output and bidirectional pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1,

DMAG2, BR6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.12See “Output Drive Currents” for typical drive current capabilities.13Applies to input pins: ACK SBTS, IRQ2-0, HBR, CS, DMAR1, DMAR2, ID2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.14Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.15Applies to three-statable pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR6–1,

TFSX, RFSX, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another ADSP-21062 isnot requesting bus mastership.)

16Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.17Applies to CPA pin.18Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another

ADSP-21060L is not requesting bus mastership).19Applies to three-statable pins with internal pull-downs: LxDAT3-0, LxCLK, LxACK.10Applies to ACK pin when keeper latch enabled.11Applies to all signal pins.12Guaranteed but not tested.

Specifications subject to change without notice.


REV. B –13–

–14–


REV. B

POWER DISSIPATION ADSP-21060 (5 V)These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calcula-tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, seethe technical note “SHARC Power Dissipation Measurements.”

Specifications are based on the following operating scenarios:

Operation Peak Activity (IDDINPEAK) High Activity (IDDINHIGH) Low Activity (IDDINLOW)

Instruction Type Multifunction Multifunction Single Function

Instruction Fetch Cache Internal Memory Internal Memory

Core Memory Access 2 per Cycle (DM and PM) 1 per Cycle (DM) None

Internal Memory DMA 1 per Cycle 1 per 2 Cycles 1 per 2 Cycles

To estimate power consumption for a specific application, use the following equation where % is the amount of time your programspends in that state:

%PEAK × IDDINPEAK + %HIGH × IDDINHIGH + %LOW × IDDINLOW + %IDLE × IDDIDLE = power consumption

Parameter Test Conditions Max Units

IDDINPEAK Supply Current (Internal)1 tCK = 30 ns, VDD = max, 745 mAtCK = 25 ns, VDD = max, 850 mA

IDDINHIGH Supply Current (Internal)2 tCK = 30 ns, VDD = max, 575 mAtCK = 25 ns, VDD = max, 670 mA

IDDINLOW Supply Current (Internal)2 tCK = 30 ns, VDD = max, 340 mAtCK = 25 ns, VDD = max, 390 mA

IDDIDLE Supply Current (Idle)3 VDD = max 200 mA

NOTESS1The test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internalpower measurements made using typical applications are less than specified.

2IDDINHIGH is a composite average based on a range of high activity code. IDDINLOW is a composite average based on a range of low activity code.3Idle denotes ADSP-21060L state during execution of IDLE instruction.

ADSP-21060L–SPECIFICATIONSRECOMMENDED OPERATING CONDITIONS (3.3 V)

K GradeParameter Test Conditions Min Max Units

VDD Supply Voltage 3.15 3.45 V

TCASE Case Operating Temperature 0 +85 °C



VIL Low Level Input Voltage1, 2 @ VDD = min –0.5 0.8 V

NOTES1Applies to input and bidirectional pins: DATA 47-0, ADDR31-0, RD, WR, SW, ACK, SBTS, IRQ2-0, FLAG3-0, HBG, CS, DMAR1, DMAR2, BR6-1, ID2-0, RPBA,CPA, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0,RCLK1.

2Applies to input pins: CLKIN, RESET, TRST.

ELECTRICAL CHARACTERISTICS (3.3 V)Parameter Test Conditions Min Max Units

VOH High Level Output Voltage1 @ VDD = min, IOH = –2.0 mA2 2.4 V

VOL Low Level Output Voltage1 @ VDD = min, IOL = 4.0 mA2 0.4 V

IIH High Level Input Current3, 4 @ VDD = max, VIN = VDD max 10 µA

IIL Low Level Input Current3 @ VDD = max, VIN = 0 V 10 µA

IILP Low Level Input Current4 @ VDD = max, VIN = 0 V 150 µA

IOZH Three-State Leakage Current5, 6, 7, 8 @ VDD = max, VIN = VDD max 10 µA

IOZL Three-State Leakage Current5, 9 @ VDD = max, VIN = 0 V 10 µA

IOZHP Three-State Leakage Current9 @ VDD = max, VIN = VDD max 350 µA

IOZLC Three-State Leakage Current7 @ VDD = max, VIN = 0 V 1.5 mA

IOZLA Three-State Leakage Current10 @ VDD = max, VIN = 2 V 350 µA

IOZLAR Three-State Leakage Current8 @ VDD = max, VIN = 0 V 4.2 mA

IOZLS Three-State Leakage Current6 @ VDD = max, VIN = 0 V 150 mA

CIN Input Capacitance11, 12 fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V 4.7 pF

NOTESS11Applies to output and bidirectional pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1,

DMAG2, BR6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.12See “Output Drive Currents” for typical drive current capabilities.13Applies to input pins: ACK SBTS, IRQ2-0, HBR, CS, DMAR1, DMAR2, ID2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.14Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.15Applies to three-statable pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR6–1,

TFSX, RFSX, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another ADSP-21062 isnot requesting bus mastership.)

16Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.17Applies to CPA pin.18Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another

ADSP-21060L is not requesting bus mastership).19Applies to three-statable pins with internal pull-downs: LxDAT3-0, LxCLK, LxACK.10Applies to ACK pin when keeper latch enabled.11Applies to all signal pins.12Guaranteed but not tested.

Specifications subject to change without notice.


–15–REV. B

–16–


REV. B

POWER DISSIPATION ADSP-21060L (3.3 V)These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calcula-tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation,see the technical note “SHARC Power Dissipation Measurements.”

Specifications are based on the following operating scenarios:

Operation Peak Activity (IDDINPEAK) High Activity (IDDINHIGH) Low Activity (IDDINLOW)

Instruction Type Multifunction Multifunction Single Function

Instruction Fetch Cache Internal Memory Internal Memory

Core Memory Access 2 per Cycle (DM and PM) 1 per Cycle (DM) None

Internal Memory DMA 1 per Cycle 1 per 2 Cycles 1 per 2 Cycles

To estimate power consumption for a specific application, use the following equation where % is the amount of time your programspends in that state:

%PEAK × IDDINPEAK + %HIGH × IDDINHIGH + %LOW × IDDINLOW + %IDLE × IDDIDLE = power consumption

Parameter Test Conditions Max Units

IDDINPEAK Supply Current (Internal)1 tCK = 30 ns, VDD = max, 540 mAtCK = 25 ns, VDD = max, 600 mA

IDDINHIGH Supply Current (Internal)2 tCK = 30 ns, VDD = max, 425 mAtCK = 25 ns, VDD = max, 475 mA

IDDINLOW Supply Current (Internal)2 tCK = 30 ns, VDD = max, 250 mAtCK = 25 ns, VDD = max, 275 mA

IDDIDLE Supply Current (Idle)3 VDD = max 180 mA

NOTESS1The test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internalpower measurements made using typical applications are less than specified.

2IDDINHIGH is a composite average based on a range of high activity code. IDDINLOW is a composite average based on a range of low activity code.3Idle denotes ADSP-21060L state during execution of IDLE instruction.


–17–REV. B

ABSOLUTE MAXIMUM RATINGS (5 V)*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 VInput Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 VOutput Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 VLoad Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pFJunction Temperature Under Bias . . . . . . . . . . . . . . . . 130°CStorage Temperature Range . . . . . . . . . . . . –65°C to +150°CLead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only, and functional operation of the device at theseor any other conditions greater than those indicated in the operational sections ofthis specification is not implied. Exposure to absolute maximum rating conditionsfor extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS (3.3 V)*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 VInput Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 VOutput Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 VLoad Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pFJunction Temperature Under Bias . . . . . . . . . . . . . . . . 130°CStorage Temperature Range . . . . . . . . . . . . –65°C to +150°CLead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only, and functional operation of the device at theseor any other conditions greater than those indicated in the operational sections ofthis specification is not implied. Exposure to absolute maximum rating conditionsfor extended periods may affect device reliability.

ESD SENSITIVITYThe ADSP-2106x processors are ESD (electrostatic discharge) sensitive devices. Electro-static charges readily accumulate on the human body and equipment and can dischargewithout detection. Permanent damage may occur to devices subjected to high energyelectrostatic discharges.

The ADSP-2106x processors include proprietary ESD protection circuitry to dissipatehigh energy discharges. Per method 3015 of MIL-STD-883, the ADSP-2106x processorshave been classified as a Class 2 device.

Proper ESD precautions are recommended to avoid performance degradation or loss offunctionality. Unused devices must be stored in conductive foam or shunts, and the foamshould be discharged to the destination socket before devices are removed.

TIMING SPECIFICATIONSTwo speed grades of the ADSP-21060 are offered, 40 MHz and33.3 MHz. The specifications shown are based on a CLKINfrequency of 40 MHz (tCK = 25 ns). The DT derating allowsspecifications at other CLKIN frequencies (within the min–maxrange of the tCK specification; see Clock Input below). DT isthe difference between the actual CLKIN period and a CLKINperiod of 25 ns:

DT = tCK – 25 ns

Use the exact timing information given. Do not attempt toderive parameters from the addition or subtraction of others.While addition or subtraction would yield meaningful results foran individual device, the values given in this data sheet reflectstatistical variations and worst cases. Consequently, you cannotmeaningfully add parameters to derive longer times.

See Figure 28 under Test Conditions for voltage referencelevels.

Switching Characteristics specify how the processor changes itssignals. You have no control over this timing—circuitry externalto the processor must be designed for compatibility with thesesignal characteristics. Switching characteristics tell you what theprocessor will do in a given circumstance. You can also useswitching characteristics to ensure that any timing requirementof a device connected to the processor (such as memory) issatisfied.

Timing Requirements apply to signals that are controlled by cir-cuitry external to the processor, such as the data input for aread operation. Timing requirements guarantee that the proces-sor operates correctly with other devices.

(O/D) = Open Drain(A/D) = Active Drive

WARNING!

ESD SENSITIVE DEVICE

–18–


REV. B

ADSP-21060 ADSP-21060L 40 MHz 33 MHz 40 MHz 33 MHz

Parameter Min Max Min Max Min Max Min Max Units

Clock Input

Timing Requirements:tCK CLKIN Period 25 100 30 100 25 100 30 100 nstCKL CLKIN Width Low 7 7 8.75 8.75 nstCKH CLKIN Width High 5 5 5 5 nstCKRF CLKIN Rise/Fall (0.4 V–2.0 V) 3 3 3 3 ns

CLKIN

tCKH

tCK

tCKL

Figure 8. Clock Input

ADSP-21060 ADSP-21060LParameter Min Max Min Max Units

Reset

Timing Requirements:tWRST RESET Pulsewidth Low1 4tCK 4tCK nstSRST RESET Setup before CLKIN High2 14 + DT/2 tCK 14 + DT/2 tCK ns

NOTES1Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESETis low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).

2Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not requiredfor multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.

CLKIN

RESET

tWRST

tSRST

Figure 9. Reset


InterruptsTiming Requirements:tSIR IRQ2-0 Setup before CLKIN High1 18 + 3DT/4 18 + 3DT/4 nstHIR IRQ2-0 Hold before CLKIN High1 12 + 3DT/4 12 + 3DT/4 nstIPW IRQ2-0 Pulsewidth2 2 + tCK 2 + tCK ns

NOTES1Only required for IRQx recognition in the following cycle.2Applies only if tSIR and tHIR requirements are not met.

CLKIN

IRQ2-0

tIPW

tSIR

tHIR

Figure 10. Interrupts


–19–REV. B


TimerSwitching Characteristic:tDTEX CLKIN High to TIMEXP 15 15 ns

CLKIN

tDTEX tDTEX

TIMEXP

Figure 11. Timer


FlagsTiming Requirements:tSFI FLAG3-0IN Setup before CLKIN High1 8 + 5DT/16 8 + 5DT/16 nstHFI FLAG3-0IN Hold after CLKIN High1 0 – 5DT/16 0 – 5DT/16 nstDWRFI FLAG3-0IN Delay after RD/WR Low1 5 + 7DT/16 5 + 7DT/16 nstHFIWR FLAG3-0IN Hold after RD/WR Deasserted1 0 0 ns

Switching Characteristics:tDFO FLAG3-0OUT Delay after CLKIN High 16 16 nstHFO FLAG3-0OUT Hold after CLKIN High 4 4 nstDFOE CLKIN High to FLAG3-0OUT Enable 3 3 nstDFOD CLKIN High to FLAG3-0OUT Disable 14 14 ns

NOTE1Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.

CLKIN

FLAG3-0OUT

FLAG OUTPUT

tDFO tHFO

tDFO tDFOD

tDFOE

CLKIN

RD, WR

FLAG INPUT

tSFI

tHFI

tHFIWR tDWRFI

FLAG3-0IN

Figure 12. Flags

–20–


REV. B


Timing Requirements:tDAD Address, Selects Delay to Data Valid1, 2 18 + DT + W 18 + DT + W nstDRLD RD Low to Data Valid1 12 + 5DT/8 + W 12 + 5DT/8 + W nstHDA Data Hold from Address, Selects3 0.5 0.5 nstHDRH Data Hold from RD High3 2.0 2.0 nstDAAK ACK Delay from Address, Selects2, 4 14 + 7DT/8 + W 14 + 7DT/8 + W nstDSAK ACK Delay from RD Low4 8 + DT/2 + W 8 + DT/2 + W ns

Switching Characteristics:tDRHA Address, Selects Hold after RD High 0 + H 0 + H nstDARL Address, Selects to RD Low2 2 + 3DT/8 2 + 3DT/8 nstRW RD Pulsewidth 12.5 + 5DT/8 + W 12.5 + 5DT/8 + W nstRWR RD High to WR, RD, DMAGx Low 8 + 3DT/8 + HI 8 + 3DT/8 + HI nstSADADC Address, Selects Setup before

ADRCLK High2 0 + DT/4 0 + DT/4 ns

W = (number of wait states specified in WAIT register) × tCK.

HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

NOTES1Data Delay/Setup: User must meet tDAD or tDRLD or synchronous spec tSSDATI.2The falling edge of MSx, SW, BMS is referenced.3Data Hold: User must meet tHDA or tHDRH or synchronous spec tHSDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold timesgiven capacitive and dc loads.

4ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for asser-tion of ACK (High).

WR, DMAG

ACK

DATA

RD

ADDRESSMSx, SW

BMS

tDARL tRW

tDAD

tSADADC

tDAAK

tHDRH

tHDA

tRWR

tDRLD

ADRCLK (OUT)

tDRHA

tDSAK

Figure 13. Memory Read—Bus Master

Memory Read—Bus MasterUse these specifications for asynchronous interfacing to memo-ries (and memory-mapped peripherals) without reference toCLKIN. These specifications apply when the ADSP-2106x isthe bus master accessing external memory space. These switching

characteristics also apply for bus master synchronous read/writetiming (see Synchronous Read/Write – Bus Master below). Ifthese timing requirements are met, the synchronous read/writetiming can be ignored (and vice versa).


–21–REV. B


Timing Requirements:tDAAK ACK Delay from Address, Selects1, 2 14 + 7DT/8 + W 14 + 7DT/8 + W nstDSAK ACK Delay from WR Low1 8 + DT/2 + W 8 + DT/2 + W ns

Switching Characteristics:tDAWH Address, Selects to WR Deasserted2 17 + 15DT/16 + W 17 + 15DT/16 + W nstDAWL Address, Selects to WR Low2 3 + 3DT/8 3 + 3DT/8 nstWW WR Pulsewidth 12 + 9DT/16 + W 12 + 9DT/16 + W nstDDWH Data Setup before WR High 7 + DT/2 + W 7 + DT/2 + W nstDWHA Address Hold after WR Deasserted 0.5 + DT/16 + H 0.5 + DT/16 + H nstDATRWH Data Disable after WR Deasserted3 1 + DT/16 + H 6 + DT/16 + H 1 + DT/16 + H 6 + DT/16 + H nstWWR WR High to WR, RD, DMAGx Low 8 + 7DT/16 + H 8 + 7DT/16 + H nstDDWR Data Disable before WR or RD Low 5 + 3DT/8 + I 5 + 3DT/8 + I nstWDE WR Low to Data Enabled –1 + DT/16 –1 + DT/16 nstSADADC Address, Selects to ADRCLK High2 0 + DT/4 0 + DT/4 ns

Memory Write—Bus MasterUse these specifications for asynchronous interfacing to memo-ries (and memory-mapped peripherals) without reference toCLKIN. These specifications apply when the ADSP-2106x isthe bus master accessing external memory space. These switching

characteristics also apply for bus master synchronous read/writetiming (see Synchronous Read/Write–Bus Master). If thesetiming requirements are met, the synchronous read/write timingcan be ignored (and vice versa).

W = (number of wait states specified in WAIT register) × tCK.H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

NOTES1ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for asser-tion of ACK (High).

2The falling edge of MSx, SW, BMS is referenced.3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

RD , DMAG

ACK

DATA

WR

ADDRESSMSx , SW

BMS

tDAWL tWW

tSADADC

tDAAK

tWWR tWDE

ADRCLK(OUT)

tDDWR tDATRWH

tDWHA

tDDWH

tDAWH

tDSAK

Figure 14. Memory Write—Bus Master

–22–


REV. B


Timing Requirements:tSSDATI Data Setup before CLKIN 3 + DT/8 3 + DT/8 nstHSDATI Data Hold after CLKIN 3.5 – DT/8 3.5 – DT/8 nstDAAK ACK Delay after Address, MSx,

SW, BMS1, 2 14 + 7 DT/8 + W 14 + 7 DT/8 + W nstSACKC ACK Setup before CLKIN2 6.5 + DT/4 6.5 + DT/4 nstHACK ACK Hold after CLKIN –1 – DT/4 –1 – DT/4 ns

Switching Characteristics:tDADRO Address, MSx, BMS, SW Delay

after CLKIN1 7 – DT/8 7 – DT/8 nstHADRO Address, MSx, BMS, SW Hold

after CLKIN –1 – DT/8 –1 – DT/8 nstDPGC PAGE Delay after CLKIN 9 + DT/8 16 + DT/8 9 + DT/8 16 + DT/8 nstDRDO RD High Delay after CLKIN –2 – DT/8 4 – DT/8 –2 – DT/8 4 – DT/8 nstDWRO WR High Delay after CLKIN –3 – 3DT/16 4 – 3DT/16 –3 – 3DT/16 4 – 3DT/16 nstDRWL RD/WR Low Delay after CLKIN 8 + DT/4 12.5 + DT/4 8 + DT/4 12.5 + DT/4 nstSDDATO Data Delay after CLKIN 19 + 5DT/16 19 + 5DT/16 nstDATTR Data Disable after CLKIN3 0 – DT/8 7 – DT/8 0 – DT/8 7 – DT/8 nstDADCCK ADRCLK Delay after CLKIN 4 + DT/8 10 + DT/8 4 + DT/8 10 + DT/8 nstADRCK ADRCLK Period tCK tCK nstADRCKH ADRCLK Width High (tCK/2 – 2) (tCK/2 – 2) nstADRCKL ADRCLK Width Low (tCK/2 – 2) (tCK/2 – 2) ns

W = (number of Wait states specified in WAIT register) × tCK.

NOTES1The falling edge of MSx, SW, BMS is referenced.2ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for assertionof ACK (High).

3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

Synchronous Read/Write—Bus MasterUse these specifications for interfacing to external memorysystems that require CLKIN—relative timing or for accessing aslave ADSP-2106x (in multiprocessor memory space). Thesesynchronous switching characteristics are also valid during asyn-chronous memory reads and writes (see Memory Read—BusMaster and Memory Write—Bus Master).

When accessing a slave ADSP-2106x, these switching character-istics must meet the slave’s timing requirements for synchronousread/writes (see Synchronous Read/Write—Bus Slave). Theslave ADSP-2106x must also meet these (bus master) timingrequirements for data and acknowledge setup and hold times.


–23–REV. B

CLKIN

ADRCLK

ADDRESSMSx, SW

ACK (IN)

PAGE

RD

DATA(OUT)

WR

tDADCCK

tADRCK

tADRCKL

tHADRO

tDAAK

tDPGC

tDRWL

tSACKC

tHACK

tHSDATI

tSSDATI

tDRDO

tDWRO

tDATTR tSDDATO

tDRWL

DATA (IN)

tDADRO

tADRCKH

WRITE CYCLE

READ CYCLE

Figure 15. Synchronous Read/Write—Bus Master

–24–


REV. B


Timing Requirements:tSADRI Address, SW Setup before CLKIN 15 + DT/2 15 + DT/2 nstHADRI Address, SW Hold before CLKIN 5 + DT/2 5 + DT/2 nstSRWLI RD/WR Low Setup before CLKIN1 9.5 + 5DT/16 9.5 + 5DT/16 nstHRWLI RD/WR Low Hold after CLKIN –4 – 5DT/16 8 + 7DT/16 –4 – 5DT/16 8 + 7DT/16 nstRWHPI RD/WR Pulse High 3 3 nstSDATWH Data Setup before WR High 5 5 nstHDATWH Data Hold after WR High 1 1 ns

Switching Characteristics:tSDDATO Data Delay after CLKIN 19 + 5DT/16 19 + 5DT/16 nstDATTR Data Disable after CLKIN2 0 – DT/8 7 – DT/8 0 – DT/8 7 – DT/8 nstDACKAD ACK Delay after Address, SW3 9 9 nstACKTR ACK Disable after CLKIN3 –1 – DT/8 6 – DT/8 –1 – DT/8 6 – DT/8 ns

NOTES1tSRWLI (min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t SRWLI (min)= 4 + DT/8.

2See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.3tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and SW inputs havesetup times greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACKregardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t ACKTR.

CLKIN

ADDRESSSW

ACK

RD

DATA (OUT)

WR

WRITE ACCESS

tSADRI tHADRI

tDACKAD tACKTR

tRWHPI tHRWLI tSRWLI

tSDDATO tDATTR

tSRWLI tHRWLI tRWHPI

tHDATWH tSDATWH

DATA(IN)

READ ACCESS

Figure 16. Synchronous Read/Write—Bus Slave

Synchronous Read/Write—Bus SlaveUse these specifications for ADSP-2106x bus master accesses ofa slave’s IOP registers or internal memory (in multiprocessor

memory space). The bus master must meet these (bus slave)timing requirements.


–25–REV. B


Timing Requirements:tHBGRCSV HBG Low to RD/WR/CS Valid1 20+ 5DT/4 20+ 5DT/4 nstSHBRI HBR Setup before CLKIN2 20 + 3DT/4 20 + 3DT/4 nstHHBRI HBR Hold before CLKIN2 14 + 3DT/4 14 + 3DT/4 nstSHBGI HBG Setup before CLKIN 13 + DT/2 13 + DT/2 nstHHBGI HBG Hold before CLKIN High 6 + DT/2 6 + DT/2 nstSBRI BRx, CPA Setup before CLKIN3 13 + DT/2 13 + DT/2 nstHBRI BRx, CPA Hold before CLKIN High 6 + DT/2 6 + DT/2 nstSRPBAI RPBA Setup before CLKIN 21 + 3DT/4 21 + 3DT/4 nstHRPBAI RPBA Hold before CLKIN 12 + 3DT/4 12 + 3DT/4 ns

Switching Characteristics:tDHBGO HBG Delay after CLKIN 7 – DT/8 7 – DT/8 nstHHBGO HBG Hold after CLKIN –2 – DT/8 –2 – DT/8 nstDBRO BRx Delay after CLKIN 7 – DT/8 7 – DT/8 nstHBRO BRx Hold after CLKIN –2 – DT/8 –2 – DT/8 nstDCPAO CPA Low Delay after CLKIN 8 – DT/8 8 – DT/8 nstTRCPA CPA Disable after CLKIN –2 – DT/8 4.5 – DT/8 –2 – DT/8 4.5 – DT/8 nstDRDYCS REDY (O/D) or (A/D) Low from CS

and HBR Low4 8.5 9.25 nstTRDYHG REDY (O/D) Disable or REDY (A/D)

High from HBG4 44 + 23DT/16 44 + 23DT/16 nstARDYTR REDY (A/D) Disable from CS or

HBR High4 10 10 ns

NOTES1For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 tCK before RD or WR goes low or by tHBGRCSV after HBG goeslow. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in theADSP-2106x SHARC User’s Manual, Second Edition .

2Only required for recognition in the current cycle.3CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.4(O/D) = open drain, (A/D) = active drive.

Multiprocessor Bus Request and Host Bus RequestUse these specifications for passing of bus mastership betweenmultiprocessing ADSP-2106xs (BRx) or a host processor(HBR, HBG).

–26–


REV. B

CLKIN

HBR

HBG(OUT)

BRx(OUT)

HBG (IN)

BRx (IN)

REDY (O/D)

RDWRCS

HBG (OUT)

REDY (A/D)

RPBA

CPA (OUT) (O/D)

CPA (IN) (O/D)

tSHBGI

tSBRI

tHHBGI

tHBRI

tHBGRCSV

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

tDRDYCS tTRDYHG

tSHBRI tHHBRI

tHHBGO

tDHBGO

tHBRO

tDBRO

tDCPAO tTRCPA

tARDYTR

tSRPBAI

tHRPBAI

HBR AND CS

Figure 17. Multiprocessor Bus Request and Host Bus Request


–27–REV. B


Read CycleTiming Requirements:tSADRDL Address Setup/CS Low before RD Low1 0 0 nstHADRDH Address Hold/CS Hold Low after RD 0 0 nstWRWH RD/WR High Width 6 6 nstDRDHRDY RD High Delay after REDY (O/D) Disable 0 0 nstDRDHRDY RD High Delay after REDY (A/D) Disable 0 0 ns

Switching Characteristics:tSDATRDY Data Valid before REDY Disable from Low 2 2 nstDRDYRDL REDY (O/D) or (A/D) Low Delay after RD Low 10 10.5 nstRDYPRD REDY (O/D) or (A/D) Low Pulsewidth

for Read 45 + 21DT/16 45 + 21DT/16 nstHDARWH Data Disable after RD High 2 8 2 8.5 ns

Write CycleTiming Requirements:tSCSWRL CS Low Setup before WR Low 0 0 nstHCSWRH CS Low Hold after WR High 0 0 nstSADWRH Address Setup before WR High 5 5 nstHADWRH Address Hold after WR High 2 2 nstWWRL WR Low Width 7 7 nstWRWH RD/WR High Width 6 6 nstDWRHRDY WR High Delay after REDY

(O/D) or (A/D) Disable 0 0 nstSDATWH Data Setup before WR High 5 5 nstHDATWH Data Hold after WR High 1 1 ns

Switching Characteristics:tDRDYWRL REDY (O/D) or (A/D) Low Delay

after WR/CS Low 10 10.5 nstRDYPWR REDY (O/D) or (A/D) Low Pulsewidth

for Write 15 + 7DT/16 15 + 7DT/16 nstSRDYCK REDY (O/D) or (A/D) Disable to CLKIN 1 + 7DT/16 8 + 7DT/16 1 + 7DT/16 8 + 7DT/16 ns

NOTE1Not required if RD and address are valid tHBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 tCLK before RDor WR goes low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Proces-sor Control of the ADSP-2106x” section in the ADSP-2106x SHARC User’s Manual, Second Edition.

CLKIN

REDY (O/D)


tSRDYCK

REDY (A/D)

Figure 18a. Synchronous REDY Timing

Asynchronous Read/Write—Host to ADSP-2106xUse these specifications for asynchronous host processor accessesof an ADSP-2106x, after the host has asserted CS and HBR(low). After HBG is returned by the ADSP-2106x, the host can

drive the RD and WR pins to access the ADSP-2106x’s internalmemory or IOP registers. HBR and HBG are assumed low forthis timing.

–28–


REV. B

tSADRDL

REDY (O/D)

RD

tDRDYRDL

tWRWH

tHADRDH

tHDARWH

tRDYPRD

tDRDHRDY tSDATRDY

READ CYCLE

ADDRESS/CS

DATA (OUT)

REDY (A/D)


tSDATWH

tHDATWH

tWWRL

REDY (O/D)

WR

tDRDYWRL

tWRWH

tHADWRH

tRDYPWR

tDWRHRDY

WRITE CYCLE

tSADWRH

DATA (IN)

ADDRESS

REDY (A/D)

tSCSWRL

CS

tHCSWRH

Figure 18b. Asynchronous Read/Write—Host to ADSP-2106x


–29–REV. B


Timing Requirements:tSTSCK SBTS Setup before CLKIN 12 + DT/2 12 + DT/2 nstHTSCK SBTS Hold before CLKIN 6 + DT/2 6 + DT/2 ns

Switching Characteristics:tMIENA Address/Select Enable after CLKIN –1.5 – DT/8 –1.25 – DT/8 nstMIENS Strobes Enable after CLKIN1 –1.5 – DT/8 –1.5 – DT/8 nstMIENHG HBG Enable after CLKIN –1.5 – DT/8 –1.5 – DT/8 nstMITRA Address/Select Disable after CLKIN 0 – DT/4 0 – DT/4 nstMITRS Strobes Disable after CLKIN1 1.5 – DT/4 1.5 – DT/4 nstMITRHG HBG Disable after CLKIN 2.0 – DT/4 2.0 – DT/4 nstDATEN Data Enable after CLKIN2 9 + 5DT/16 9 + 5DT/16 nstDATTR Data Disable after CLKIN2 0 – DT/8 7 – DT/8 0 – DT/8 7 – DT/8 nstACKEN ACK Enable after CLKIN2 7.5 + DT/4 7.5 + DT/4 nstACKTR ACK Disable after CLKIN2 –1 – DT/8 6 – DT/8 –1 – DT/8 6 – DT/8 nstADCEN ADRCLK Enable after CLKIN –2 – DT/8 –2 – DT/8 nstADCTR ADRCLK Disable after CLKIN 8 – DT/4 8 – DT/4 nstMTRHBG Memory Interface Disable before

HBG Low3 0 + DT/8 0 + DT/8 nstMENHBG Memory Interface Enable after

HBG High3 19 + DT 19 + DT ns

NOTES1Strobes = RD, WR, SW, PAGE, DMAG.2In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.3Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).

Three-State Timing—Bus Master, Bus Slave, HBR, SBTSThese specifications show how the memory interface is disabled(stops driving) or enabled (resumes driving) relative to CLKIN

CLKIN

SBTS

ACK

tMITRA, tMITRS, tMITRHG

tSTSCKtHTSCK

tDATTRtDATEN

tACKTRtACKEN

tADCTRtADCEN

ADRCLK

DATA

tMIENA, tMIENS, tMIENHG

MEMORYINTERFACE

Figure 19a. Three-State Timing (Bus Transition Cycle, SBTS Assertion)

MEMORYINTERFACE

tMENHBG

tMTRHBGHBG

MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)

Figure 19b. Three-State Timing (Host Transition Cycle)

and the SBTS pin. This timing is applicable to bus master tran-sition cycles (BTC) and host transition cycles (HTC) as well asthe SBTS pin.

–30–


REV. B

transfer is controlled by ADDR31-0, RD, WR, MS3-0, and ACK(not DMAG). For Paced Master mode, the Memory Read–BusMaster, Memory Write–Bus Master, and Synchronous Read/Write–Bus Master timing specifications for ADDR31-0, RD, WR,MS3-0, SW, PAGE, DATA47-0, and ACK also apply.


Timing Requirements:tSDRLC DMARx Low Setup before CLKIN1 5 5 nstSDRHC DMARx High Setup before CLKIN1 5 5 nstWDR DMARx Width Low

(Nonsynchronous) 6 6 nstSDATDGL Data Setup after DMAGx Low2 10 + 5DT/8 10 + 5DT/8 nstHDATIDG Data Hold after DMAGx High 2 2 nstDATDRH Data Valid after DMARx High2 16 + 7DT/8 16 + 7DT/8 nstDMARLL DMARx Low Edge to Low Edge 23 + 7DT/8 23 + 7DT/8 nstDMARH DMARx Width High 6 6 ns

Switching Characteristics:tDDGL DMAGx Low Delay after CLKIN 9 + DT/4 15 + DT/4 9 + DT/4 15 + DT/4 nstWDGH DMAGx High Width 6 + 3DT/8 6 + 3DT/8 nstWDGL DMAGx Low Width 12 + 5DT/8 12 + 5DT/8 nstHDGC DMAGx High Delay after CLKIN –2 – DT/8 6 – DT/8 –2 – DT/8 6 – DT/8 nstVDATDGH Data Valid before DMAGx High3 8 + 9DT/16 8 + 9DT/16 nstDATRDGH Data Disable after DMAGx High4 0 7 0 7 nstDGWRL WR Low before DMAGx Low 0 2 0 2 nstDGWRH DMAGx Low before WR High 10 + 5DT/8 + W 10 + 5DT/8 + W nstDGWRR WR High before DMAGx High 1 + DT/16 3 + DT/16 1 + DT/16 3 + DT/16 nstDGRDL RD Low before DMAGx Low 0 2 0 2 nstDRDGH RD Low before DMAGx High 11 + 9DT/16 + W 11 + 9DT/16 + W nstDGRDR RD High before DMAGx High 0 3 0 3 nstDGWR DMAGx High to WR, RD, DMAGx

Low 5 + 3DT/8 + HI 5 + 3DT/8 + HI nstDADGH Address/Select Valid to DMAGx High 17 + DT 17 + DT nstDDGHA Address/Select Hold after DMAGx

High –0.5 –0.5 ns

W = (number of wait states specified in WAIT register) × tCK.HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

NOTES1Only required for recognition in the current cycle.2tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, thedata can be driven tDATDRH after DMARx is brought high.

3tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = 8 + 9DT/16 + (n × tCK) wheren equals the number of extra cycles that the access is prolonged.

4See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.

DMA HandshakeThese specifications describe the three DMA handshake modes.In all three modes DMAR is used to initiate transfers. For hand-shake mode, DMAG controls the latching or enabling of dataexternally. For external handshake mode, the data transfer iscontrolled by the ADDR31-0, RD, WR, SW, PAGE, MS3-0,ACK, and DMAG signals. For Paced Master mode, the data


–31–REV. B

CLKIN

tSDRLC

DMARx

DATA (FROMADSP-2106x TO

EXTERNAL DRIVE)

DATA (FROMEXTERNAL DRIVE

TO ADSP-2106x)

RD

WR

tWDR

tSDRHC

tDMARH

tDMARLL

tHDGC

tWDGH

tDDGLtWDGL

DMAGx

tVDATDGH

tDATDRH

tDATRDGH

tHDATIDG

tDGWRL tDGWRH tDGWRR

tDGRDL

tDRDGH

tDGRDR

tSDATDGL

* MEMORY READ – BUS MASTER, MEMORY WRITE – BUS MASTER, AND SYNCHRONOUS READ/WRITE – BUS MASTER TIMING SPECIFICATIONS FOR ADDR31-0, RD, WR, SW, MS3-0 AND ACK ALSO APPLY HERE.

(EXTERNAL DEVICETO EXTERNAL

MEMORY)

(EXTERNALMEMORY TO

EXTERNAL DEVICE)

TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE

TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)

tDDGHA

ADDRESSMSx, SW

tDADGH

Figure 20. DMA Handshake Timing

–32–


REV. B

Link Ports: 1 × CLK Speed Operation


ReceiveTiming Requirements:tSLDCL Data Setup before LCLK Low 3.5 3 nstHLDCL Data Hold after LCLK Low 3 3 nstLCLKIW LCLK Period (1 × Operation) tCK tCK nstLCLKRWL LCLK Width Low 6 6 nstLCLKRWH LCLK Width High 5 5 ns

Switching Characteristics:tDLAHC LACK High Delay after CLKIN High 18 + DT/2 28.5 + DT/2 18 + DT/2 28.5 + DT/2 nstDLALC LACK Low Delay after LCLK High1 –3 13 –3 13 nstENDLK LACK Enable from CLKIN 5 + DT/2 5 + DT/2 nstTDLK LACK Disable from CLKIN 20 + DT/2 20 + DT/2 ns

TransmitTiming Requirements:tSLACH LACK Setup before LCLK High 18 20 nstHLACH LACK Hold after LCLK High –7 –7 ns

Switching Characteristics:tDLCLK LCLK Delay after CLKIN (1 × operation) 15.5 16.5 nstDLDCH Data Delay after LCLK High 3 2.5 nstHLDCH Data Hold after LCLK High –3 –3 nstLCLKTWL LCLK Width Low (tCK/2) – 2 (tCK/2) + 2 (tCK/2) – 1 (tCK/2) + 1.25 nstLCLKTWH LCLK Width High (tCK/2) – 2 (tCK/2) + 2 (tCK/2) – 1.25 (tCK/2) + 1.0 nstDLACLK LCLK Low Delay after LACK High (tCK/2) + 8.5 (3 × tCK/2) + 17 (tCK/2) + 8.0 (3 × tCK/2) + 17.5 nstENDLK LDAT, LCLK Enable after CLKIN 5 + DT/2 5 + DT/2 nstTDLK LDAT, LCLK Disable after CLKIN 20 + DT/2 20 + DT/2 ns

Link Port Service Request Interrupts: 1 × and2 × Speed OperationsTiming Requirements:tSLCK LACK/LCLK Setup before CLKIN Low2 10 10 nstHLCK LACK/LCLK Hold after CLKIN Low2 2 2 ns

NOTES1LACK will go low with tDLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.2Only required for interrupt recognition in the current cycle.


–33–REV. B

Link Ports: 2 × CLK Speed OperationCalculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that canbe introduced in the transmission path between LDATA and LCLK. Setup skew is the maximum delay that can be introduced inLDATA relative to LCLK, (setup skew = tLCLKTWH min – tDLDCH – tSLDCL). Hold skew is the maximum delay that can be intro-duced in LCLK relative to LDATA, (hold skew = tLCLKTWL min – tHLDCH – tHLDCL). Calculations made directly from 2 × speedspecifications will result in unrealistically small skew times because they include multiple tester guardbands. The setup and hold skewtimes shown below are calculated to include only one tester guardband.

ADSP-21060 Setup Skew = 1.93 ns maxADSP-21060 Hold Skew = 2.95 ns max

ADSP-21060L Setup Skew = 1.87 ns maxADSP-21060L Hold Skew = 1.69 ns max


ReceiveTiming Requirements:tSLDCL Data Setup before LCLK Low 2.5 2.25 nstHLDCL Data Hold after LCLK Low 2.25 2.25 nstLCLKIW LCLK Period (2 × Operation) tCK/2 tCK/2 nstLCLKRWL LCLK Width Low 4.5 5.0 nstLCLKRWH LCLK Width High 4.25 4.0 ns

Switching Characteristics:tDLAHC LACK High Delay after CLKIN High 18 + DT/2 28.5 + DT/2 18 + DT/2 29.5 + DT/2 nstDLALC LACK Low Delay after LCLK High1 6 16 6 18 ns

TransmitTiming Requirements:tSLACH LACK Setup before LCLK High 19 19 nstHLACH LACK Hold after LCLK High –6.75 –6.5 ns

Switching Characteristics:tDLCLK LCLK Delay after CLKIN 8 8 nstDLDCH Data Delay after LCLK High 2.5 2.25 nstHLDCH Data Hold after LCLK High –2.0 –2.0 nstLCLKTWL LCLK Width Low (tCK/4) – 1 (tCK/4) + 1 (tCK/4) – 0.75 (tCK/4) + 1.5 nstLCLKTWH LCLK Width High (tCK/4) – 1 (tCK/4) + 1 (tCK/4) – 1.5 (tCK/4) + 1 nstDLACLK LCLK Low Delay after LACK High (tCK/4) + 9 (3 * tCK/4) + 16.5 (tCK/4) + 9 (3 * tCK/4) + 16.5 ns

NOTE1LACK will go low with tDLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.

–34–


REV. B

CLKIN

LCLKLDAT(3:0)

LACK

LCLK 1xOR

LCLK 2x

CLKIN

LDAT(3:0)

LACK (IN)

LCLK 1xOR

LCLK 2x

LDAT(3:0)

LACK (OUT)

THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.

CLKIN

TRANSMIT

tDLDCH

tHLDCH

tDLCLK

tLCLKTWH tLCLKTWL

tSLACH tHLACH

tDLACLK

tSLDCL

tHLDCL

tLCLKRWH

tDLAHC

tDLALC

LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.

tENDLKtTDLK

RECEIVE

LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION

tLCLKRWL

tLCLKIW

CLKIN

tSLCKtHLCK

LINK PORT INTERRUPT SETUP TIME

LCLK

LACK

LAST NIBBLETRANSMITTED

FIRST NIBBLETRANSMITTED

LCLK INACTIVE (HIGH)

OUT

IN

Figure 21. Link Ports


–35–REV. B

Serial Ports


External ClockTiming Requirements:tSFSE TFS/RFS Setup before TCLK/RCLK1 3.5 3.5 nstHFSE TFS/RFS Hold after TCLK/RCLK1, 2 4 4 nstSDRE Receive Data Setup before RCLK1 1.5 1.5 nstHDRE Receive Data Hold after RCLK1 4 4 nstSCLKW TCLK/RCLK Width 9.5 9.0 nstSCLK TCLK/RCLK Period tCK tCK ns

Internal ClockTiming Requirements:tSFSI TFS Setup before TCLK1; RFS Setup

before RCLK1 8 8 nstHFSI TFS/RFS Hold after TCLK/RCLK1, 2 1 1 nstSDRI Receive Data Setup before RCLK1 3 3 nstHDRI Receive Data Hold after RCLK1 3 3 nsExternal or Internal ClockSwitching Characteristics:tDFSE RFS Delay after RCLK (Internally

Generated RFS)3 13 13 nstHOFSE RFS Hold after RCLK (Internally

Generated RFS)3 3 3 ns

External ClockSwitching Characteristics:tDFSE TFS Delay after TCLK (Internally

Generated TFS)3 13 13 nstHOFSE TFS Hold after TCLK (Internally

Generated TFS)3 3 3 nstDDTE Transmit Data Delay after TCLK3 16 16 nstHODTE Transmit Data Hold after TCLK3 5 5 ns

Internal ClockSwitching Characteristics:tDFSI TFS Delay after TCLK (Internally

Generated TFS)3 4.5 4.5 nstHOFSI TFS Hold after TCLK (Internally

Generated TFS)3 –1.5 –1.5 nstDDTI Transmit Data Delay after TCLK3 7.5 7.5 nstHDTI Transmit Data Hold after TCLK3 0 0 nstSCLKIW TCLK/RCLK Width (tSCLK/2) – 2 (tSCLK/2) + 2 (tSCLK/2) – 2.5 (tSCLK/2) + 2.5 nsEnable and Three-StateSwitching Characteristics:tDDTEN Data Enable from External TCLK3 3.5 4.0 nstDDTTE Data Disable from External TCLK3 10.5 10.5 nstDDTIN Data Enable from Internal TCLK3 0 0 nstDDTTI Data Disable from Internal TCLK3 3 3 nstDCLK TCLK/RCLK Delay from CLKIN 22 + 3DT/8 22 + 3DT/8 nstDPTR SPORT Disable after CLKIN 17 17 ns

Gated SCLK with External TFS(Mesh Multiprocessing)4

Timing Requirements:tSTFSCK TFS Setup before CLKIN 5 5 nstHTFSCK TFS Hold after CLKIN tCK/2 tCK/2 ns

External Late Frame SyncSwitching Characteristics:tDDTLFSE Data Delay from Late External TFS or 12 12.8 ns

External RFS with MCE = 1, MFD = 05

tDDTENFS Data Enable from late FS or MCE = 1, MFD = 05 3 3.5 ns

To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay & frame sync setupand hold, 2) data delay & data setup and hold, and 3) SCLK width.

–36–


REV. B

NOTES1Referenced to sample edge.2RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.3Referenced to drive edge.4Applies only to gated serial clock mode used for serial port system I/O in mesh multiprocessing systems.5MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS.

DT

DT

tDDTTEtDDTEN

tDDTTI

tDDTIN

DRIVE EDGE DRIVE EDGE

DRIVEEDGE

DRIVEEDGE

TCLK / RCLKTCLK (INT)

TCLK / RCLKTCLK (EXT)

CLKIN

SPORT ENABLE ANDTHREE-STATELATENCYIS TWO CYCLES

tDPTR

SPORT DISABLE DELAYFROM INSTRUCTION

tDCLK

LOW TO HIGH ONLY

TCLK (INT)

RCLK (INT)

TCLK, RCLK

TFS, RFS, DT

CLKIN

TFS (EXT)

tHTFSCKtSTFSCK

NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITHEXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FORMESH MULTIPROCESSING.

tSDRI

RCLK

RFS

DR

DRIVEEDGE

SAMPLEEDGE

tHDRI

tSFSI tHFSI

tDFSEtHOFSE

tSCLKIW

DATA RECEIVE– INTERNAL CLOCK

tSDRE

DATA RECEIVE– EXTERNAL CLOCK

RCLK

RFS

DR

DRIVEEDGE

SAMPLEEDGE

tHDRE

tSFSE tHFSE

tDFSE

tSCLKW

tHOFSE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

tDDTItHDTI

TCLK

TFS

DT

DRIVEEDGE

SAMPLEEDGE

tSFSI tHFSI

tSCLKIW

tDFSItHOFSI

tDDTEtHDTE

TCLK

TFS

DT

DRIVEEDGE

SAMPLEEDGE

tSFSE tHFSE

tDFSE

tSCLKW

tHOFSE

DATA TRANSMIT– INTERNAL CLOCK DATA TRANSMIT– EXTERNAL CLOCK

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

Figure 22. Serial Ports


–37–REV. B

tHOFSE/I

tSFSE/I

(SEE NOTE 2)

DRIVE SAMPLE DRIVE

tDDTE/I

tDDTENFS

tDDTLFSE

tHDTE/I

TCLK

tHOFSE/I

tSFSE/I

TFS

DT

DRIVE SAMPLE DRIVE

tDDTE/I tDDTENFS

tDDTLFSE

tHDTE/I

LATE EXTERNAL TFS

EXTERNAL RFS with MCE = 1, MFD = 0

1ST BIT 2ND BITDT

RCLK

RFS

1ST BIT 2ND BIT

(SEE NOTE 2)

Figure 23. External Late Frame Sync

–38–


REV. B

JTAG Test Access Port and Emulation


Timing Requirements:tTCK TCK Period tCK tCK nstSTAP TDI, TMS Setup before TCK High 5 5 nstHTAP TDI, TMS Hold after TCK High 6 6 nstSSYS System Inputs Setup before TCK Low1 7 7 nstHSYS System Inputs Hold after TCK Low1 18 18.5 nstTRSTW TRST Pulsewidth 4tCK 4tCK ns

Switching Characteristics:tDTDO TDO Delay from TCK Low 13 13 nstDSYS System Outputs Delay after TCK Low2 18.5 18.5 ns

NOTES1System Inputs = DATA47-0, ADDR31-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR6-1, ID2-0, RPBA, IRQ2-0, FLAG3-0, DR0, DR1,TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET.

2System Outputs = DATA47-0, ADDR31-0, MS3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR6-1, CPA, FLAG3-0, TIMEXP, DT0,DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, BMS.

TCK

tSTAP

tTCK

tHTAP

tDTDO

tSSYS tHSYS

tDSYS

TMSTDI

TDO

SYSTEMINPUTS

SYSTEMOUTPUTS

Figure 24. IEEE 11499.1 JTAG Test Access Port


–39–REV. B

Table III. External Power Calculations (3.3 V Device)

Pin # of %Type Pins Switching 3 C 3 f 3 VDD

2 = PEXT

Address 15 50 × 44.7 pF × 10 MHz × 10.9 V = 0.037 WMS0 1 0 × 44.7 pF × 10 MHz × 10.9 V = 0.000 WWR 1 – × 44.7 pF × 20 MHz × 10.9 V = 0.010 WData 32 50 × 14.7 pF × 10 MHz × 10.9 V = 0.026 WADDRCLK 1 – × 4.7 pF × 20 MHz × 10.9 V = 0.001 W

PEXT = 0.074 W

A typical power consumption can now be calculated for theseconditions by adding a typical internal power dissipation:

PTOTAL = PEXT + (IDDIN2 × 5.0 V )

Note that the conditions causing a worst-case PEXT are differentfrom those causing a worst-case PINT. Maximum PINT cannotoccur while 100% of the output pins are switching from all onesto all zeros. Note also that it is not common for an application tohave 100% or even 50% of the outputs switching simultaneously.

TEST CONDITIONSOutput Disable TimeOutput pins are considered to be disabled when they stop driv-ing, go into a high impedance state, and start to decay fromtheir output high or low voltage. The time for the voltage on thebus to decay by ∆V is dependent on the capacitive load, CL andthe load current, IL. This decay time can be approximated bythe following equation:

tDECAY =

CL ∆VIL

The output disable time tDIS is the difference between tMEASUREDand tDECAY as shown in Figure 25. The time tMEASURED is theinterval from when the reference signal switches to when theoutput voltage decays ∆V from the measured output high oroutput low voltage. tDECAY is calculated with test loads CL andIL, and with ∆V equal to 0.5 V.

Output Enable TimeOutput pins are considered to be enabled when they have madea transition from a high impedance state to when they startdriving. The output enable time tENA is the interval from when areference signal reaches a high or low voltage level to when theoutput has reached a specified high or low trip point, as shownin the Output Enable/Disable diagram (Figure 25). If multiplepins (such as the data bus) are enabled, the measurement valueis that of the first pin to start driving.

OUTPUT DRIVE CURRENTSFigure 28 shows typical I-V characteristics for the output driversof the ADSP-2106x. The curves represent the current drivecapability of the output drivers as a function of output voltage.

POWER DISSIPATIONTotal power dissipation has two components, one due to inter-nal circuitry and one due to the switching of external outputdrivers. Internal power dissipation is dependent on the instruc-tion execution sequence and the data operands involved. Inter-nal power dissipation is calculated in the following way:

PINT = IDDIN × VDD

The external component of total power dissipation is caused bythe switching of output pins. Its magnitude depends on:

– the number of output pins that switch during each cycle (O)– the maximum frequency at which they can switch (f)– their load capacitance (C)– their voltage swing (VDD)

and is calculated by:

PEXT = O × C × VDD2 × f

The load capacitance should include the processor’s packagecapacitance (CIN). The switching frequency includes driving theload high and then back low. Address and data pins can drivehigh and low at a maximum rate of 1/(2tCK). The write strobecan switch every cycle at a frequency of 1/tCK. Select pins switchat 1/(2tCK), but selects can switch on each cycle.

Example:

Estimate PEXT with the following assumptions:

–A system with one bank of external data memory RAM (32-bit)–Four 128K × 8 RAM chips are used, each with a load of 10 pF–External data memory writes occur every other cycle, a rateof 1/(4tCK), with 50% of the pins switching

–The instruction cycle rate is 40 MHz (tCK = 25 ns).

The PEXT equation is calculated for each class of pins that candrive:

Table II. External Power Calculations (5 V Device)

Pin # of %Type Pins Switching 3 C 3 f 3 VDD

2 = PEXT

Address 15 50 × 44.7 pF × 10 MHz × 25 V = 0.084 WMS0 1 0 × 44.7 pF × 10 MHz × 25 V = 0.000 WWR 1 – × 44.7 pF × 20 MHz × 25 V = 0.022 WData 32 50 × 14.7 pF × 10 MHz × 25 V = 0.059 WADDRCLK 1 – × 4.7 pF × 20 MHz × 25 V = 0.002 W

PEXT = 0.167 W

–40–


REV. B

Example System Hold Time CalculationTo determine the data output hold time in a particular system,first calculate tDECAY using the equation given above. Choose ∆Vto be the difference between the ADSP-2106x’s output voltageand the input threshold for the device requiring the hold time. Atypical ∆V will be 0.4 V. CL is the total bus capacitance (perdata line), and IL is the total leakage or three-state current (perdata line). The hold time will be tDECAY plus the minimumdisable time (i.e., tDATRWH for the write cycle).

REFERENCESIGNAL

tDIS

OUTPUT STARTSDRIVING

VOH (MEASURED) – DV

VOL (MEASURED) + DV

tMEASURED

VOH (MEASURED)

VOL (MEASURED)

2.0V

1.0V

VOH (MEASURED)

VOL (MEASURED)

HIGH-IMPEDANCE STATE.TEST CONDITIONS CAUSETHIS VOLTAGE TO BEAPPROXIMATELY 1.5V

OUTPUT STOPSDRIVING

tENA

tDECAY

Figure 25. Output Enable/Disable

+1.5V

50pF

TOOUTPUT

PIN

IOL

IOH

Figure 26. Equivalent Device Loading for AC Measure-ments (Includes All Fixtures)

INPUT OROUTPUT 1.5V1.5V

Figure 27. Voltage Reference Levels for AC Measure-ments (Except Output Enable/Disable)

Capacitive LoadingOutput delays and holds are based on standard capacitive loads:50 pF on all pins (see Figure 26). The delay and hold specifica-tions given should be derated by a factor of 1.5 ns/50 pF forloads other than the nominal value of 50 pF. Figures 29–30,33–34 show how output rise time varies with capacitance. Fig-ures 31, 35 show graphically how output delays and holds varywith load capacitance. (Note that this graph or derating doesnot apply to output disable delays; see the previous sectionOutput Disable Time under Test Conditions.) The graphs ofFigures 29, 30 and 31 may not be linear outside the rangesshown.


–41–REV. B

SOURCE VOLTAGE – V

100

–75

–150

0 5.25

SO

UR

CE

CU

RR

EN

T –

mA

0.75 1.50 2.25 3.00 3.75 4.50

75

–50

–100

–125

25

–25

50

0

–175

–200

4.75V, +85°C

5.0V, +25°C 5.25V, –40°C

4.75V, +85°C

5.0V, +25°C

5.25V, –408C

Figure 28. ADSP-2106x Typical Drive Currents (VDD = 5 V)

LOAD CAPACITANCE – pF

16.0

8.0

00 20020 40 60 80 100 120 140 160 180

14.0

12.0

4.0

2.0

10.0

6.0 FALL TIME

RISE TIME

RIS

E A

ND

FA

LL T

IME

S –

ns

(0.5

V –

4.5

V, 1

0% –

90%

)

Y = 0.005X + 3.7

Y = 0.0031X + 1.1

Figure 29. Typical Output Rise Time (10%–90% VDD) vs.Load Capacitance (VDD = 5 V)

3.5

0

RIS

E A

ND

FA

LL T

IME

S –

ns

(0.8

V –

2.0

V)

3.0

2.5

2.0

1.5

1.0

0.5

LOAD CAPACITANCE – pF0 20020 40 60 80 100 120 140 160 180

FALL TIME

RISE TIME

Y = 0.009X + 1.1

Y = 0.005X + 0.6

Figure 30. Typical Output Rise Time (0.8 V–2.0 V) vs.Load Capacitance (VDD = 5 V)


OU

TP

UT

DE

LAY

OR

HO

LD –

ns

5

–125 20050 75 100 125 150 175

4

3

2

1

NOMINAL

Y = 0.03X –1.45

Figure 31. Typical Output Delay or Hold vs. Load Capaci-tance (at Maximum Case Temperature) (VDD = 5 V)

SOURCE VOLTAGE – V

120

–20

–80

0 3.5

SO

UR

CE

CU

RR

EN

T –

mA

0.5 1 1.5 2 2.5 3

100

0

–40

–60

60

20

80

40

–100

–120

3.0V, +85°C3.3V, +25°C

3.6V, –40°C

3.6V, –40°C

3.3V, +25°C

3.0V, +858CVOH

VOL

Figure 32. ADSP-2106x Typical Drive Currents (VDD = 3.3 V)


0

2

020 40 60 80 100 120

Y = 0.0796X + 1.17

Y = 0.0467X + 0.55

RISE TIME

FALL TIME

140 160 180 200

4

6

8

10

12

14

16

18

RIS

E A

ND

FA

LL T

IME

S –

ns

(10%

– 9

0%)

Figure 33. Typical Output Rise Time (10%–90% VDD) vs.Load Capacitance (VDD = 3.3 V)

–42–


REV. B


00

20 40 60 80 100 120

Y = 0.0391X + 0.36

Y = 0.0305X + 0.24RISE TIME

FALL TIME

140 160 180 200

RIS

E A

ND

FA

LL T

IME

S –

ns

(0.8

V –

2.0

V)

1

2

3

4

5

6

7

8

9

Figure 34. Typical Output Rise Time (0.8 V–2.0 V) vs.Load Capacitance (VDD = 3.3 V)

ENVIRONMENTAL CONDITIONSThermal CharacteristicsThe ADSP-2106x is packaged in a 240-lead thermally enhancedPQFP. The top surface of the package contains a copper slugfrom which most of the die heat is dissipated. The slug is flushwith the top surface of the package. Note that the copper slug isinternally connected to GND through the device substrate.The ADSP-2106x is specified for a case temperature (TCASE).To ensure that the TCASE data sheet specification is not ex-ceeded, a heatsink and/or an air flow source may be used. Aheatsink should be attached with a thermal adhesive.

TCASE = TAMB + ( PD × θCA )

TCASE = Case temperature (measured on top surface of package)PD = Power dissipation in W (this value depends upon the

specific application; a method for calculating PD isshown under Power Dissipation).

θCA = Value from table below.

Airflow(Linear Ft./Min.) 0 100 200 400 600

θCA (°C/W) 10 9 8 7 6

NOTESThis represents thermal resistance at total power of 5 W.With air flow, no variance is seen in θCA with power.θCA at 0 LFM varies with power: at 2W, θCA = 14°C/W, at 3 W θCA = 11°C/W.θJC = 0.3°C/W.


OU

TP

UT

DE

LAY

OR

HO

LD –

ns

5

–125 20050 75 100 125 150 175

4

3

2

1

NOMINAL

Y = 0.0329X –1.65

Figure 35. Typical Output Delay or Hold vs. Load Capaci-tance (at Maximum Case Temperature) (VDD = 3.3 V)


–43–REV. B

240-LEAD METRIC PQFP PIN CONFIGURATIONS

1

240

60

61 120

121

180

181

TOP VIEW

HEATSLUG

GND

THE 240–LEAD PACKAGE CONTAINS A COPPER HEAT SLUG FLUSH WITHITS TOP SURFACE. THE SLUG IS INTERNALLY CONNECTED TO GROUND.

Pin PinNo. Name

1 TDI2 TRST3 VDD4 TDO5 TIMEXP6 EMU7 ICSA8 FLAG39 FLAG210 FLAG111 FLAG012 GND13 ADDR014 ADDR115 VDD16 ADDR217 ADDR318 ADDR419 GND20 ADDR521 ADDR622 ADDR723 VDD24 ADDR825 ADDR926 ADDR1027 GND28 ADDR1129 ADDR1230 ADDR1331 VDD32 ADDR1433 ADDR1534 GND35 ADDR1636 ADDR1737 ADDR1838 VDD39 VDD40 ADDR19

Pin PinNo. Name

121 DATA41122 DATA40123 DATA39124 VDD125 DATA38126 DATA37127 DATA36128 GND129 NC130 DATA35131 DATA34132 DATA33133 VDD134 VDD135 GND136 DATA32137 DATA31138 DATA30139 GND140 DATA29141 DATA28142 DATA27143 VDD144 VDD145 DATA26146 DATA25147 DATA24148 GND149 DATA23150 DATA22151 DATA21152 VDD153 DATA20154 DATA19155 DATA18156 GND157 DATA17158 DATA16159 DATA15160 VDD

Pin PinNo. Name

81 TCLK082 TFS083 DR084 RCLK085 RFS086 VDD87 VDD88 GND89 ADRCLK90 REDY91 HBG92 CS93 RD94 WR95 GND96 VDD97 GND98 CLKIN99 ACK100 DMAG2101 DMAG1102 PAGE103 VDD104 BR6105 BR5106 BR4107 BR3108 BR2109 BR1110 GND111 VDD112 GND113 DATA47114 DATA46115 DATA45116 VDD117 DATA44118 DATA43119 DATA42120 GND

Pin PinNo. Name

201 L2DAT0202 L2CLK203 L2ACK204 NC205 VDD206 L3DAT3207 L3DAT2208 L3DAT1209 L3DAT0210 L3CLK211 L3ACK212 GND213 L4DAT3214 L4DAT2215 L4DAT1216 L4DAT0217 L4CLK218 L4ACK219 VDD220 GND221 VDD222 L5DAT3223 L5DAT2224 L5DAT1225 L5DAT0226 L5CLK227 L5ACK228 GND229 ID2230 ID1231 ID0232 LBOOT233 RPBA234 RESET235 EBOOT236 IRQ2237 IRQ1238 IRQ0239 TCK240 TMS

Pin PinNo. Name

161 DATA14162 DATA13163 DATA12164 GND165 DATA11166 DATA10167 DATA9168 VDD169 DATA8170 DATA7171 DATA6172 GND173 DATA5174 DATA4175 DATA3176 VDD177 DATA2178 DATA1179 DATA0180 GND181 GND182 L0DAT3183 L0DAT2184 L0DAT1185 L0DAT0186 L0CLK187 L0ACK188 VDD189 L1DAT3190 L1DAT2191 L1DAT1192 L1DAT0193 L1CLK194 L1ACK195 GND196 GND197 VDD198 L2DAT3199 L2DAT2200 L2DAT1

Pin PinNo. Name

41 ADDR2042 ADDR2143 GND44 ADDR2245 ADDR2346 ADDR2447 VDD48 GND49 VDD50 ADDR2551 ADDR2652 ADDR2753 GND54 MS355 MS256 MS157 MS058 SW59 BMS60 ADDR2861 GND62 VDD63 VDD64 ADDR2965 ADDR3066 ADDR3167 GND68 SBTS69 DMAR270 DMAR171 HBR72 DT173 TCLK174 TFS175 DR176 RCLK177 RFS178 GND79 CPA80 DT0

–44–


REV. B

PACKAGE DIMENSIONSDimensions shown in inches and (mm).

240-Lead Metric PQFP

1

181

180

121

12061

60

GND

HEATSLUG

THE THERMALLY ENHANCED PQFP PACKAGE CONTAINS ACOPPER HEAT SLUG FLUSH WITH ITS TOP SURFACE; THESLUG IS INTERNALLY CONNECTED TO GROUND. THE HEATSLUG DIAMETER IS 24.1 (0.949) mm.

240–LEAD METRIC PQFPTOP VIEW (PINS DOWN)

1.372 (34.85) 1.362 (34.60) TYP SQ 1.352 (34.35) 1.264 (32.10) 1.260 (32.00) TYP SQ 1.256 (31.90) 1.165 (29.60) 1.161 (29.50) TYP SQ 1.157 (29.40)

240

INCHES (MILLIMETERS)

SEATINGPLANE

0.161 (4.10)MAX

0.030 (0.75) 0.024 (0.60) TYP 0.020 (0.50)

0.004 (0.10)MAX

0.010 (0.25)MIN

0.138 (3.50) 0.134 (3.40) TYP 0.130 (3.30)

0.011 (0.27) 0.009 (0.22) TYP 0.007 (0.17)

LEAD PITCH0.01969 (0.50)

TYP

LEAD WIDTH

NOTE:THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08)0.0032 FROM ITS IDEAL POSITION WHEN MEASURED IN THELATERAL DIRECTION.CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED

ORDERING GUIDE

Part Number Case Temperature Range Instruction Rate On-Chip SRAM Operating Voltage

ADSP-21060KS-133 0°C to +85°C 33 MHz 4 Mbit 5 VADSP-21060KS-160 0°C to +85°C 40 MHz 4 Mbit 5 VADSP-21060LKS-133 0°C to +85°C 33 MHz 4 Mbit 3.3 VADSP-21060LKS-160 0°C to +85°C 40 MHz 4 Mbit 3.3 V

NOTES1. These parts are packaged in a 240-lead, thermally enhanced Plastic Quad Flatpack (PQFP).2. Parts for the industrial and military temperature ranges will be available in 1998.

C31

65–4

–4/9

8P

RIN

TE

D IN

U.S

.A.

a DSP Microcomputer Family ADSP-2106x SHARC ADSP-21060 ...

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