A configurable Interlock System for RF-Stations at XFEL M.Penno, T. Grevsmühl, H.Leich, A. Kretzschmann W.Köhler, B. Petrosyan, G.Trowitzsch, R.Wenndorff
Jan 17, 2016
A configurable Interlock System for RF-Stations at XFEL
M.Penno, T. Grevsmühl, H.Leich, A. KretzschmannW.Köhler, B. Petrosyan, G.Trowitzsch, R.Wenndorff
Page 2A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
• XFEL European X-ray free-electron laser project• opens many possibilities for research with short
wave length x-rays (below 1 nm)• start of construction 2007• initial operation 2012• requires 33 ... 40
RF-Stations for theaccelerator sections based on super-conducting cavities
European XFEL-Project
Page 3A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Content
• Interlock Concept
• Interlock Hardware
• Software for the Interlock
Page 4A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Main Task of the RF-Interlock-System
• Prevent any damage from the cost expensive components of the RF-Station
• Prevent also any damage from other equipment
• Support secure operation of the RF-System
Page 5A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Sources of Interlock Error Signals
• Hardware failures (non-reversible malfunctions)– broken cable or damaged contact, dead sensor,...
• Soft errors (reversible error conditions)– sparks in the klystron or wave guide system– temperature outside a valid range, ...
• Error conditions caused by transient noise from the RF-Station itself
Page 6A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Qualities of the XFEL Interlock System
• Configurable and scaleable System
• Modular structured
• Interlock functionality independend from software
• Support of different signal types– digital, LWL, analog inputs and outputs
• Selftest and reliability check on power up
Page 7A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Interlock3 architecture overview
- interlock function completely implemented in hardware- Strict separation of interlock logic and processor bus
InterlockController
Processor Bus, Interrupts and Other
Interlock Logicin pure hardware
Slave I/OModule
Slave ExpansionBoard
(optional)
Slave I/OModule
...
SoftcoreRISC Processor
NIOS-II
Output Control Signals
Input Status Signals
Backplane
BackplaneBackp
lane
Backp
lane
Page 8A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Control-Bus Interface
Service Requests
IndividualModule Logic
Time Multiplex Bus
Interlock Direct I/O Output Control Signals
Input Status Signals
FPGAInterlockModule
Module InputHardware
Module OutputHardware
Output Control Signals
Input Status Signals
Control-Bus InterfaceLogic
Common ModuleInterface
ID ROMEPCS
InterfaceInterlockStatus
EPCS Flash
Backplane Co
mp
on
ents o
f the R
F-S
ystem
Interlock3 Module Architecture
Page 9A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Interlock3 Controller Architecture
Inte
rn B
us
SoftcoreNIOS2 32-Bit RISC
Processor(full featured)
Control-Bus Interface
SDRAM32 MBytes
Flash Memory16 MB
MRAM
Temperatur Sensor
InterlockConfig
Systest LogicE
xter
n B
us
RS232 Interface
Service Requests
Bus WriteProtection
Ethernet Controller
SPIInterface
MMCInterface
FPGAInterlockController
Backplane
Interlock Logic
Status MaskROM
ProtectionMask
Time Multiplex Bus
Interlock Direct I/OOutput Control Signals
Input Status Signals
Direct connection
Bus
Interlock Signals
Legend
Page 10A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Content
• Interlock Concept
• Interlock Hardware
• Software for the Interlock
Page 11A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Interlock Crate
Distribution Panels
- 19`` 3HU crate
- 20 slots for slave modules
Slave Modules
InterlockController
• provides many signal connections• distribution panels connect the interlock crate with incoming and outgoing signal cables
easy access to all signal cableseasy module exchange
Page 12A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Components of the Interlock System
• Controller Module– NIOS II Processor, 64MB RAM, 16MB Flash– Ethernet Interface
• Slave Modules– Digital I/O, 32 input, 8 output channels– Analog window comparator, 36 input channels– Light I/O, 6 input, 6 output channels, – Analog I/O, 8 input, output channels
• Backplane, power supply
Page 13A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Interlock Modules
Page 14A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
NIOS/II Experiences
easy scaleable by Altera SOPC-Builder
good IDE integration and development flow
close to hardware development
no Memory Management Unit (MMU) not suitable for our software project software errors hard to find
strange behavior with LWIP-Stack and µC/OS on our board
fixing errors is very time consuming
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Planned future development
• move on-board applications from NIOS/II to another platform
• shrink on-board applications on NIOS/II side• put computer-on-board module on intlk.-controller
(f.ex. x86-architecture, X-Board) • use Linux as operating system
•AMD Geode SC1200 CPU 266 MHz •Up to 128MB RAM / 128MB Flash on board •Integrated video controller with up to 4MB DRAM •Power consumption 3-4Watts •On board 10/100MBit Ethernet •IDE interface with UDMA-33 support •PCI and LPC expansion busses •3 USB 1.1 ports OHCI •2 serial interfaces (TTL signals)
Page 16A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Interlock Controller Architecture with X-Board
Inte
rn B
us
SoftcoreNIOS2 32-Bit RISC
Processor
Control-Bus Interface
SDRAM32 MBytes
EPCS Flash Memory
Temperatur Sensor
InterlockConfig
Systest Logic
RS232 Interface
Service Requests
Bus WriteProtection
Ethernet Interface
SPIInterface
FPGAInterlockController
Backplane
Interlock Logic
Status MaskROM
ProtectionMask
Time Multiplex Bus
Interlock Direct I/OOutput Control Signals
Input Status Signals
X-BoardGeode AMD x86
266 MHz, 128MB RAM
running TINEon LINUX
LPC Bus
Compact FlashInterface
USB Interface
Page 17A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Content
• Interlock Concept
• Interlock Hardware
• Software for the Interlock
Page 18A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Software capabilities
• Perform system-selftest at power-up
• Offer access over intranet via browser
• Access secured by authentication
• Display signal status and change signal mask
• Special mode for updating firmware and FPGA design
Page 19A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Klystron Interlock Server - Architecture
Altera HAL
Interlock Backend (module drivers and subsystems)
HTTP ServerUDP Interfaceto DOOCS
UDP Interfaceto LabVIEW
µC/OS II with LWIP
Client applications
Interlock controller and slave modules
ControllInterlockStatus
System Test
Ba
cke
nd
Ap
plic
atio
n L
aye
r
ManageInterlock
Configuration
UpdateFirmware
Page 20A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
System-Test
• runs on power-up• System-selftest checks:
1. controller
2. backplane
3. TM-bus, control-bus
4. modules
5. FPGA design compatibility
6. module configuration
• System-selftest must not fail, to put interlock system into operation mode
Page 21A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
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Interlock HTTP Interface
- display actual signal states
- edit signal-masks- edit interlock
configuration
Page 22A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Klystron Interlock Server
• server runs on the controller, NIOS/II processor• web-interface, access via browser
Page 23A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Access Privileges
- User authentification- Different User Roles (chief engineer, engineer, technician)- IP-Address check , 2 addresses possible
Page 24A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Client Applications - Overview
- DOOCS Interface for viewing state
-Integration into the control-system
- Tools under LabVIEW
-Detailed error diagnostics
Page 25A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Interlock to DOOCS - Interface
• Interlock sends actual status data to Metaserver
• Metaserver integrates status-data into DOOCS-System and history
• Clients monitor signal states
DOOCS
HTMLBrowser
LabVIEWTools
Network
Interlock Crate
DOOCSMetaserver
DOOCS System
Clients
Page 26A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Interlock to LabVIEW - Interface
• used for diagnostic• view detailed information
about interlock signals• store highly detailed data into
database for later diagnostic• very helpful on resolving
errors
LabVIEW Tools
HTMLBrowser
InterlockData-Recorder
Network
Interlock Crate
DOOCS
NI DatasocketServer
Actual DataViewer
History DataViewer
DB
Page 27A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Diagnostic with LabVIEW
Diagnostic overview of all status signals
Time graph of status signals
Page 28A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Viewing Timegraph Curves
RF-Station working
RF-Stationpaused
Page 29A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Example: Help with cable diagnose
Noise impulses
Select Curves
working on cables
noise removed
Page 30A configurable Interlock System for RF-Stations at XFEL28. Nov., Tech. Seminar
Marek Penno, DESY
Summary
• Highly flexible Interlock System for XFEL
• Interlock-function implemented in hardware
• Process many signals with different types
• Signals can be masked
• Updateable firmware over intranet
• High connectivity to other applications– DOOCS, LabVIEW, HTML-Browser
Thank you for your attention!