A compact rail-to-rail CMOS buffer amplifier with very low quiescent current

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A compact rail-to-rail CMOS bufferamplifier with very low quiescentcurrentEmre Arslana, Merih Yıldızb & Shahram Minaeib

a Department of Electrical and Electronics Engineering, MarmaraUniversity, Goztepe, 34722 Kadikoy, Istanbul, Turkeyb Department of Electronics and Communications Engineering,Dogus University, Acibadem, 34722 Kadikoy, Istanbul, TurkeyAccepted author version posted online: 24 Jul 2014.Publishedonline: 12 Aug 2014.

To cite this article: Emre Arslan, Merih Yıldız & Shahram Minaei (2015) A compact rail-to-railCMOS buffer amplifier with very low quiescent current, International Journal of Electronics, 102:6,982-992, DOI: 10.1080/00207217.2014.947637

To link to this article: http://dx.doi.org/10.1080/00207217.2014.947637

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A compact rail-to-rail CMOS buffer amplifier with very low quiescentcurrent

Emre Arslana, Merih Yıldızb and Shahram Minaeib*

aDepartment of Electrical and Electronics Engineering, Marmara University, Goztepe, 34722Kadikoy, Istanbul, Turkey; bDepartment of Electronics and Communications Engineering, Dogus

University, Acibadem, 34722 Kadikoy, Istanbul, Turkey

(Received 24 August 2013; accepted 1 March 2014)

In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystaldisplay (LCD) applications is proposed. Compared to other buffer amplifiers, theproposed circuit has a very simple architecture, occupies a small number of transistorsand also has a large driving capacity with very low quiescent current. It is composed oftwo complementary differential input stages to provide rail-to-rail driving capacity. Thepush–pull transistors are directly connected to the differential input stage, and theoutput is taken from an inverter. The proposed buffer circuit is laid out using MentorGraphics IC Station layout editor using AMS 0.35 μm process parameters. It is shownby post-layout simulations that the proposed buffer can drive a 1 nF capacitive loadwithin a small settling time under a full voltage swing, while drawing only 1.6 μAquiescent current from a 3.3 V power supply.

Keywords: liquid crystal display; buffer amplifier; rail-to-rail; settling time; slew rate;quiescent current

1. Introduction

Liquid crystal displays (LCDs) have been widely used in electronics industry in consumerelectronics, communication and computers. For the LCDs used in mobile devices, powerconsumption is the major requirement. An LCD driver consists of column drivers, gatedrivers, a controller and a reference source. Column driver is usually called bufferamplifier and is the main block of the LCD driver systems. As the speed capability andpower consumption of the LCD block mainly depend on the buffer amplifier, this topic isthe major subject of many papers. There are many different buffer amplifier designsproposed in literature (Itakura & Minamizaki, 2002; Itakura, Minamizaki, Saito, &Kuroda, 2003; Ito, Itakura, & Minamizaki, 2007; Lu, 2004, 2009; Lu & Hsiao, 2011;Lu & Hsu, 2004; Lu & Lee, 2002; Lu & Xiao, 2006; Marano, Palumbo, & Pennisi, 2010a,2010b; Wang et al., 2007; Weng & Wu, 2002; Yıldız, Minaei, & Arslan, 2011; Yu & Wu,1999). An NMOS input class-A differential amplifier has a large charge capacity but poordischarge and vice versa for a PMOS input differential amplifier. So traditional bufferamplifiers use class-AB or class-B buffer amplifiers instead of class-A amplifiers (Lu &Hsu, 2004). In addition, it is also known that class-A amplifiers usually consume morestatic power than class-AB and class-B amplifiers. Especially to reduce the powerconsumption, class-B output buffer amplifiers are used (Yu & Wu, 1999), but this designprocess gives rise to larger die area because of the larger output transistors. In addition, the

*Corresponding author. Email: [email protected]

International Journal of Electronics, 2015Vol. 102, No. 6, 982–992, http://dx.doi.org/10.1080/00207217.2014.947637

© 2014 Taylor & Francis

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settling time is not effective to drive larger LCD panels. To reduce the settling time andpower consumption, class-AB output buffer amplifiers, using reduced current paths, areproposed (Ito et al., 2007). A rail-to-rail class-AB buffer amplifier concerning offsetcancellation is proposed in Lu (2009), which uses dual single-ended amplifier to drivelow-output impedance devices. Another class-AB buffer amplifier, which uses comparatorcircuit to sense the transient changes in the input, achieves good settling time but drivestoo much quiescent current (Lu & Lee, 2002). A different topology using a comparator atthe output stage of the buffer amplifier is given in Weng and Wu (2002). In this circuit,class-B operating principle is also used. Although the circuit is working rail-to-rail andhas a small quiescent current, it still has high settling time. In Itakura and Minamizaki(2002) and Itakura et al. (2003), some improvements have been done for their quiescentcurrent. Although their load capacitances are as small as 170 nF, they still have similarsettling time values with Weng and Wu (2002). A rail-to-rail class-B buffer amplifierusing a compensation resistor connected between the two output stages is proposed in Lu(2004). In this circuit, two output stages operate as comparators which improve thesensing time of the input transient signal, and as a result, the circuit will have a bettersettling time performance. But the disadvantage of this circuit is to have too manytransistors causing a large die area. Another class-B buffer amplifier using a doublecascade current mirror in the differential pairs of the input stage is given in Lu andXiao (2006). This configuration has a self-biasing scheme, which brings a limited range ofsupply voltage. A low-power high-slew rate class-AB buffer amplifier for LCD drivers ispresented in Wang et al. (2007) and Marano et al. (2010b). Although some improvementhas been done for their settling time performance in these circuits, they still suffer fromhigh quiescent current. A new compact low-power high-speed rail-to-rail class-B bufferamplifier for LCD applications reported in Marano et al. (2010a) has a better quiescentcurrent and settling time performance, but it still needs extra quiescent current from thepower supply. A high-speed rail-to-rail buffer amplifier using two complementary com-mon-source amplifiers and complementary push–pull transistors as an output is given inLu and Hsiao (2011). The circuit has an improved settling time, but it has too manytransistors. A high-slew rate rail-to-rail buffer amplifier using a positive feedback in thecomparators used in the output stage is published in Yıldız et al. (2011). Although thecircuit has a very good performance on settling time, it still consumes much quiescentcurrent from the supply.

All the previous works (Itakura & Minamizaki, 2002; Itakura et al., 2003; Lu, 2004;Lu & Hsiao, 2011; Lu & Lee, 2002; Lu & Xiao, 2006; Marano et al., 2010a, 2010b; Wanget al., 2007; Weng & Wu, 2002; Yıldız et al., 2011) presented in literature can beimproved in major parameters such as settling time and quiescent current. In this paper,a new rail-to-rail CMOS buffer amplifier is presented which occupies a small number oftransistors and has a large driving capacity with very low quiescent current. The paper isorganised as follows. The proposed circuit is explained in Section 2. Simulation results aregiven in Section 3. Finally, Section 4 concludes the paper with a comparison table of thepervious works to show the performance of the proposed buffer amplifier.

2. The proposed circuit

The block diagram of the proposed buffer amplifier is given in Figure 1. The circuit ismainly composed of a rail-to-rail input differential stage and an output stage including aninverter. The circuit implementation of the proposed amplifier is illustrated in Figure 2. Inthis circuit, the transistors M13–M16 constitute the proper biasing for the rail-to-rail

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differential input stage. To provide a rail-to-rail operation, the NMOS transistors M3 andM6 and PMOS transistors M4 and M5 are used as differential inputs. As a unity gainamplifier, the output is connected to the inverting input and the input signal is appliedfrom the non-inverting terminal. When there is no input signal in the input terminal, theinput and the output voltages are the same. If the bias current supplied by the transistorsM13 and M14 is I, then the transistors M3 (M4) and M6 (M5) draw I/2. The workingprinciple of the circuit can be explained as follows. When the non-inverting terminal (Vin)of the buffer amplifier increases by ΔVi, the current of the transistor M3 increases and thecurrent of the transistor M4 decreases (Yıldız et al., 2011). The current change in thetransistor will affect the currents of M7 and M8 with the same way. The decrement in thecurrent of M8 will cause the increase at drain voltage of M8 which will give rise to nearzero volts at the input of the inverter (M11, M12). So the load capacitance will charge fromthe transistor M11. The similar operation is also valid for the input terminal when the inputvoltage (Vin) decreases. In many buffer amplifier topologies, rail-to-rail differential inputstage output is connected to the output push–pull transistors with a comparator. However,in the proposed buffer amplifier, the push–pull transistors are directly connected to the

out

Mp

Mn

VDD

Rail-to-railop-amp

in

Figure 1. Block diagram of the rail-to-rail buffer amplifier.

M9 M11

M12M10M8

M6

M2

M13

M1

M15

M16 M14

M7

M3

M4 M5

VDD

Vbias

outB

Á

A

in

Figure 2. Circuit schematic of the proposed compact low-quiescent current rail-to-rail bufferamplifier.

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differential input stage, and the output terminal is taken from an inverter as shown inFigure 1. Therefore, the proposed topology requires lower number of transistors whichbrings lower quiescent current and smaller die area with respect to the comparator-basedbuffer structures.

The output resistance of the proposed buffer amplifier can be found as:

Rout ¼ ro11kro121þ Aβ

(1)

where roi (i = 11, 12) is the output resistance of the ith transistor at the output stage, andAβ is the loop gain in the proposed circuit. The value of Aβ can be computed as:

Aβ ¼ Vout

Vin¼ gm11 þ gm12ð Þ gm9gm3 þ gm10gm4ð ÞroAroB ro11kro12ð Þ (2)

where gmi is the transconductance of the relevant transistor, roA ¼ ro2jjro6 (≅ roA0 ¼ ro5jjro8)and roB ¼ ro9jjro10 are the total resistances at nodes A and B, respectively. Thus, the outputresistance is found as:

Rout ffi 1

gm11 þ gm12ð Þ gm9gm3 þ gm10gm4ð Þ ro2kro6ð Þ ro9kr010ð Þ (3)

3. Simulation results of the buffer amplifier

Based on 0.35 µm AMS CMOS technology parameters, the proposed circuit is laid outusing Mentor Graphics IC Station layout editor, and it is given in Figure 3. The layoutoccupies an area of approximately 30 × 36 µm2. The supply voltage is +3.3 V. Thedimensions of the transistors are given in Table 1. To achieve a compact die area,

36 μm

30 μ

m

Figure 3. Layout of the proposed buffer amplifier.

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transistor dimensions are chosen to be small. The quiescent current of the circuit is foundas 1.6 µA.

Figure 4 shows the transient response of the proposed buffer amplifier with a loadcapacitance of CL = 1 nF (in the literature most of the simulations have been performedunder a load capacitance of 600 pF), connected to the output of the circuit. The transientresponse simulation is performed with a 125-kHz full-swing input step. The slew ratevalues of the proposed buffer amplifier under this load capacitance are 3 V/µs and3.1 V/µs for the rising and falling edges, respectively. The average of the positive andnegative settling time is 1.45 µs for the final voltages.

To simulate the tracking performance of the proposed buffer amplifier, a full-swingtriangle waveform with a frequency of 50 kHz is applied to the input of the circuit. Thesimulation results are given in Figure 5. It is shown that the output voltage follows theinput voltage for a full dynamic range. Figure 6 shows the simulated transient response toa 50-kHz full-swing input step waveform for a small capacitive load of CL = 10 pF.Similarly, in Figure 7, the simulation results are given for a 50-kHz, 50-mV input stepvoltage under a 10-pF load capacitance. This simulation shows that the offset voltage issmaller than 1 mV.

Table 1. The dimensions of the MOS transistors used in the proposedbuffer amplifier.

MOSFET W (μm) L (μm)

M1, M2 15 0.7M3, M6, M7, M8 5 0.7M4, M5 10 0.7M9 90 0.9M10 30 0.9M11 60 0.5M12 20 0.35M13 15 1M14, M15 10 1M16 5 1

3.5inputoutput3

2.5

1.5

1

0.5

Vol

tage

[V

]

00 2 4 6 8 10 12 14 16

Time [μs]

2

Figure 4. Post-layout simulated transient response to a 125-kHz full-swing input step waveformfor a capacitive load of CL = 1 nF.

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In order to analyse any process mismatches and tolerances, Monte Carlo analysis hasbeen performed. W, L, tox and VT0 parameters of each transistor are varied by using thevalues supplied by the AMS. Simulation results are given in Figure 8. It is observed thatthe proposed buffer amplifier is less affected by the process mismatches. Frequencyvariation of the impedance at output port is given in Figure 9. The value of the equivalentimpedance is 0.19 Ω at 1 MHz, 2.09 Ω at 10 MHz and 115.4 Ω at 100 MHz. Frequencyresponse of the proposed circuit is given in Figure 10. The 3 dB frequency is obtained as28.4 MHz with 1 nF load capacitor. In order to reveal the stability of the proposed circuit,

input

output

3

1

Vol

tage

[V

]

00 10 20 30 40 50 60

Time [μs]

2

3

1V

olta

ge [

V]

0

2

Figure 5. Post-layout simulated transient response to a 50-kHz full-swing input triangular wave-form for a capacitive load of CL = 1 nF.

input

output

3

1Vol

tage

[V

]

00 10 20 30 40 50 60

Time [μs]

2

3

1

Vol

tage

[V

]

0

2

Figure 6. Post-layout simulated transient response to a 50-kHz full-swing input step waveform fora capacitive load of CL = 10 pF.

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3.5

3

2.5

1.5

1

0.5

Vol

tage

[V

]

00 2 4 6 8 10 12 14 16

Time [μs]

2

Figure 8. Monte Carlo simulation result for the proposed buffer amplifier transient response.

input

output

Vol

tage

[V

]

0 5 10 15 20 25 30 35 40Time [μs]

1.64

1.6Vol

tage

[V

]

1.62

1.64

1.6

1.62

Figure 7. Post-layout transient response to a 50-kHz, 50-mV input step waveform for a capacitiveload of CL = 10 pF.

3.5

3

2.5

1.5

1

0.5

Impe

danc

e [k

Ω]

0104 105 106 107 108 109 1010

Frequency [Hz]

2

Figure 9. Frequency variation of the output impedance.

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the feedback connection, from the output node to the gates of M5 and M6, is detached andthe loop gain versus phase response is analysed. A phase margin (PM) of 25° is obtainedat the crossover frequency. The simulation results are given in Figure 11. To compare theperformance of the proposed circuit with previously proposed buffer amplifiers, a basicfigure of merit (FOM) is defined as:

0

–20

–40

–80

–100

Gai

n [d

B]

103 104 105 106 107 108 109

Frequency [Hz]

–60

Figure 10. Frequency response of the buffer amplifier.

0

–50

–150

–100

0

50

–50

–100

Phas

e [d

egre

e]L

oop

Gai

n [d

B]

102 104 106

Frequency [Hz]

PM = 25 degrees

–200

Figure 11. Phase margin of the proposed circuit.

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Table

2.Perform

ance

comparisonof

thebu

ffer

amplifiercircuits.

Lu

(200

4)LuandXiao

(200

6)Wanget

al.

(200

7)Maranoet

al.

(201

0b)

Maranoet

al.

(201

0a)

LuandHsiao

(2011)

Yıld

ızet

al.

(2011)

This

work

CMOStechno

logy

0.35

µm

0.35

µm

0.35

µm

0.35

µm

0.6µm

0.35

µm

0.35

µm

0.35

µm

Sup

plyvo

ltage

(V)

3.3

3.3

3.3

33

3.3–

83.3

3.3

Loadcapacitor(pF)

600

600

1000

1000

1000

600

600

1000

Quiescent

current

(µA)

7(Exp

.)5.4(Exp

.)7.7(Exp

.)8(Sim

.)3.5(Sim

.)5(Exp

.)3(Sim

.)1.6

(Sim

.)Settling

time(µs)

2.8

(Exp

.)1.5(Exp

.)1.28

(Exp

.)0.8(Sim

.)1.7(Sim

.)1.5(Exp

.)0.85

(Sim

.)1.45

(Sim

.)In/out

rang

e(V

)0/3.3

0/3.3

0/3.3

0/3

0/3

0.1/(V

DD-0.1)

0/3.3

0/3.3

In/out

rang

e(%

VDD)

100%

100%

100%

100%

100%

97%

100%

100%

Activearea

(µm

2)

46.5

×57

29.3

×86

.347

×45

25×25

30.5

×30

30×98

60×36

30×36

FOM

(F/A.s)

30.6

74.1

101.5

156.2

168.1

8023

543

1

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FOM ¼ CL

IQtS(4)

In FOM expression, CL is the load capacitance, tS is the average settling time and IQ is thequiescent current of the buffer amplifier. FOM shows the performance of the bufferamplifiers where bigger values bring better performance. The main performance para-meters and FOM value of the proposed buffer amplifier are compared with the otherbuffer amplifier topologies in Table 2. In this paper although the settling time is similarwith other works, it has a very low quiescent current compared with the other circuits. Theproposed amplifier has a FOM value of 431 which points out that the overall performanceof the proposed circuit is better than that of the previously reported topologies.

4. Conclusion

In this paper, a low-quiescent current rail-to-rail CMOS buffer amplifier is proposed. Thelayout of the buffer amplifier is drawn with 0.35 µm AMS CMOS technology parameters.The post-layout simulations of the buffer amplifier are obtained with a high outputcapacitance (CL = 1 nF) connected to the output of the amplifier. From the simulations,the average settling time is obtained as 1.45 µs with a very low quiescent current. Inaddition to this process, the layout area of the proposed buffer amplifier is achieved as30 × 36 µm2, which is also important for big size LCD displays. As a result, theperformance of the proposed buffer amplifier is better than that of the previouslypublished ones. Since this proposed buffer amplifier drives a very low quiescent currentfrom the source, it is suitable for compact and portable LCD devices.

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