Name: Yuan Mei Brookhaven National Laboratory Instrumentation Division ULITIMA 2018 A Calibration concept for SAR ADC for operation in LAr TPC 9/11/2018 Yuan Mei 1 [email protected]
Name: Yuan Mei
Brookhaven National Laboratory
Instrumentation Division
ULITIMA 2018
A Calibration concept for SAR ADC for operation in LAr TPC
9/11/2018 Yuan Mei 1
Motivation
▪Design a 12-bit ADC running 2MS/s for DUNE
▪Risk mitigation for cold temperature @77K
▪Errors from analog circuits should be overcome with digital calibration, transferring complexity from analog to digital domain
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SAR ADC Architecture
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DAC SAR Logic
Vin
Digital Outputs
Comparator
• Bottom plate sampling method with synchronous timing
• 12-bit resolution with 14 conversion-cycle (2-bit redundancy)
• Digital foreground calibration implemented
Static Error sources
• Conversion accuracy is subject to the non-idealities of analog components, the main error source are DAC mismatch and comparator offset errors.
• SAR only has one comparator, offset won’t affect linearity.
• Bottom-plate sampling is performed, thus injected charge to the top-plate is independent of input signal and contribute a fixed offset
• Auto-zeroing and chopper techniques are often used to eliminate comparator offset
• Capacitor mismatch is fatal to ADC performance if not solved
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Capacitor mismatch issues
• 12-bit matching is needed in the capacitor array
oRandom mismatch: Gaussian distribution
oGradient mismatch: Location-dependent
oRouting mismatch: Layout dependent
• Unit-cap and common-centroid layout can fix gradient mismatch and routing mismatch
• Random mismatch can be solved by using larger unit-capacitor [1] or using calibration method
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Capacitor mismatch in DAC
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DAC mismatch limit ADC performance and calibration would improve ADC!
Idea of Digital Calibration
• Post-processing of codes
oRelies on digital signal processing
oNo feedback to ADC and thus no stability issue
oDoesn’t required complex analog circuit
oDigital circuits scale in advanced process
Correlation-based calibration is selected for this prototype
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Correlation-based Calibration
• Inject a small amount of analog signal that is uncorrelated with the input signal. Since it passes through the same path as DAC signal, it encounter same non-idealities and hence can detect the mismatch error
• Using a statistical correlator (histogram method) or the least mean square (LMS) algorithm, the inject signal can be “correlated out” in the digital back-end and capacitor mismatch error are estimated in the process [2]
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Implementation of Algorithm
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• Each sampled analog signal will be digitized twice
• Decimal output codes d1 and d2 will create a error function
• Error function will provide information to infer the unknown weighting vector W
• Adaptive learning algorithm (LMS) to update weight coefficient in DAC in which error is gradually forced to zero
• Learning procedure converges, the mean of d1 and d2 will yield the correct digital output codes
Fig. Block diagram of the perturbation based digital calibration for SAR ADC [3]
SARCORE
Encode 1
Encode 2
e[n]
LMS
d
a a
2
D1
D2 d2
d1
doutVin
W1
W2
Calibration engine
LMS : Wk [N+1] = Wk[n] - µ*e[n]*dk[n]
e [N] = d1[n] - d2[n] -2 d
Capacitor ratio with redundancy
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Calibration circuit
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Advantage• Calibration circuit can be utilized in DAC• Calibration circuit is stable at cold • Calibration control is simple
Disadvantage• Decrease input dynamic range
Notes :Single-ended for simplicityImplemented in differential
Vinput
Bootstrap_Switch
Transmission-Gate Switch
Vref_pos
Transmission-Gate Switch
Vref_neg
1920 1024 544 288 144 80 40 24 12 8 6 2 2 1 10
MSB LSB Calibration Cap
VCM
Controlled by SAR Logic
VCM
Calibration Circuit
Timing Diagram
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40 Cycles
Reset
Sample
Output1
D14 D13 D12 D2 D1
Clk
Output2
D14b D2b D1b
Input regeneration
• One complete conversion consist of a 5 clock-cycle sampling phase and two 14 clock-cycle conversion phases;• Besides, 1 clock-cycle is reserve for reset and 6 clock-cycle is for input regeneration.
Timing diagram of the proposed calibration method
Simulations with digital calibration
• Simulations are done in Cadence @ 77K temperature
• All blocks are implemented and simulated in transistor level
• Unit capacitor is MIM cap provided by foundry (about 10 fF)
• DAC mismatch errors are the major error source
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Capacitor mismatch calibration verification
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• Set random mismatch on capacitor weights
• Simulate to see if calibration can find the optimal weight and improve the performance
• Other mismatch is excluded from this verfication
Capacitor mismatch calibration
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Simulated with 2^14 (16,384) samples, weights are converged around 10,000 samples X-axis: # of samples Y-axis: Capacitor weight
Capacitor mismatch calibration
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Simulated with 2^14 (16,384) samples, weights are converged around 10,000 samples X-axis: # of samples Y-axis: Capacitor weight
Capacitor mismatch calibration
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With calibration, all the weights in the DAC are updated X-axis: # of samples Y-axis: Capacitor weight
Dynamic test
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FFT points:2^14
Without CalibrationENOB = 8.3 bits
With CalibrationENOB= 11.2 bits
• ENOB is improved• Dynamic range also improved
Dynamic test
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FFT points:2^17
Without CalibrationENOB = 8.3 bits
With CalibrationENOB= 11.9 bits
• ENOB is further improved from 11.2bits to 11.9bits • Dynamic range also improved from 69.1 dB to 73.6dB
With more samples :
Static test
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Without Calibration Without Calibration
• Linearity is improved with the digital calibration
Sample points:2^14
A lot missing codes! NO missing code!
Static test
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With samples 131,072 (2^17)
• Linearity is further improved with more samples
With samples 16,384 (2^14)
Floorplan
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N-DAC
P-DAC
DummyDummy Dummy
Dummy Dummy Dummy
Du
mm
yD
um
my
Du
mm
yD
um
my
Dummy Dummy
Dummy Dummy Dummy
N-DAC DC Switches
P-DAC DC Switches
VCMSwitch
VCMSwitch
Vin+ BootstrapSwitch
Vin- BootstrapSwitch
Comparator
Preamp
Preamp
NomalModeSAR
Logic
CalibrationModeSAR
Logic
Clock GeneratorData Formatter
+LVDS I/O
Digital DomainAnalog Domain
Floorplan of SAR ADC prototype
Die Photo
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Die photo of SAR ADC prototype
Measurement
• Chip came back in Mid-July and measurement will be done in October
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Power consumption @77K(Simulation by PEX)
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Block Name Power consumption 2MS/s
Digital 240 µw
Analog 280 µW
Total 520 µW
Acknowledgement
• My colleagues : Gabriella Carini, Huchen Chen, Mietek Dabrowski, Shaorui Li , and Emerson Vernon
• Fermi lab collaborators and their cold model for TSMC 65nm at 77K
• DUNE and DoE for support of this work
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Reference
[1] Yi-long Yu, ADI talk, A 12 bit 100MS/s two step hybrid ADC in 40nm CMOS with statistical calibration
[2] Ahmed M. A. Ali. 2016. High Speed Data Converters. Institution of Engineering and Technology.
[3] W. Liu, P. Huang and Y. Chiu, "A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration," in IEEE J. of Solid-State Circuits, vol. 46, no. 11, pp. 2661-2672, Nov. 2011.
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Q & A
Thank you for your attention.
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Backup slides
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Wi represents the respective bit weight. µ i is the step size of the update equation and is scaled according to the bit.e[N] is the total error of the Nth step. dN are the raw ADC output;Δd are digitized offset of the inserting analog offset Δa
LMS : Wk [N+1] = Wk[n] - µ*e[n]*dk[n]
e [N] = d1[n] - d2[n] -2 d
Convergence of Error
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