A 77-GHz High Gain Low Noise Receiver for Automatic Radar ...

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Article

A 77-GHz High Gain Low Noise Receiver for AutomaticRadar Applications

Shuai Cheng 1,2 , Linhong Li 1,2, Niansong Mei 1 and Zhaofeng Zhang 1,*

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Citation: Cheng, S.; Li, L.; Mei, N.;

Zhang, Z. A 77-GHz High Gain Low

Noise Receiver for Automatic Radar

Applications. Electronics 2021, 10,

1516. https://doi.org/10.3390/

electronics10131516

Academic Editor: Krzysztof S. Kulpa

Received: 19 May 2021

Accepted: 21 June 2021

Published: 23 June 2021

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4.0/).

1 Shanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai 201210, China;[email protected] (S.C.); [email protected] (L.L.); [email protected] (N.M.)

2 University of Chinese Academy of Sciences, Beijing 100049, China* Correspondence: [email protected]

Abstract: In this paper, a high gain 77-GHz receiver with a low noise figure (NF) was designed andimplemented in a 40-nm CMOS process. With the purpose of making better use of active devices, anextra inductor, Ld, is adopted in the new neutralization technique. The three-stage differential lownoise amplifier (LNA) using the proposed technique improves the voltage gain and reduces the NF.The receiver design utilizes an active double-balanced Gilbert mixer with a transformer couplingnetwork between the transconductance stage and the switch stage. The flicker noise contributionfrom the switch MOS transistors is largely reduced due to the low DC current of the switch pairs.The LO signal is provided by an on-chip fundamental voltage-controlled oscillator (VCO) with atuning range from 70.5 to 78.1 GHz. A conversion gain of 32 dB and a NF of 11.86 dB are achievedat 77 GHz by the designed receiver. The LNA as well as the mixer consume a total DC power of33.2 mW and occupy a core size of 1 × 0.38 mm2.

Keywords: radar; receiver; front-end; low noise amplifier; mixer; neutralization technique; high gain;voltage-controlled oscillator

1. Introduction

In recent years, the advanced driver assistance system (ADAS) for automobiles hasbecome a research hotspot and has made great development. The millimeter-wave radarhas been a fundamental sensor in the ADAS due to its unparalleled adaptability to complexenvironments. Meanwhile, as the CMOS technology node scales, the CMOS millimeter-wave circuits and systems for radar applications become popular [1–5] because of the highintegrity and low cost. However, compared with the HEMTs and BJTs, CMOS transistorsstill suffer from low gain and high noise. Particularly, the RF front-end design of thelong-range radar sensor based on CMOS technology faces more severe challenges since itrequires better system sensitivity [6].

For high system sensitivity, the receiver front-end is required to have a high amplitudegain and a low noise contribution. Many designs [7–11] in CMOS technology for radarapplications have been reported. Reference [7] presents an LNA design with a gain of20 dB and a noise figure (NF) of 4.6 dB. The receiver in [8] achieves a conversion gain of14 dB and an NF of 12.8 dB. The designs in [7,8] use the advanced FD-SOI technology,which means more cost for the consumers. Reference [9] realizes an LNA with a gain of17.3 dB and an NF of 7.4 dB using the microstrip lines as inductive components, whichoccupy more chip areas. References [10,11] adopt a passive mixer to realize a good NF of 9and 8.7 dB, respectively. However, the LNA designs using the traditional neutralizationtechnique have room for gain improvement.

This paper proposes a neutralization technique using an extra inductor based onthe Gmax theories in the gain-plane [12–14]. Compared with the traditional capacitiveneutralization technique, the proposed one helps the low noise amplifier (LNA) attainbetter gain and lower NF. The active mixer structure is also used to improve the gain.

Electronics 2021, 10, 1516. https://doi.org/10.3390/electronics10131516 https://www.mdpi.com/journal/electronics

Electronics 2021, 10, 1516 2 of 14

In order to reduce the contribution of flicker noise, the transformer coupling networkis employed between the transconductance stage and the switch stage with a small DCcurrent of the switching transistors. The receiver design has a high conversion gain andlow noise figure, which is rather applicable for long-range radar applications. Section 2details the design of the LNA using the new neutralization technique, active mixer, and thedesign of the fundamental voltage-controlled oscillator (VCO) for LO signals of the mixer.The receiver measurement results and discussions, as well as performance comparison, arepresented in Section 3. The conclusions are drawn in Section 4.

2. Receiver Design

The LNA is a critical block in the receiver front-end since it reduces the noise con-tribution of the following circuits and thus improves the system sensitivity. However, atmillimeter-wave frequencies, the amplifiers in CMOS suffer from low gain. Especially, theparasitic capacitance, Cgd, exacerbates the problem by providing a feedback path. Mean-while, single-ended structures are significantly sensitive to the parasitics of the currentreturn paths, particularly the parasitic inductive degeneration at the source terminal. Ac-cordingly, differential amplifiers using the capacitive neutralization technique are mostlyadopted to mitigate the above issues [15–18].

Unfortunately, according to the Gmax theories in the gain-plane, the traditional neu-tralization technique is a sub-optimal method. References [12,14] give the maximumachievable gain in Equation (1), where U expressed in Equation (2) denotes the unilateralgain or Mason’s gain, which is a real number. References [12,13] demonstrate a specific wayusing three inductors to realize the maximum gain in theory. However, the MOS transistorswith the same gate and drain voltage cannot flexibly be configured for performance, andthe main inductor becomes bulky at the lower frequencies. The LNA proposed to overcomethe above issues is depicted in Figure 1. An extra inductor Ld is added to help attain theoptimal design.

Electronics 2021, 10, x FOR PEER REVIEW 2 of 15

and lower NF. The active mixer structure is also used to improve the gain. In order to reduce the contribution of flicker noise, the transformer coupling network is employed between the transconductance stage and the switch stage with a small DC current of the switching transistors. The receiver design has a high conversion gain and low noise figure, which is rather applicable for long-range radar applications. Section 2 details the design of the LNA using the new neutralization technique, active mixer, and the design of the fundamental voltage-controlled oscillator (VCO) for LO signals of the mixer. The receiver measurement results and discussions, as well as performance comparison, are presented in Section 3. The conclusions are drawn in Section 4.

2. Receiver Design The LNA is a critical block in the receiver front-end since it reduces the noise contri-

bution of the following circuits and thus improves the system sensitivity. However, at millimeter-wave frequencies, the amplifiers in CMOS suffer from low gain. Especially, the parasitic capacitance, Cgd, exacerbates the problem by providing a feedback path. Mean-while, single-ended structures are significantly sensitive to the parasitics of the current return paths, particularly the parasitic inductive degeneration at the source terminal. Ac-cordingly, differential amplifiers using the capacitive neutralization technique are mostly adopted to mitigate the above issues [15–18].

Unfortunately, according to the Gmax theories in the gain-plane, the traditional neu-tralization technique is a sub-optimal method. References [12,14] give the maximum achievable gain in Equation (1), where U expressed in Equation (2) denotes the unilateral gain or Mason’s gain, which is a real number. References [12,13] demonstrate a specific way using three inductors to realize the maximum gain in theory. However, the MOS transistors with the same gate and drain voltage cannot flexibly be configured for perfor-mance, and the main inductor becomes bulky at the lower frequencies. The LNA proposed to overcome the above issues is depicted in Figure 1. An extra inductor Ld is added to help attain the optimal design.

Figure 1. Schematic of the proposed low noise amplifier.

As described in [12,13], the maximum achievable gain of the gain cell is determined by the locations in the gain-plane shown in Figure 2. A is the function of y-parameters shown in Equation (3), which is a complex variable. The x-axis corresponds to the real part of the ratio of U to A, i.e., re(U/A). The y-axis represents the imaginary part of the ratio of U to A. Some gain circles are illustrated, and the best location for achieving the maximum gain is marked, which approximately equals (−0.25, 0). The design with a ratio of U to A, which belongs to the points on the gain circles excluding the dot points, means its maxi-mum achievable gain equals the corresponding gain. For example, the points in the gain circle of Gmax/U = 2 make the amplifier attain a maximum gain of 2U. The parabola curve represents the stability boundary of Kf = 1. The stable region satisfying Kf > 1 is inside this curve. Meanwhile, the nearer the distance of the gain circle to the best location, the larger the maximum achievable gain.

LdLdLd

M3

M4

M5

M6

M1

M2

Cn

Cn

Cn

Cn

Cn

Cn

VinVop

Von

Figure 1. Schematic of the proposed low noise amplifier.

As described in [12,13], the maximum achievable gain of the gain cell is determinedby the locations in the gain-plane shown in Figure 2. A is the function of y-parametersshown in Equation (3), which is a complex variable. The x-axis corresponds to the realpart of the ratio of U to A, i.e., re(U/A). The y-axis represents the imaginary part of theratio of U to A. Some gain circles are illustrated, and the best location for achieving themaximum gain is marked, which approximately equals (−0.25, 0). The design with a ratioof U to A, which belongs to the points on the gain circles excluding the dot points, meansits maximum achievable gain equals the corresponding gain. For example, the points in thegain circle of Gmax/U = 2 make the amplifier attain a maximum gain of 2U. The parabolacurve represents the stability boundary of Kf = 1. The stable region satisfying Kf > 1 isinside this curve. Meanwhile, the nearer the distance of the gain circle to the best location,the larger the maximum achievable gain.

Electronics 2021, 10, 1516 3 of 14Electronics 2021, 10, x FOR PEER REVIEW 3 of 15

Figure 2. Gmax circles and the stability boundary with respect to U/A.

Figure 3 compares the location movements with increased capacitances between the proposed neutralization technique and the traditional neutralization technique. The blue trace exhibits the movements with increased neutralization capacitance of the traditional neutralization technique without Ld. A larger capacitance helps the movements reach higher gain circles. However, the movement has a deviation from the best location, which means the amplifiers with the traditional neutralization technique are sub-optimal de-signs. The red trace demonstrates that an Ld of 20 pH helps the location move towards the best location more closely. To illustrate the performance improvements, the simulated S21 and NF of the LNA in Figure 1 with Ld = 0 and Ld = 20 pH, respectively, are presented in Figure 4. The results imply that Ld contributes to higher gain and lower NF.

Therefore, the traditional neutralization technique adopts a large neutralization ca-pacitance to obtain a high gain with a positive imaginary part of the U/A, which is a sub-optimal choice. The optimal neutralization technique adopts the appropriate neutraliza-tion capacitance and inductor, making a zero imaginary part of the U/A and the real part of the U/A close to −0.25, with the stable condition.

−2.5

−2

−1.5

−1

−0.5

0

0.5

1

1.5

2

2.5

−1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3 3.5

Im(U

/A)

Re(U/A)

Gmax/U=2

Gmax/U=1Gmax/U=0.5

Kf =1

Figure 2. Gmax circles and the stability boundary with respect to U/A.

Figure 3 compares the location movements with increased capacitances between theproposed neutralization technique and the traditional neutralization technique. The bluetrace exhibits the movements with increased neutralization capacitance of the traditionalneutralization technique without Ld. A larger capacitance helps the movements reachhigher gain circles. However, the movement has a deviation from the best location, whichmeans the amplifiers with the traditional neutralization technique are sub-optimal designs.The red trace demonstrates that an Ld of 20 pH helps the location move towards the bestlocation more closely. To illustrate the performance improvements, the simulated S21 andNF of the LNA in Figure 1 with Ld = 0 and Ld = 20 pH, respectively, are presented inFigure 4. The results imply that Ld contributes to higher gain and lower NF.

Therefore, the traditional neutralization technique adopts a large neutralization ca-pacitance to obtain a high gain with a positive imaginary part of the U/A, which is asub-optimal choice. The optimal neutralization technique adopts the appropriate neutral-ization capacitance and inductor, making a zero imaginary part of the U/A and the realpart of the U/A close to −0.25, with the stable condition.

Gmax= (2U − 1) + 2√

U(U − 1) (1)

U =|Y21 −Y12|

4(Re[Y11] ·Re[Y22]−Re[Y12] · Re[Y21])(2)

A =Y21

Y12(3)

Electronics 2021, 10, 1516 4 of 14Electronics 2021, 10, x FOR PEER REVIEW 4 of 15

Figure 3. Location movements with the increased neutralization capacitances with and without Ld, respectively.

Figure 4. Simulated S21 and NF with and without Ld, respectively.

G U U U− −max = (2 1) + 2 ( 1) (1)

Y YU

Y Y Y Y

−

⋅ − ⋅21 12

11 22 12 21

=4(Re[ ] Re[ ] Re[ ] Re[ ])

(2)

−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

−1 −0.5 0 0.5 1

Im(U

/A)

Re(U/A)

Ld =20pLd =0

Kf =1

Gmax/U=2

Gmax/U=1

5

10

15

20

25

72 73 74 75 76 77 78 79 80 81 82

S21(

dB)/N

F(dB

)

Frequency(GHz)

S21 Ld=0S21 Ld=20 pHNF Ld=0NF Ld=20 pH

>2.5dB

>0.3dB reduction

Figure 3. Location movements with the increased neutralization capacitances with and without Ld,respectively.

Electronics 2021, 10, x FOR PEER REVIEW 4 of 15

Figure 3. Location movements with the increased neutralization capacitances with and without Ld, respectively.

Figure 4. Simulated S21 and NF with and without Ld, respectively.

G U U U− −max = (2 1) + 2 ( 1) (1)

Y YU

Y Y Y Y

−

⋅ − ⋅21 12

11 22 12 21

=4(Re[ ] Re[ ] Re[ ] Re[ ])

(2)

−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

−1 −0.5 0 0.5 1

Im(U

/A)

Re(U/A)

Ld =20pLd =0

Kf =1

Gmax/U=2

Gmax/U=1

5

10

15

20

25

72 73 74 75 76 77 78 79 80 81 82

S21(

dB)/N

F(dB

)

Frequency(GHz)

S21 Ld=0S21 Ld=20 pHNF Ld=0NF Ld=20 pH

>2.5dB

>0.3dB reduction

Figure 4. Simulated S21 and NF with and without Ld, respectively.

At the millimeter-wave frequency, to attain enough gain for the front-end, an activeGilbert mixer is utilized, which helps reduce the noise contribution of the subsequentblocks. However, the classic active mixer shown in Figure 5 accompanied with high outputflicker noise has difficulty achieving high gain due to the low voltage headroom acrossthe load resistor. Therefore, we propose a high gain and low flicker noise mixer structuredemonstrated in Figure 6. The RF voltage signal is converted to RF current through the

Electronics 2021, 10, 1516 5 of 14

transconductance stage. Then the current signal is coupled to the switching stage by a 1:1transformer. The DC current of the switching transistors is set to 0.25 mA, which greatlyreduces the flicker noise contribution from the transistors. Meanwhile, high load resistorsand the transconductance stage using the proposed neutralization technique help realize ahigh conversion gain. Another advantage of the proposed topology is the low amplitudelevel requirement of the LO signal.

The NF comparison between the proposed mixer and the classic mixer is conducted todemonstrate the NF performance improvement. With a higher supply voltage, the classicmixer is designed with the same conversion gain of 11 dB as that of the proposed mixer.The simulated single-sideband (SSB) NF results are presented in Figure 7. It is observedthat the classic mixer design suffers higher NF at the flicker-noise regions and larger cornerfrequency compared with the proposed design. The NF of the proposed mixer is reducedby above 4 dB with the IF frequency lower than 1 MHz, which indicates the flicker noisecontribution is significantly reduced.

Electronics 2021, 10, x FOR PEER REVIEW 5 of 15

YA

Y21

12

= (3)

At the millimeter-wave frequency, to attain enough gain for the front-end, an active Gilbert mixer is utilized, which helps reduce the noise contribution of the subsequent blocks. However, the classic active mixer shown in Figure 5 accompanied with high out-put flicker noise has difficulty achieving high gain due to the low voltage headroom across the load resistor. Therefore, we propose a high gain and low flicker noise mixer structure demonstrated in Figure 6. The RF voltage signal is converted to RF current through the transconductance stage. Then the current signal is coupled to the switching stage by a 1:1 transformer. The DC current of the switching transistors is set to 0.25 mA, which greatly reduces the flicker noise contribution from the transistors. Meanwhile, high load resistors and the transconductance stage using the proposed neutralization technique help realize a high conversion gain. Another advantage of the proposed topology is the low amplitude level requirement of the LO signal.

The NF comparison between the proposed mixer and the classic mixer is conducted to demonstrate the NF performance improvement. With a higher supply voltage, the clas-sic mixer is designed with the same conversion gain of 11 dB as that of the proposed mixer. The simulated single-sideband (SSB) NF results are presented in Figure 7. It is observed that the classic mixer design suffers higher NF at the flicker-noise regions and larger cor-ner frequency compared with the proposed design. The NF of the proposed mixer is re-duced by above 4 dB with the IF frequency lower than 1 MHz, which indicates the flicker noise contribution is significantly reduced.

Figure 5. The schematic of the classic mixer.

M1 M2

Cn

Vrfp Vrfn

BufferVifp

Rload Rload

M3 M4 M5 M6

Vlo

Cn

BufferVifn

VDD

Figure 5. The schematic of the classic mixer.Electronics 2021, 10, x FOR PEER REVIEW 6 of 15

Figure 6. The schematic of the proposed double-balanced mixer.

To simplify the gain analysis, the current coupling model is illustrated in Figure 8. The current source i0 represents the RF current converted by the transconductance stage. Zo and Zi denote the output impedance of the transconductance stage and the input im-pedance of the switching stage, respectively. According to the principle of the trans-former, we obtain Equations (4) and (5). The current coupling factor provided by the trans-former is derived as Equation (6). Therefore, the overall gain can be obtained from Equa-tion (7). It is apparent that a larger |k| results in a larger numerator and a smaller denom-inator. So, a larger coupling factor is beneficial for the conversion gain. The structure of the stacked transformer is a proper choice. The transformer design in the commercial Elec-tro-Magnetic simulator HFSS (i.e., High Frequency Structure Simulator) is presented in Figure 9. Figure 10 demonstrates the inductances of the primary and secondary windings and the coupling factor, k, between them. At 77 GHz, a large k of −0.83 is realized in the transformer design. Meanwhile, the quality factors are higher than 9 at the desired fre-quencies.

Figure 7. The simulated noise figure of the mixer.

Ld

M1

M2

Cn

Cn

Vrfp

Vrfn

Buffer

Buffer

Vifp

Vifn

Rload

Rload

M3

M4M5

M6

Vlo

10

15

20

25

30

35

40

Noi

se F

igur

e(dB

)

Intermediate Frequency(Hz)10K 100K 1M 10M 100M 1G

Figure 6. The schematic of the proposed double-balanced mixer.

Electronics 2021, 10, 1516 6 of 14

To simplify the gain analysis, the current coupling model is illustrated in Figure 8. Thecurrent source i0 represents the RF current converted by the transconductance stage. Zo andZi denote the output impedance of the transconductance stage and the input impedanceof the switching stage, respectively. According to the principle of the transformer, weobtain Equations (4) and (5). The current coupling factor provided by the transformer isderived as Equation (6). Therefore, the overall gain can be obtained from Equation (7).It is apparent that a larger |k| results in a larger numerator and a smaller denomina-tor. So, a larger coupling factor is beneficial for the conversion gain. The structure ofthe stacked transformer is a proper choice. The transformer design in the commercialElectro-Magnetic simulator HFSS (i.e., High Frequency Structure Simulator) is presented inFigure 9. Figure 10 demonstrates the inductances of the primary and secondary windingsand the coupling factor, k, between them. At 77 GHz, a large k of −0.83 is realized inthe transformer design. Meanwhile, the quality factors are higher than 9 at the desiredfrequencies.

V1= (i0 − i1)Zo = i1 · sL1 − i2 · sM (4)

V2 = i2 · Zi = −i2 · sL2 + i1 · sM (5)

i2i0

=ZosM

(Zi+sL2)(Zo+sL1)− s2M2 (6)

CG =2π

gmRDZos|k|

√L1L2

|s2L1L2(1 − k2) + sL1Zi+sL2Zo + ZiZo|(7)

Electronics 2021, 10, x FOR PEER REVIEW 6 of 15

Figure 6. The schematic of the proposed double-balanced mixer.

To simplify the gain analysis, the current coupling model is illustrated in Figure 8. The current source i0 represents the RF current converted by the transconductance stage. Zo and Zi denote the output impedance of the transconductance stage and the input im-pedance of the switching stage, respectively. According to the principle of the trans-former, we obtain Equations (4) and (5). The current coupling factor provided by the trans-former is derived as Equation (6). Therefore, the overall gain can be obtained from Equa-tion (7). It is apparent that a larger |k| results in a larger numerator and a smaller denom-inator. So, a larger coupling factor is beneficial for the conversion gain. The structure of the stacked transformer is a proper choice. The transformer design in the commercial Elec-tro-Magnetic simulator HFSS (i.e., High Frequency Structure Simulator) is presented in Figure 9. Figure 10 demonstrates the inductances of the primary and secondary windings and the coupling factor, k, between them. At 77 GHz, a large k of −0.83 is realized in the transformer design. Meanwhile, the quality factors are higher than 9 at the desired fre-quencies.

Figure 7. The simulated noise figure of the mixer.

Ld

M1

M2

Cn

Cn

Vrfp

Vrfn

Buffer

Buffer

Vifp

Vifn

Rload

Rload

M3

M4M5

M6

Vlo

10

15

20

25

30

35

40

Noi

se F

igur

e(dB

)

Intermediate Frequency(Hz)10K 100K 1M 10M 100M 1G

Figure 7. The simulated noise figure of the mixer.

Electronics 2021, 10, x FOR PEER REVIEW 7 of 15

Figure 8. The current coupling model of the mixer.

V i i Z i L i M− ⋅ − ⋅1 0 1 o 1 1 2= ( ) = s s (4)

V i Z i L i M⋅ − ⋅ ⋅2 2 i 2 2 1= = s + s (5)

Z Mii Z L Z L M−

o22 2

0 i 2 o 1

s=

( + s )( + s ) s (6)

Z k L LCG g R

L L k L Z L Z Z Z−

o 1 2m D 2 2

1 2 1 i 2 o i o

s2=π s (1 ) + s + s +

(7)

In addition, an on-chip 77 GHz fundamental VCO is realized for the LO signal, as shown in Figure 11. Small varactors with minimal length to reduce tank loss are employed for continuous frequency tuning. At the millimeter-wave frequencies, the digitally con-trolled artificial dielectric (DiCAD) structure is widely adopted [19–21] for discrete fre-quency tuning because it is easy to model and introduces less parasitic inductance for the capacitor bank. The traditional DiCAD structure is shown in Figure 12a. According to Equation (8), the differential open transmission lines behave like a capacitor, whose ca-pacitance is controlled by the digital switches. The traditional DiCAD structure suffers from a limited capacitance range. Therefore, to make the VCO adapt to process-voltage-temperature (PVT) variations better, the proposed DiCAD structure with double-stacked slots presented in Figure 12b is utilized.

Figure 9. The transformer model in the E-M software.

k

i1 i2

Zo ZiL1 L2i0

Figure 8. The current coupling model of the mixer.

Electronics 2021, 10, 1516 7 of 14

In addition, an on-chip 77 GHz fundamental VCO is realized for the LO signal, asshown in Figure 11. Small varactors with minimal length to reduce tank loss are em-ployed for continuous frequency tuning. At the millimeter-wave frequencies, the digitallycontrolled artificial dielectric (DiCAD) structure is widely adopted [19–21] for discretefrequency tuning because it is easy to model and introduces less parasitic inductance forthe capacitor bank. The traditional DiCAD structure is shown in Figure 12a. Accordingto Equation (8), the differential open transmission lines behave like a capacitor, whosecapacitance is controlled by the digital switches. The traditional DiCAD structure suffersfrom a limited capacitance range. Therefore, to make the VCO adapt to process-voltage-temperature (PVT) variations better, the proposed DiCAD structure with double-stackedslots presented in Figure 12b is utilized.

Zin =−jZ0

tan(βl)(8)

Electronics 2021, 10, x FOR PEER REVIEW 7 of 15

Figure 8. The current coupling model of the mixer.

V i i Z i L i M− ⋅ − ⋅1 0 1 o 1 1 2= ( ) = s s (4)

V i Z i L i M⋅ − ⋅ ⋅2 2 i 2 2 1= = s + s (5)

Z Mii Z L Z L M−

o22 2

0 i 2 o 1

s=

( + s )( + s ) s (6)

Z k L LCG g R

L L k L Z L Z Z Z−

o 1 2m D 2 2

1 2 1 i 2 o i o

s2=π s (1 ) + s + s +

(7)

In addition, an on-chip 77 GHz fundamental VCO is realized for the LO signal, as shown in Figure 11. Small varactors with minimal length to reduce tank loss are employed for continuous frequency tuning. At the millimeter-wave frequencies, the digitally con-trolled artificial dielectric (DiCAD) structure is widely adopted [19–21] for discrete fre-quency tuning because it is easy to model and introduces less parasitic inductance for the capacitor bank. The traditional DiCAD structure is shown in Figure 12a. According to Equation (8), the differential open transmission lines behave like a capacitor, whose ca-pacitance is controlled by the digital switches. The traditional DiCAD structure suffers from a limited capacitance range. Therefore, to make the VCO adapt to process-voltage-temperature (PVT) variations better, the proposed DiCAD structure with double-stacked slots presented in Figure 12b is utilized.

Figure 9. The transformer model in the E-M software.

k

i1 i2

Zo ZiL1 L2i0

Figure 9. The transformer model in the E-M software.

Electronics 2021, 10, x FOR PEER REVIEW 8 of 15

Figure 10. The simulated inductances of the primary and secondary windings and the coupling factor.

0in

-j=

tan( )Z

Zβl

(8)

From the view of the minimum capacitance cell, the proposed DiCAD structure dou-bles the capacitance, Con, when the switch is on, while the capacitance, Coff, is just increased a small amount with the switch off. The two structures are simulated by HFSS and the spectre simulator to get the results of capacitance increments and quality factors demon-strated in Figure 13. The DiCAD structure is controlled by the 4-bit switch word, where the high voltage level switches on the corresponding control transistor. The conventional structure achieves a capacitance range from 42 to 59 fF, while the proposed one realizes the range from 38 to 63 fF. The amount of capacitance increment is increased from 17 to 25 fF, which is 42% bigger, using the proposed structure. The minimum quality factor is decreased from 14.4 to 12.6 with all switches on, which is a slight deterioration.

−1

−0.95

−0.9

−0.85

−0.8

−0.75

−0.7

100

140

180

220

260

300

340

70 75 80 85 90

k

Indu

ctan

ce (p

H)

Frequency(GHz)

Lp Ls k

Figure 10. The simulated inductances of the primary and secondary windings and the coupling factor.

From the view of the minimum capacitance cell, the proposed DiCAD structure dou-bles the capacitance, Con, when the switch is on, while the capacitance, Coff, is just increased

Electronics 2021, 10, 1516 8 of 14

a small amount with the switch off. The two structures are simulated by HFSS and thespectre simulator to get the results of capacitance increments and quality factors demon-strated in Figure 13. The DiCAD structure is controlled by the 4-bit switch word, wherethe high voltage level switches on the corresponding control transistor. The conventionalstructure achieves a capacitance range from 42 to 59 fF, while the proposed one realizesthe range from 38 to 63 fF. The amount of capacitance increment is increased from 17 to25 fF, which is 42% bigger, using the proposed structure. The minimum quality factor isdecreased from 14.4 to 12.6 with all switches on, which is a slight deterioration.

Electronics 2021, 10, x FOR PEER REVIEW 9 of 15

Figure 11. The schematic of the fundamental voltage-controlled oscillator.

(a) (b)

Figure 12. Diagrams of (a) the traditional DiCAD structure, and (b) the proposed DiCAD structure.

Figure 13. The capacitance increments and quality factor of the traditional and proposed DiCAD structures, respectively.

S0

S1

S2

S15

DiCAD

VDD

VctrlBuffer Buffer

05101520253035404550

0

5

10

15

20

25

30

Qua

lity

Fact

or

Cap

acita

nce

Incr

emen

t(fF)

Control Bits

CI_classic CI_proposedQ_classic Q_proposed

Figure 11. The schematic of the fundamental voltage-controlled oscillator.

Electronics 2021, 10, x FOR PEER REVIEW 9 of 15

Figure 11. The schematic of the fundamental voltage-controlled oscillator.

(a) (b)

Figure 12. Diagrams of (a) the traditional DiCAD structure, and (b) the proposed DiCAD structure.

Figure 13. The capacitance increments and quality factor of the traditional and proposed DiCAD structures, respectively.

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Figure 12. Diagrams of (a) the traditional DiCAD structure, and (b) the proposed DiCAD structure.

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Figure 11. The schematic of the fundamental voltage-controlled oscillator.

(a) (b)

Figure 12. Diagrams of (a) the traditional DiCAD structure, and (b) the proposed DiCAD structure.

Figure 13. The capacitance increments and quality factor of the traditional and proposed DiCAD structures, respectively.

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Figure 13. The capacitance increments and quality factor of the traditional and proposed DiCADstructures, respectively.

3. Results and Discussions

This receiver is designed in HLMC 40-nm technology with 8 layers of metals. The topmetal, M8, has a thickness of 3.3 µm, and the thickness of M7 is 0.8 µm. The maximumoscillation frequency, fmax, of the MOS transistors with the minimum channel lengthof 40 nm is about 230 GHz. The passive components in the full layout, like inductors,interconnecting lines, and transformers, are divided into three parts, which are importedin HFSS to conduct the E-M simulations, respectively. The ground plane consists of M1and M2 for less loss. The active transistors are extracted with parasitic resistances andcapacitances by the StarRC tool for the fully post-simulations.

The receiver’s chip photograph is shown in Figure 14. The LNA and mixer occupya core area of 1 × 0.38 mm2, while the size of the VCO is 0.59 × 0.59 mm2. The LNAconsumes a DC power of 24 mW from a 0.8-V supply, and the mixer consumes 9.2 mWfrom a 1.2-V supply. The core of the VCO circuit dissipates 33 mW from a 1.2-V supply.

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3. Results and Discussions This receiver is designed in HLMC 40-nm technology with 8 layers of metals. The top

metal, M8, has a thickness of 3.3 μm, and the thickness of M7 is 0.8 μm. The maximum oscillation frequency, fmax, of the MOS transistors with the minimum channel length of 40 nm is about 230 GHz. The passive components in the full layout, like inductors, intercon-necting lines, and transformers, are divided into three parts, which are imported in HFSS to conduct the E-M simulations, respectively. The ground plane consists of M1 and M2 for less loss. The active transistors are extracted with parasitic resistances and capacitances by the StarRC tool for the fully post-simulations.

The receiver’s chip photograph is shown in Figure 14. The LNA and mixer occupy a core area of 1 × 0.38 mm2, while the size of the VCO is 0.59 × 0.59 mm2. The LNA consumes a DC power of 24 mW from a 0.8-V supply, and the mixer consumes 9.2 mW from a 1.2-V supply. The core of the VCO circuit dissipates 33 mW from a 1.2-V supply.

With the network analyzer, the input return loss is measured, as shown in Figure 15. It is observed that the measured S11 has a deviation to higher frequencies. The deviation mainly results from the transistor model inaccuracy in high frequencies. The RF signal is provided by a signal source and a 6× frequency multiplier, while the on-chip VCO offers the LO signal. The measurement setup of the NF is depicted in Figure 16, in which a SAGE E-band noise source is utilized. The conversion gain and SSB NF results of the receiver with IF = 1 GHz are demonstrated in Figure 17. The buffer loss, about 3.5 dB, is de-em-bedded. Then, a maximum conversion gain of 34 dB and a minimum NF of 10.66 dB are obtained. At 77 GHz, the achieved conversion gain and SSB NF are 32 and 11.83 dB. The measurements are generally consistent with the simulation results. Due to the model in-accuracy in the desired frequencies, the conversion gain has a peak at a higher frequency. Correspondingly, the minimum NF of 10.66 dB is realized at the same frequency; some NF deviations relate to the input impedance deviations. Additionally, the measured OP1dB at 77 GHz is about −8 dBm, as shown in Figure 18.

Figure 14. The chip photograph of the receiver. Figure 14. The chip photograph of the receiver.

With the network analyzer, the input return loss is measured, as shown in Figure 15.It is observed that the measured S11 has a deviation to higher frequencies. The deviationmainly results from the transistor model inaccuracy in high frequencies. The RF signalis provided by a signal source and a 6× frequency multiplier, while the on-chip VCOoffers the LO signal. The measurement setup of the NF is depicted in Figure 16, in whicha SAGE E-band noise source is utilized. The conversion gain and SSB NF results of thereceiver with IF = 1 GHz are demonstrated in Figure 17. The buffer loss, about 3.5 dB, isde-embedded. Then, a maximum conversion gain of 34 dB and a minimum NF of 10.66 dBare obtained. At 77 GHz, the achieved conversion gain and SSB NF are 32 and 11.83 dB.

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The measurements are generally consistent with the simulation results. Due to the modelinaccuracy in the desired frequencies, the conversion gain has a peak at a higher frequency.Correspondingly, the minimum NF of 10.66 dB is realized at the same frequency; some NFdeviations relate to the input impedance deviations. Additionally, the measured OP1dB at77 GHz is about −8 dBm, as shown in Figure 18.

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Figure 15. The return loss of the receiver.

Figure 16. The NF measurement setup for the receiver.

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Figure 15. The return loss of the receiver.

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Figure 15. The return loss of the receiver.

Figure 16. The NF measurement setup for the receiver.

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Figure 16. The NF measurement setup for the receiver.

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Figure 17. The conversion gain and NF measurement results.

Figure 18. The conversion gain and NF measurement results.

The VCO is measured by the spectrum analyzer FSW85. A tuning range from 70.5 to 78.2 GHz, i.e., a 10.4% fractional range, is achieved, as shown in Figure 19. Meanwhile, the phase noise at 1 MHz offset frequency is −91.8~−93.48 dBc/Hz, and the phase noise of 77.74 GHz is shown in Figure 20. The phase noise measurements are bigger than the simulated results by 1~2 dB.

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Figure 17. The conversion gain and NF measurement results.

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Figure 17. The conversion gain and NF measurement results.

Figure 18. The conversion gain and NF measurement results.

The VCO is measured by the spectrum analyzer FSW85. A tuning range from 70.5 to 78.2 GHz, i.e., a 10.4% fractional range, is achieved, as shown in Figure 19. Meanwhile, the phase noise at 1 MHz offset frequency is −91.8~−93.48 dBc/Hz, and the phase noise of 77.74 GHz is shown in Figure 20. The phase noise measurements are bigger than the simulated results by 1~2 dB.

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Figure 18. The conversion gain and NF measurement results.

The VCO is measured by the spectrum analyzer FSW85. A tuning range from 70.5 to78.2 GHz, i.e., a 10.4% fractional range, is achieved, as shown in Figure 19. Meanwhile,the phase noise at 1 MHz offset frequency is −91.8~−93.48 dBc/Hz, and the phase noiseof 77.74 GHz is shown in Figure 20. The phase noise measurements are bigger than thesimulated results by 1~2 dB.

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The performance comparison of the receiver with other designs is shown in Table 1.This work achieves a relatively high conversion gain and a relatively low NF. The highgain and low noise receiver is applicable to the long-range radar sensor.

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The performance comparison of the receiver with other designs is shown in Table 1. This work achieves a relatively high conversion gain and a relatively low NF. The high gain and low noise receiver is applicable to the long-range radar sensor.

Figure 19. The measured phase noise at 77.74 GHz.

Figure 20. The tuning range of the on-chip VCO.

Table 1. Performance comparison with other receiver designs.

Reference [1] [2] [3] [4] [5] This Work Technology 90 nm 65 nm 65 nm 28 nm 65 nm 40 nm

Frequency (GHz) 77 77 77 75 83 77 Conversion Gain (dB)

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Figure 19. The measured phase noise at 77.74 GHz.

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The performance comparison of the receiver with other designs is shown in Table 1. This work achieves a relatively high conversion gain and a relatively low NF. The high gain and low noise receiver is applicable to the long-range radar sensor.

Figure 19. The measured phase noise at 77.74 GHz.

Figure 20. The tuning range of the on-chip VCO.

Table 1. Performance comparison with other receiver designs.

Reference [1] [2] [3] [4] [5] This Work Technology 90 nm 65 nm 65 nm 28 nm 65 nm 40 nm

Frequency (GHz) 77 77 77 75 83 77 Conversion Gain (dB)

16 23 13 28 45 32

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Figure 20. The tuning range of the on-chip VCO.

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Table 1. Performance comparison with other receiver designs.

Reference [1] [2] [3] [4] [5] This Work

Technology 90 nm 65 nm 65 nm 28 nm 65 nm 40 nmFrequency

(GHz) 77 77 77 75 83 77

ConversionGain (dB) 16 23 13 28 45 32

Noise Figure(dB) 13 14.8 7.95 1 8.3 15 11.83

OP1dB (dBm) −5 N.A. −13 3 N.A. −8DC Power

(mW) 28.5 27 25.8 77.3 2 120 3 32.4/132.7 3

Chip Area(mm2) 0.88 × 2.65 0.95 × 1.1 4 0.91 × 1.46 5 1.76 × 0.62 1 4 0.59 × 1

Topologies(LNA/Mixer)

Single-ended/Subharmonic

Single-ended/Single-

balanced

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balanced

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Differential/Single-

balanced

Differential/Double-

balanced1 LNA NF; 2 including IF amplifiers; 3 total power; 4 total TRx; 5 total Rx.

4. Conclusions

A 77 GHz receiver based on a 40-nm CMOS technology is implemented in this paper.The proposed neutralization technique makes better use of the active devices than theclassic neutralization technique, thus enhancing the conversion gain. Meanwhile, theproposed mixer largely reduces the flicker noise contribution. Measurement results showthat a conversion gain of 32 dB and a SSB NF of 11.83 dB are achieved at 77 GHz. The LOsignal is provided by an on-chip VCO with a 10.4% tuning range and good phase noiseperformance. Compared with other designs, this work realizes a high conversion gain anda low NF, which is suitable for long-range radar applications.

Author Contributions: Conceptualization, S.C.; methodology, S.C.; validation, S.C., L.L.; formalanalysis, S.C.; writing—original draft preparation, S.C. and L.L.; writing—review and editing, N.M.;supervision, Z.Z. All authors have read and agreed to the published version of the manuscript.

Funding: This research received no external funding.

Acknowledgments: Authors acknowledge Shanghai Integrated Circuit Research and DevelopmentCenter Ltd. for technical supports.

Conflicts of Interest: The authors declare no conflict of interest.

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