A 600MS/s 30mW 0.13µm CMOS ADC Array Achieving over 60dB SFDR with Adaptive Digital Equalization • Time-interleaved ADC array – High sampling rate, low power – Channel mismatch errors • Offset, gain, linearity and skew • Approaches – Correlation, statistics, and Chopping • Slow convergence, involved analog path, ad-hoc solutions – Equalization • Fast convergence, digital post-processing, systematic solution
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A 600MS/s 30mW 0.13µm CMOS ADC Array Achieving over 60dB SFDR with Adaptive Digital Equalization
A 600MS/s 30mW 0.13µm CMOS ADC Array Achieving over 60dB SFDR with Adaptive Digital Equalization. Time-interleaved ADC array High sampling rate, low power Channel mismatch errors Offset, gain, linearity and skew Approaches Correlation, statistics, and Chopping - PowerPoint PPT Presentation
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A 600MS/s 30mW 0.13µm CMOS ADC Array Achieving over 60dB SFDR with
Adaptive Digital Equalization
• Time-interleaved ADC array– High sampling rate, low power – Channel mismatch errors
• Offset, gain, linearity and skew
• Approaches– Correlation, statistics, and Chopping
• Slow convergence, involved analog path, ad-hoc solutions
– Equalization• Fast convergence, digital post-processing, systematic