A 400MHz Direct Digital Synthesizer with the AD9912 · DDS is a device capable of digitally generating sinusoidal waves with programmable frequency and phase. ferrite bead is a passive

A 400MHz

Direct Digital Synthesizer

with the AD9912

Daniel Da [email protected]

Brendan [email protected]

Project Sponser:Dr. Kirk W. Madison

Project 1160Engineering Physics 479

The University of British Columbia

January 9, 2012

Part I

Design and Fabrication of theDevice

i

Executive Summary

Part I of this report discusses the design and and fabrication stage of this project. At time of writing,testing is on hold while a complete prototype device has been assembled. Part II will follow and willinclude documentation the testing procedures, the results and all recommendations.

This project aimed to design, build and test a complete and functional Direct Digital Synthesizer(DDS) device with output frequencies of up to 400MHz. A DDS is a device capable of digitallygenerating sinusoidal waves with programmable frequency and phase. The Analog Devices 9912(AD9912) was chosen as a suitable DDS Integrated Circuit (IC) and this was used in the projectdesign. An enclosure also had to be built to house the DDS device.

The device had to be compatible with an existing parallel control interface used in the lab,requiring a parallel-to-serial converter, as the AD9912 requires a serial interface. This parallel-to-serial converter was designed and prototyped on a breadboard to verify correct operation.

It was also necessary for the device to minimize noise. This was accomplished with a passiveanalog filter circuit that was simulated in SPICE and confirmed to meet design specifications.

Complete designs and fabrication files for the circuit and enclosure had to be provided. Theschematics for the board were completed and a PCB layout was designed from this schematic. ThePCB layout generated all files required for manufacturing. The enclosure was modified from anexisting design to better accommodate the PCB layout and to improve heat dissipation.

Twenty PCBs had to be manufactured and parts had to be ordered for 15 boards. These haveall arrived and a prototype device is currently being assembled. Enclosures for 15 boards also hadto be ordered and these are all currently being manufactured.

ii

Contents

Executive Summary ii

Contents iv

List of Figures vi

List of Tables vii

Glossary viii

Acronyms ix

Acknowledgements x

1 Introduction 1

2 Discussion 42.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1.1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1.2 The AD9912 Direct Digital Synthesizer . . . . . . . . . . . . . . . . . . . . . 4

2.1.2.1 DAC Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . 62.1.3 RF Output and the Reconstruction Filter . . . . . . . . . . . . . . . . . . . . 6

2.1.3.1 SPICE Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1.4 Clock Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1.5 Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.5.1 SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1.5.2 SYSCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1.5.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.6 Digital Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1.6.1 The UTBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.1.6.2 The AD9912’s Serial Control Port . . . . . . . . . . . . . . . . . . . 112.1.6.3 Parallel-to-Serial Converter . . . . . . . . . . . . . . . . . . . . . . . 122.1.6.4 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.7 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2 PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.1 Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2.2 Power Plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2.3 Heat Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.2.4 Characteristic Impedance and Trace Width . . . . . . . . . . . . . . . . . . . 15

2.3 Design and Fabrication Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.3.1 Schematic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.3.2 PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.3.3 PCB Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

iii

CONTENTS iv

2.3.4 Enclosures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.4 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.4.1 Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.4.2 DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.4.3 Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.4.3.1 SYSCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.4.3.2 SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.4.3.3 SCLK Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.4.3.4 CMOS Clock Driver Voltage . . . . . . . . . . . . . . . . . . . . . . 252.4.3.5 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.4.3.6 RF Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.5 Breadboard Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3 Conclusions 29

4 Project Deliverables 304.1 List of Deliverables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304.2 Financial Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

References 32

A Schematic Diagrams 33

B PCB Fabrication Drawings 43

C 3D PCB Renderings 48

D PCB Parts List 51

List of Figures

1.1 Photo of the 150MHz AD9852-based DDS . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1 Block diagram of the full DDS device, showing input and outputs. . . . . . . . . . . 52.2 Block diagram showing internal functionality of the AD9912. . . . . . . . . . . . . . 62.3 Reconstruction filter schematic used for SPICE simulation. . . . . . . . . . . . . . . 72.4 Reconstruction filter transfer function generated from SPICE simulation. . . . . . . 82.5 Diagram of the 50-Pin UTBus Connector . . . . . . . . . . . . . . . . . . . . . . . . 102.6 Timing diagram for the UTBus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.7 The PCB power plane design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.8 Diagram of microstrip trace geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . 162.9 Diagram of stripline trace geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.10 PCB layout, top side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.11 PCB layout, bottom side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.12 Device Assembly diagram, top side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.13 Device Assembly diagram, bottom side. . . . . . . . . . . . . . . . . . . . . . . . . . 192.14 Photo of the PCB, top side. Some components have been installed. . . . . . . . . . . 202.15 Photo of the PCB, bottom side, no components. . . . . . . . . . . . . . . . . . . . . 212.16 Labelled diagram of the enclosure body. . . . . . . . . . . . . . . . . . . . . . . . . . 222.17 Diagram of the enclosure lid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.18 3D rendering of the enclosure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232.19 Parallel-to-serial converter breadboard test results. . . . . . . . . . . . . . . . . . . . 28

A.1 Schematic diagram, top level. Top Level.SchDoc . . . . . . . . . . . . . . . . . . . . 33A.2 Schematic diagram, clocks. CLK.SchDoc . . . . . . . . . . . . . . . . . . . . . . . . . 34A.3 Schematic diagram, digital. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35A.4 Schematic diagram, flip-flops and board select comparator. . . . . . . . . . . . . . . 36A.5 Schematic diagram, parallel-to-serial converter. . . . . . . . . . . . . . . . . . . . . . 37A.6 Schematic diagram, AD9912. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38A.7 Schematic diagram, power 1 (voltage regulators). . . . . . . . . . . . . . . . . . . . . 39A.8 Schematic diagram, power 2 (bypass capacitors and ferrite beads). . . . . . . . . . . 40A.9 Schematic diagram, analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41A.10 Schematic diagram, reconstruction filter. . . . . . . . . . . . . . . . . . . . . . . . . . 42

B.1 Fabrication Drawings, top copper layer. . . . . . . . . . . . . . . . . . . . . . . . . . 43B.2 Fabrication Drawings, ground plane (negative). . . . . . . . . . . . . . . . . . . . . . 44B.3 Fabrication Drawings, power plane (negative). . . . . . . . . . . . . . . . . . . . . . . 44B.4 Fabrication Drawings, bottom copper layer. . . . . . . . . . . . . . . . . . . . . . . . 45B.5 Fabrication Drawings, top silkscreen. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45B.6 Fabrication Drawings, bottom silkscreen. . . . . . . . . . . . . . . . . . . . . . . . . . 46B.7 Fabrication Drawings, top soldermask. . . . . . . . . . . . . . . . . . . . . . . . . . . 46B.8 Fabrication Drawings, bottom soldermask. . . . . . . . . . . . . . . . . . . . . . . . . 47B.9 Fabrication Drawings, drill drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

v

LIST OF FIGURES vi

C.1 3D Rendering of the DDS, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48C.2 3D Rendering of the DDS, bottom view. . . . . . . . . . . . . . . . . . . . . . . . . . 49C.3 3D Rendering of the DDS, angled view. . . . . . . . . . . . . . . . . . . . . . . . . . 50

List of Tables

2.1 Serial control port instruction word bit functionality. . . . . . . . . . . . . . . . . . . 112.2 AD9912 byte transfer count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.3 Sample DDS Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.4 List of connection pads available on the Printed Circuit Board (PCB) designed for

BNC Connector mounting. Note that only J3, J5 and J6 are intended for massproduction, and the enclosure design reflects this. . . . . . . . . . . . . . . . . . . . . 24

2.5 Options for Power-Up Default Frequencies on the AD9912 . . . . . . . . . . . . . . . 252.6 Recommended Loop Filter Values for a Nominal 1.5 MHz SYSCLK PLL Loop Band-

width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.7 Device Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1 Financial Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314.2 DDS Enclosure Costs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

D.1 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

vii

Glossary

AD9852 is a DDS IC produced by Analog Devices, with a maximum system clock of 300MHz.

AD9912 is Analog Devices’ highest-performance DDS IC, with a maximum system clock of 1GHz.

DDS is a device capable of digitally generating sinusoidal waves with programmable frequency andphase.

ferrite bead is a passive component which is primarily resistive at high frequencies. Therefore,they act to block high-frequency noise and are useful as an inexpensive means of isolatingnoisy power supply groups.

FSC is a digitally programmable 10-bit scale factor that sets the peak output current of the AD9912Digital-to-Analog Converter (DAC)[3].

prepreg is a shorthand term for pre-impregnated material. In this report, it is a name for thedielectric material placed between copper layers on a PCB.

via is a connection between one or more copper layers on a PCB.

viii

Acronyms

CSB Chip Select Bit.

DAC Digital-to-Analog Converter.

DAQ Data Acquisition System.

DIP Dual In-line Package.

EMI Electromagnetic Interference.

FTW Frequency Tuning Word.

IC Integrated Circuit.

LDO Low-Dropout.

NI National Instruments.

PCB Printed Circuit Board.

PHAS Department of Physics and Astronomy.

PLL Phase-Locked Loop.

QDG Quantum Degenerate Gasses.

SMD Surface-Mount Devices.

UTBus University of Texas Bus.

VCO Voltage-Controlled Oscillator.

ix

Acknowledgements

We’d like to thank Kirk Madison and Jon Nakane for taking their time to review our in-progressdesigns. Extra thanks to Kirk having enough confidence in us amateur PCB designers to fund theproject. Thanks to Will Gunton for being our reliable contact at the QDG lab and for administratingthe purchasing for the project. Thanks to Pavel Trochtchanovitch, Richard, Gar and Dave at thePHAS electronics shop for assembling our boards and having patience when our instructions didn’tmake sense. Extra thanks to Richard for spending time on several occasions to review out PCBlayout.

x

1

Introduction

The Quantum Degenerate Gasses (QDG) Laboratory at the University of British Columbia inves-tigates the applications of ultra-cold gases to the physics of many-body quantum systems [8]. Onesuch investigation attempts to trap, isolate and precisely control the movement of ultra-cold atoms.

Naturally, this experiment requires precise control of experimental conditions. To achieve this,they employ a complex computer-controlled electronic system. Contained within this control systemare several devices called Direct Digital Synthesizer (DDS)s. The current generation of these devicesare designed by Todd Meyrath and are capable of producing radio frequency signals between DCand 135MHz [9]. Todd Meyrath’s device is shown in Figure 1.1. The DDSs are based around theAnalog Devices 9852 (AD9852), a highly integrated 300MBPS CMOS digital synthesizer. This ICprovides a highly stable frequency-, phase-, and amplitude-programmable cosine output[2].

Other key features of the AD9852 are the ability to internally multiply an external clock up toa maximum of 300MHz (20 × 15MHz) and an output update of speed up to 108Hz. The AD9852supports Phase-Shift Keying (PSK) and Frequency-Shift Keying (FSK), which allow switching be-tween two pre-programmed phases or frequencies based upon the level of a digital signal. Further,a high-speed integrated analog comparator allows the AD9852 to be used as a programmable clocksource.

The QDG lab requires eight devices capable of analog sinusoidal outputs with programmablefrequencies of up to 400MHz. These devices will be used to control acousto-optic modulators, whichcan be used to precisely control the frequency of the laser beams. The QDG lab uses these lasers tocontrol ultra-cold atoms in experiments that are beyond the scope of this document.

To fit the lab requirements, this project aims to redesign, implement and test a new DDS device,the AD9912, which replaces the AD9852 microchip with a similar chip, the AD9912. This IC is anewer and faster edition of the AD9852 - a 1GBPS digital synthesizer capable of producing radiofrequency signals at frequencies of up to 400MHz and an output update speed of up to 2MHz. Tosimplify usage in the lab, the AD9912-based DDS device must support the existing AD9852 DDSdevice control interface.

As the AD9912 is a faster IC than the AD9852, it has several requirements that make a designingan AD9912-based DDS device more challenging. For example, the higher speed signals involvedrequire much more careful impedance control of the signal lines than the AD9852 DDS devices.There are feature differences as well: the AD9912 does not support PSK or FSK, though the AD9852does, and supports serial programming in place of a parallel control bus. The AD9912 also requiresvoltage supplies at 1.8V on top of the 3.3V the AD9852 required. Like the AD9852, the AD9912’soutput must be filtered to remove noise resulting from the digital synthesis process; this filter mustbe designed and characterized.

Due to these differences, the design for DDS device built for this project did not begin with theAD9852 DDS device. Instead, the design began with the AD9912 evaluation board. This is evidentin the analog portion of the AD9912 DDS device, which uses similar structure and componentschoice as the evaluation board. However, the AD9912 DDS device did draw inspirations from theAD9852 device[9]. In particular, the digital control and power circuitry design is heavily based upon

1

1. INTRODUCTION 2

the AD9852 device and the overall PCB layout is very similar.To house the DDS device, an enclosure must be designed. This should securely fasten the AD9912

DDS device, provide noise isolation and be compatible with the rack mount solution used for theAD9852. Both the enclosures and the front panel mounting mechanism should be ordered.

This project is sponsored by Dr. Kirk Madison, Assistant Professor with the department ofPhysics and Astronomy at The University of British Columbia and head of the QDG Laboratory.

This report is organized into several chapters: Discussion, Conclusions and Project Deliverables.A chapter on recommendations will be included with Part II of this report. The Discussion isbroken into Theory of Operation, PCB Layout Considerations, Design and Fabrication Methods,Board Features and Breadboard Testing. The Discussion aims to provide a quantitative descriptionof the expected operation of the device and give insight into the methodology of the design process.The Conclusions provide closure to the report, summarise the important results and findings. TheProject Deliverables describe the physical and electronic results of this project which are to be handedover to the QDG Laboratory. Finally, the Appendices present the design schematics, fabricationdrawings, 3D renderings of the PCB and a full parts list.

1. INTRODUCTION 3

Figure 1.1: Photo of the 150MHz AD9852-based DDS designed by Todd Meyrath[9].

2

Discussion

2.1 Theory of Operation

This section will begin by giving an overview of the functionality of the device. Next, the internalworkings of the AD9912 IC itself will be discussed, providing an understanding what to expect fromthe IC’s RF and clock outputs. Afterwards the supporting circuitry will be described block by block,returning as needed to the AD9912 IC to explain related concepts.

2.1.1 Device Overview

The device is designed to generate a sinusoidal or square output signal with a frequency of up to400MHz. The frequency and phase of both output signals can be rapidly digitally programmed (butnot independently). The output signal is generated by the AD9912, a high-performance, low-noise14-bit DDS[3].

The sinusoidal output is filtered through a 400MHz low-pass filter to remove unwanted high-frequency noise. Depending on board configuration, the filtered RF signal can then be taken asthe primary device output or it can be brought back to the AD9912 to become the input signal foreither of the AD9912’s two clock drivers - the CMOS output driver and the HSTL output driver(see Section 2.1.4).

Figure 2.1 is a high-level block diagram of the newly designed AD9912-based DDS device. Theblock diagram shows all existing BNC connection pads. Only three of these are intended for use inthe finished devices. These are SYSCLK, the system clock input, RF, the sinusoidal signal outputand CMOS, the CMOS clock driver output. The remaining connections are intended primarily fortesting.

Significant omissions from the block diagram are the Phase-Locked Loop (PLL) loop filter (seeSection 2.1.5.3) and the voltage regulation circuitry (see Section 2.2.2).

2.1.2 The AD9912 Direct Digital Synthesizer

Figure 2.2 is a block diagram showing the core internal functionality of the AD9912, reproducedfrom the datasheet[3]. This diagram consists of three main blocks: the 48-bit accumulator, angle toamplitude conversion and the DAC. fs is the DAC sample rate[3].

Each cycle of fs, the accumulator increments its running total by the 48-bit value of the FrequencyTuning Word (FTW)[3]. The accumulator will periodically reach its maximum value (248) and rollover. The rate of roll over is equal to the frequency of the sinusoidal output, fDDS , and is given by

fDDS =FTW

248fs[3]. (2.1)

Equation 2.1 can be solved to give

FTW = round(248(fDDS

fs))[3]. (2.2)

4

2. DISCUSSION 5

AD9912

RF

Reconstruction Filter

(400 MHz Low-Pass)

DAC_OUT

FDBK_IN

OUT_P

OUT_N

CMOS

SYSCLK

OUT/OUTB

OUT_CMOS

FDBK_IN/

FDBK_INB

DAC_OUT/

DAC_OUTB

SYSCLK/

SYSCLKB

SDIO

SCLK

Clock

Oscillator

(~25MHz)

Board

Address

Comparator

Parallel-to-

Serial

Converter

Parallel Data

Input

Address

Data

Strobe

10-Pos DIP Switch

Startup

Config

Board

Address

46

616

SZCSB

SCLK

Figure 2.1: Block diagram of the full DDS device, showing input and outputs. Switches are imple-mented as 0Ω resistors. The crystal oscillator shown is optional and replaces the external SYSCLKinput.

The output of the accumulator is offset by the 14-bit value Phase Offset. This results in a phaseoffset to fDDS of ∆Φ given by

∆Φ = 2π(∆phase

214)[3]. (2.3)

Both the FTW and the Phase Offset can be digitally controlled by the user (see Section 2.1.6),allowing the frequency and phase of the output sinusoid to be controlled with 48 and 14 bits ofprecision, respectively. This corresponds to increments of approximately 3.6µHz (at fs = 1GHz)and 3.8× 10−4rads.

After the phase offset, the accumulator output (which is a digital representation of the phase ofthe output sinusoid) is converted to a 14-bit digital value representing the amplitude of the outputsinusoid. The DAC then converts this value to an analog differential signal pair (DAC OUT/DAC OUTB). The frequency, phase and peak output current (see Section 2.1.2.1) of this signal aredigitally controllable. It will be transformed into a single-ended signal and low-pass filtered (seeSection 2.1.3) before becoming the output RF signal of the DDS device.

2. DISCUSSION 6

2.1.2.1 DAC Peak Output Current

The peak output current of the DAC is determined by two factors: a reference current on theDAC RSET pin (IDAC RESET ) and a digitally programmable 10-bit scale factor referred to as theFSC[3]. The DAC RSET pin is internally connected to a reference voltage of 1.2V and externallyconnected to ground through the resistor RDAC REF (R26 on the PCB), and therefore

IDAC REF =1.2V

RDAC REF[3]. (2.4)

The AD9912 datasheet recommends IDAC REF = 120µA which implies taking RDAC REF =10kΩ.

The DAC full-scale output current (IDAC FS) is given by

IDAC FS = IDAC REF (72 +192FSC

1024)[3]. (2.5)

Digital control of the FSC allows the DAC output current to be digitally controlled in incrementsof 0.1875µA from a minimum of 8.64µA to a maximum of 31.68µA1.

Figure 2.2: Block diagram showing internal functionality of the AD9912, reproduced from thedatasheet[3].

2.1.3 RF Output and the Reconstruction Filter

The AD9912’s DAC produces a sampled reconstruction of the desired sinusoidal signal. A basicresult in Fourier Analysis says that this reconstructed signal contains both the desired basebandsignal, extending from DC to the Nyquist frequency (fs/2), as well as images of this baseband signalwhich appear periodically at intervals of fs/2 and theoretically extend to infinity[3].

Note that the first unwanted image is that of the baseband signal, mirrored about fs/2. Thismeans that as the DDS output frequency is increased, the frequency of the fundamental spur inthe first image decreases. For example, if the DDS output frequency is 400MHz, the first spur willappear at 600MHz. At an output frequency of 490MHz, the first spur will appear at 510MHz. Soas the output frequency increases, the requirements on the filter become more stringent. The resultis a practical limitation on the DDS output frequency which is less than the Nyquist frequency offs/2. The actual limit will depend upon the properties of the filter used and the requirements ofthe application.

Our application desires only the baseband signal, and therefore the DAC output must be low-passfiltered to remove higher frequency noise. This filter is referred to as the reconstruction filter. It isdesired that this filter have a cut-off frequency of 400MHz, as steep a roll-off as possible (rejectionat 500MHz is desired) and very good rejection in the stop-band (60dB attenuation at a minimum).

1This follows from Equation 2.4. Comparably, the datasheet’s AC specifications table gives the DAC’s typical andmaximum full-scale output current as 20µA and 31µA, respectively.

2. DISCUSSION 7

Following from the AD9912 evaluation board design, a 50Ω surface mount RF transformer(ADT2-1T-1P+, Mini-Circuits) is used to transform the differential signal pair of Figure 2.2 (DAC OUT/DAC OUTB) into a single-ended signal prior to filtering[4]. A single-ended filter design is less sus-ceptible to component variations than its differential counterpart[4]. A differential filter design mightbe more appealing to users who were only interested in the clock generation feature of the AD9912(see Section 2.1.4), not the RF output, since no transformers would be required. However, ourapplication requires a single-ended RF output, and so one the transformer would still be required.Note that the RF transformers have a (7× 8)mm2 footprint and cost approximately $4.25.

Note that since transformers do not function at low frequencies, the RF output will be attenuatedat very low frequencies and will not function near DC2. The ADT2-1T-1P+ RF transformers arerated for frequencies in the range of 8 to 600 MHz.

The reconstruction filter design is based on that of the AD9912 evaluation board, Rev. B3. It isa 7th-order passive elliptic low-pass filter, shown in Figure 2.3.

2.1.3.1 SPICE Verification

The reconstruction filter design was verified through a SPICE simulation (AC Analysis in NI Mul-tiSim v11.0). Figure 2.3 shows the schematic used for SPICE simulation and Figure 2.4 shows theresulting transfer function.

As we can see from the transfer function, the cut-off frequency is 400MHz, the roll-off occurs in100MHz and the stop-band attenuation is about 60dB. The data used to generate the plot showsthat the pass-band ripple is a maximum of about 1.5dB.

Figure 2.3: Reconstruction filter schematic used for SPICE simulation. This is a 7th order ellipticlow-pass filter with a 400MHz cut-off frequency. Designators were taken to match the PCB.

2.1.4 Clock Drivers

The AD9912 has two on-board clock drivers, the CMOS output driver and the HSTL output driver.These clock drivers share the differential FDBK IN/FDBK INB inputs and effectively serve to trans-form the filtered sinusoidal DAC output into a square clock signal. A second ADT2-1T-1P+ RF

2This is not a concern for the QDG lab, as the existing AD9852-based devices function at frequencies from DC to135MHz[9].

3Rev. A uses a 240 MHz low-pass filter with very similar design.

2. DISCUSSION 8

0 100 200 300 400 500 600 700 800 900 100011001200130014001500−120

−100

−80

−60

−40

−20

0

Mag

nitu

de (

dB)

Frequency (MHz)

Magnitude Plot

0 100 200 300 400 500 600 700 800 900 100011001200130014001500−180−135−90−45

04590

135180

Pha

se (

deg)

Frequency (MHz)

Phase Plot

Figure 2.4: Reconstruction filter frequency-domain transfer function generated from a SPICE sim-ulation of the circuit shown in Figure 2.3

transformer is used to transform the single-ended filter output into a differential signal suitable forthe FDBK IN/FDBK INB inputs.

The CMOS output driver provides a CMOS-level clock signal and is suitable for frequenciesin the range 8kHz to 150MHz[3]. The device can be configured at component population to havea CMOS voltage of either 3.3V or 1.8V (see Section 2.4). The CMOS output driver includes aninteger divider which can be enabled or bypassed. When bypassed, the CMOS output frequency isthe same as the signal on the FDBK IN/FDBK INB inputs. When enabled, this frequency can bereduced. At frequencies below 30MHz, noise on the CMOS output can be reduced by enabling theCMOS divider and running the DAC at a higher frequency[3]. See the AD9912 datasheet for moreinformation.

The HSTL output driver provides a 1.8V differential clock signal and is suitable for frequenciesin the range 20MHz to 725MHz[3]. Frequencies above the Nyquist rate fo the AD9912 are achievedwith a 2× frequency multiplier. The datasheet claims a duty cycle between 48% and 52%, while theCMOS driver’s duty cycle is given as being between 45% and 55%. Note that unlike the AD9852,the AD9912 does not support digital control of the duty cycle of the output clock.

2.1.5 Clock Inputs

The DDS device has two clocks on-board. These are referred to as SYSCLK and SCLK. SYSCLKdrives fs, the internal DAC sample rate of the AD9912. The frequency of fs is directly proportionalto the output frequency of the DDS. If PLL is enabled on the AD9912, fs can be made to havea frequency up to 66 times greater than that of SYSCLK. SCLK is the digital control clock andcontrols the frequency of the AD9912’s serial control interface.

2. DISCUSSION 9

2.1.5.1 SCLK

SCLK controls the frequency of the AD9912’s serial control input. This clock is also used to convertthe incoming digital programming parallel signal into the serial signal used by the AD9912. Ourimplementation allows for two possible sources for SCLK: an external connection and an on-boardclock oscillator (TXC 7C Series). The external connection is intended for testing purposes, particu-larly to determine the maximum frequency at which the serial input can reliably operate (see nextparagraph). Once this frequency has been determined, an appropriately selected TXC 7C IC willbe placed on board and used as SCLK.

An important note is that the TXC 7C datasheet does not specify whether the enable pin isactive high or active low. The board includes jumpers to allow for both possibilities; see Section 2.4for information on switching between these two options.

According to the AD9912 datasheet SCLK is limited to a maximum of 50MHz[3]. However, themaximum value of SCLK will likely be limited by the digital control logic and not the AD9912.Timing analysis based upon information in all relevant components’ datasheets suggests that themaximum SCLK frequency should be around 25MHz; see Section 2.1.6 for details.

2.1.5.2 SYSCLK

SYSCLK is the main system clock. The DAC sample rate, fs, is controlled by SYSCLK. As discussedbelow, the AD9912 has PLL multiplier circuitry which allows fs to be up to 66 times greater thanthe frequency of SYSCLK. From the AD9912 datasheet, fs is limited to a maximum of 1GHz, sothe SYSCLK and PLL multiplier must be carefully chosen to be less than this speed[3].

The AD9912 supports the use of either a crystal oscillator or a clock oscillator; the DDS devicesupports both an on-board crystal oscillator and an external clock source (recommended). Dependingon which is to be used, the jumpers necessary to connect the clock source or crystal oscillator to theAD9912 must be installed; see Table 2.7.

2.1.5.3 PLL

The AD9912’s PLL circuitry allows the frequency of SYSCLK to be increased by any even multiplebetween 4 and 66. This circuitry generates an internal clock using a Voltage-Controlled Oscillator(VCO). The voltage that controls the VCO is generated by a current pump and an external loopfilter consisting of components defined in Table 2.6 and is related to the phase difference betweenthe internal clock, divided by a number set by the PLL register, and the SYSCLK. The voltage thenraises and lowers to converge the internal clock on a set multiple of the SYSCLK[3].

The AD9912 PLL also includes a frequency doubler before the PLL circuitry itself. This func-tionality creates a clock pulse on both the rising and falling edge of SYSCLK, doubling the frequency.Using the frequency doubler creates a clock output that has an improved phase noise performanceover simply using double the PLL multiplier instead. Unfortunately, the frequency doubler does notproduce a clean rectangular pulse with constant duty cycle. That is, subharmonics are introduced atmultiples of the SYSCLK input frequency. The PLL multiplier should be chosen to suppress thesesubharmonics[3].

Using the PLL allows for a slower clock to be used as the input to the DDS device. Slower clocksources are much cheaper and easier to acquire. However, the PLL will introduce additional noiseand inaccuracy into the system, especially as the PLL multiplier approaches the maximum of 66×.

The ideal configuration of the PLL loop filter depends on the multiplier to be used. If PLL is tobypassed, then the loop filter can also be bypassed. See Section 2.4 for details.

2.1.6 Digital Control

The devices are controlled through an existing parallel interface called the University of Texas Bus(UTBus). Custom circuitry on board our devices has been designed to interface the parallel UTBuswith the AD9912’s serial control port. This section will describe the UTBus, the serial control portand the custom interface between the two.

2. DISCUSSION 10

2.1.6.1 The UTBus

The UTBus is an existing parallel programming interface used by the QDG lab and based uponTodd Meyrath’s work[9]. As the UTBus is already in use in the lab4, supporting this interface wasa design requirement.

The interface uses ribbon cable and a 50-pin Molex connector with pin functionality as definedin Figure 2.5. As shown, these 50 pins are divided into 25 grounded pins, 8 address bits, 16 data bitsand one additional bit, called the strobe. The 8 address bits are used to specify which device shouldreceive the 16 bit command. The strobe bit is effectively a clock with a 1/3 duty cycle; when thestrobe bit is high, the address and command are guaranteed to be stable. The UTBus address anddata pins are asserted for three distinct periods with equal length: once, while the strobe remainslow, a second time while the strobe is high, and a third time while the strobe is low[7]. These threeperiods together comprise one UTBus command. This timing is illustrated in Figure 2.6.

Figure 2.5: Diagram of the 50-Pin UTBus Connector, reproduced from [9].

Figure 2.6: Timing diagram for the UTBus, showing the strobe, address, data and NI-DAQ clock.Each command sent to a device requires three periods of the NI-DAQ clock to complete. Reproducedfrom Keith Ladouceur’s Master’s Thesis[7].

The QDG lab currently uses an NI-DAQ, controlled by a desktop computer running a custompython script, to drive the UTBus. Current uses of the UTBus send one command at a time, withan NI-DAQ clock frequency of up to 5MHz.

4The UTBus is used to control various devices in the QDG lab, including analog output devices and the existingAD9852-based DDSs[7].

2. DISCUSSION 11

2.1.6.2 The AD9912’s Serial Control Port

In contrast with the parallel programming interface of the AD9852, which was used on the previousgeneration of DDS devices, operation of the AD9912 is controlled through a serial interface. This isinconvenient from a design standpoint because the UTBus provides 16 bits of data in parallel andno suitable clock. Section 2.1.6.3 describes the hardware solution which interfaces the UTBus withthe serial control port.

A detailed discussion of the serial control port is given in the AD9912’s datasheet, includingmultiple timing diagrams. Here we summarize the essential elements.

The serial control port of the AD9912 consists of four pins: a clock (SCLK), an I/O pin (SDIO),an active-low control pin which gates the I/O cycles (Chip Select Bit (CSB)) and an output pin(SDO). SDO is unnecessary for our application and has been left unconnected on the board5.

Control of the AD9912 is established through the writing of binary data to various registers. Eachregister has a unique 13-bit address and some functionality which is documented in the datasheet.For example, the DDS output frequency can be controlled by writing to the 48-bit register containingthe FTW. Note that all registers are not equal in size.

Each communication cycle consists of two parts: the writing of a 16-bit instruction word and thereading of or writing to a register. Table 2.1 shows the 16-bits of the instructions words mappedto their corresponding bits in the UTBus. The instruction word contains a 13-bit register address(A12,. . . ,A0), two bits indicating the length of the coming data transfer (W1 and W0, see Table2.2) and a single bit indicating whether the transfer is to be a read or a write (R/W ). Note thatour device supports only only one- and two-byte transfers and does not support reads. Writing toregisters larger than two bytes will require multiple communication cycles.

Table 2.1: Serial control port instruction word bit functionality. D0,. . . ,D15 correspond toDAT0,. . . ,DAT15 in our design and schematics (see Figures A.3 and A.5). The last row correspondsto the 16 bits of the instruction word. Adapted from the AD9912 datasheet[3].MSB LSBD0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Table 2.2: Decoding of the W1 and W2 bits in an instruction sent the AD9912’s serial control port.These two bits control the number of bytes to be transferred in the current communication cycle anddescribe the number of bytes transferred in this command cycle, excluding the 2-byte instruction.W1 and W0 correspond to the DAT14 and DAT13 data bits on the UTBus, respectively. Notethat the AD9912 DDS device does not support all byte lengths. Reproduced from the AD9912datasheet[3].

W1 W0 Bytes to Transfer Supported?0 0 1 Yes0 1 2 Yes1 0 3 No1 1 Streaming mode No

The CSB must be held low in order for the AD9912 to recognize data on the SDIO. Accordingly,the CSB should be held low during writing of the instruction word. Afterwards, the CSB can remainlow and data transfer can begin immediately. Alternatively, the CSB can be brought high to disablethe serial control port until the user is ready to transfer data. Data transfer is similar: the CSB mustbe held low during the writing of each byte of data. Between each byte, the CSB can be broughthigh to pause the transfer if desired6.

5Actually, the pin itself is connected to a trace leading away from the AD9912 IC and to a via. This is to facilitatetesting.

6Streaming mode is an exception to this; during streaming mode, a rising edge on the CSB indicates the end ofthe communication cycle.

2. DISCUSSION 12

Some registers on the AD9912 are buffered so that writing to these registers does not affectthe device output until an I/O update operation is performed to transfer the data from the bufferregisters to the control registers. This can be accomplished by toggling the IO UPDATE pin or bywriting a 1 to the register update bit. To simplify the design of the interface between the UTBusand the serial control port, the IO UPDATE pin is disabled on our devices, and so the latter methodwill be used in practice. In practice, the CSB will be brought high between commands sent on theUTBus in order to stall the communication cycle and allow time for the UTBus to send the nextcommand.

2.1.6.3 Parallel-to-Serial Converter

Schematics for the parallel-to-serial converter are shown in Figures A.3, A.4 and A.5.An 8-bit comparator is used to compare bits A7 to A2 of the UTBus address bits (the lower

2 bits are not used as addresses) against the board address. The board address, which can be setusing a Dual In-line Package (DIP) switch, is a 6-bit address which should be unique for each deviceconnected to the UTBus. If the address bits match the address set on the DIP switch, a customarrangement of flip flops listens for a rising edge on the strobe bit. When this happens, a pulse isgenerated that latches the 16 bit command into two SN74HC166 8-bit shift registers. These 8-bitshift registers are daisy-chained together to form a 16-bit shift register.

Once the data is loaded in, the shift registers output the UTBus data into the AD9912’s serialport one bit at a time beginning with DAT0. The number of data bits clocked into the AD9912 isan option set by the UTBus address bus bit 1 (A1), renamed to SZ in our schematics. The SZ bitswitches between using all 16 bits of the data bus (SZ=0) or only the lower 8 bits of the data bus(SZ=1). The SZ bit will be critical when programming the AD9912; see Section 2.1.6.4.

To implement the switch between 8 and 16 bits, the DDS device design takes advantage of theCSB pin on the AD9912. Since the AD9912 can only be programmed when the CSB is held low,the DDS device ensures that the CSB is only held low for either 8 or 16 bits. This is accomplishedby using a mirrored set of SN74HC166 8 bit shift registers. These second set of shift registers areloaded with either all logic low, or 8 bits of logic low followed by 8 bits of logic high. The outputfrom these shift registers is directly connected to the CSB and is clocked out at the same time asthe shift registers containing the command. This ensures that the AD9912 is only able to receivedata on the serial port for exactly the time it takes to clock in one of 8 or 16 bits.

Parts of this circuit have been prototyped and tested; see Section 2.5. A timing diagram ispresented in this section using the data collected; see Figure 2.19.

2.1.6.4 Programming

Programming the DDS device consists of sending a series of commands on the UTBus. On eachcommand, 8 or 16 bits of data on the UTBus are clocked into the DDS one bit at a time beginningwith DAT0. The UTBus address bit A1 (renamed to SZ in our schematics) controls the length ofthe data transfer (low for a 16-bit transfer). Thus (see Section 2.1.6.2), each communication cyclewith the AD9912 requires two commands to be sent on the UTBus. The first command sent willalways be 16-bits and tells the AD9912 which register is to be written to as well as how much datais to be written (8 or 16 bits; see Table 2.2). The second command can be either 8-bits or 16-bitsand is the actual data to be written to the register addressed previously.

If the register being written is a buffered register (see Section 2.1.6.2), an additional register mustbe written to update the DDS output. This can be done immediately or after multiple registershave been written to.

If the register to be written to is larger than 16-bits, multiple communication cycles are required,as illustrated in the example below.

The following is an example of a series of commands to set the FTW to 68DB8BAC7167 (FTW

controls the output frequency; see Section 2.1.2). With fs=1GHz, this sets the AD9912 output to100MHz. The FTW is 48 bits, and so requires 3 communication cycles to completely overwrite. The

768DB8BAC716 = 0000 0000 0000 0110 1000 1101 1011 1000 1011 1010 1100 01112

2. DISCUSSION 13

fourth communication cycle shown below is a write to the I/O Update register, which causes theoutput frequency to be updated. The address and strobe bits are not shown.

Table 2.3: Sample DDS Device Commands to set the output frequency to 100MHz and subsequentlyupdate the output. The first 6 commands set the FTW to the value required for at output frequencyof 100MHz, while the last two commands tell the AD9912 to update the output.

DataSZ 0-3 4-7 8-11 12-15 Description0 0010 0001 1010 1011 Send (0) the next two bytes (01) of data to register 01AB16

(0001101010112), the register containing the top 8 bits ofthe FTW

0 0000 0000 0000 0110 Write 000000002 to register 01AB16 and 000001102 to regis-ter 01AA16

0 0010 0001 1010 1001 Send (0) the next two bytes (01) of data to register 01A916(0001101010012)

0 1000 1101 1011 1000 Write 100011012 to register 01A916 and 101110002 to regis-ter 01A816

0 0010 0001 1010 0111 Send (0) the next two bytes (01) of data to register 01A716(0001101001112)

0 1011 1010 1100 0111 Write 101110102 to register 01A716 and 110001112 to regis-ter 01A616, bits 15:8 of the FTW

0 0000 0000 0000 0101 Send (0) the next byte (00) of data to register 000516(00000000001012), the IO UPDATE register that tells theAD9912 to update the output

1 1000 0000 0000 0000 Write 1 to the 1 bit IO UPDATE register

2.1.7 Power Management

The AD9912 has stringent power requirements to ensure the highest-performance operation. Both3.3V and 1.8V power supplies are needed. While it would be possible to implement an AD9912-based device using only two power rails, the datasheet highly recommends isolation between eachgroup of power supplies on the AD9912. The extent to which isolation is required depends on therequirements of the application. See Power Supply Partitioning in the AD9912 datasheet for adetailed description of which pins can be grouped together and which should be isolated.

The isolation between power supply groups can be achieved by using separate regulators for eachgroup or by placing a ferrite bead between a common regulator and each rail. Separate voltageregulators provide better isolation but require more PCB area, increase the cost of the device8 andincrease the power consumption of the device9. Our design uses four regulators, two at each of 1.8Vand 3.3V, each separated into the broad groups analog and digital. Five ferrite beads are then usedto isolate five power supply groups, each sourcing from the 1.8V analog regulator. See the schematicsshown in Figures A.7 and A.8.

The CMOS clock driver power supply (VDD CMOS) can either be connected to the analog 3.3Vregulator through a ferrite bead (F4) or to the analog 1.8V regulator through a 0Ω jumper (W14)10,depending on the desired CMOS output voltage level.

All power pins on the AD9912 and digital logic ICs have a 0.1µF bypass capacitor connected asclose as possible to the supply connection. Bypass capacitors serve as power reservoirs, providinginstantaneous power to the IC. They prevent that power from needing to travel over a long connectionto the voltage regulator, introducing delays due to parasitic inductance of the traces involved. Instead

8The cost of each high-performance Low-Dropout (LDO) voltage regulator used was about $4.50.9This is not a significant concern for this application.

10See the datasheet for more information on the CMOS power supply recommendations. W14 uses the same 0805package as the ferrite beads, allowing a ferrite bead to be used instead of a jumper if desired.

2. DISCUSSION 14

the power comes directly from the capacitor, which is placed as close as possible to the IC in order tominimize parasitic inductance. This capacitor is then recharged by power from the voltage regulatorat a speed much closer to DC.

2.2 PCB Layout Considerations

Major sources of inspiration were the AD9912 evaluation board and Todd Meyrath’s AD9852design[9] (shown in Figure 1.1). Here we discuss the components chosen for the DDS device, theconsiderations needed for power management, techniques for managing heat and how trace widthswere chosen to ensure signal integrity.

2.2.1 Components

All parts and components used on the DDS device were selected and sourced, beginning by con-sidering the components used on either the AD9912 evaluation board or Todd Meyrath’s AD9852design[9]. Many of these parts were re-used, as reflected in the complete Bill of Materials, which isgiven in Appendix D.

For this application, Surface-Mount Devicess (SMDs) were preferred to through-hole componentsdue to reduced inductances and the possibility of higher component density, which is ideal for highfrequency design[10]. For these reasons (and following the example of the AD9912 evaluation boardand the old AD9852 DDS), most components on our board are surface-mount. There are onlythree through-hole components: the 50-pin Molex UTBus connector, the 3-pin Molex power con-nector (5V) and the 10-Pos switch (sets the board address and the AD9912 start-up configuration).Component choice for the UTBus and power connectors is compatible with those used in previousgeneration devices.

Most common passive components use either 1206 (3.2mm×1.6mm) or 0402 (1.0mm×0.51mm)surface-mount packages. The 1206 packages is preferred for its larger footprint11, but 0402 is pre-ferred near the AD9912 IC in order to shorten the trace lengths between the AD9912 IC and itsbypass capacitors12.

Most components are placed on the top side of the board. Bottom-side components are limitedto resistors, capacitors and ferrite beads.

The BNC connectors are mounted to the enclosure and solder directly to 2.54×6.35mm pads onthe PCB. This design is identical to that used in Todd Meyrath’s AD9852 design[9].

The linear regulators used for this board (Texas Instruments TPS78633 and TPS78618) wereselected due to their proven use in Todd Meyrath’s AD9852 design[9]. These are fixed-voltage 1.5ALDO voltage regulators suitable for use with a 5V supply. Four regulators are used. See Section2.1.7 for more information.

2.2.2 Power Plane

The third layer of the 4-layer PCB is a dedicated power plane, shown in Figure 2.7. This power planewas split into five regions. Around the outside perimeter of board is a 5V plane which is suppliedby the 3-pin external power connector. A 470µF tantalum capacitor near the connector stabilizesthis supply and ensures constant voltage levels. The 5V supply is used by the four on-board linearpower regulators which power the remaining four regions.

The left side of the power plane (labelled Digital 3.3V) is used to supply a 3.3V signal to thedigital components which provide the digital interface between the UTBus and the AD9912. TheDigital 3.3V power plane also provides power for the AD9912’s serial control port.

The three other power planes (Digital 1.8V, Analog 1.8V and Analog 3.3V) provide power tothe appropriate sections of the AD9912 IC. These are all required to be independently supplied and

11The small 0402 footprint requires a steady hand and some skill in order to install manually.12To reduce Electromagnetic Interference (EMI), a Texas Instruments white paper recommends that the length-to-

width ratio of traces between an IC and its voltage source should not exceed 3:1[10].

2. DISCUSSION 15

there are stringent requirements on bypass capacitors and ferrite beads, as listed by the AD9912datasheet. These recommendations have been followed wherever practical.

Digital 3.3V

Digital 1.8V

Analog 1.8V

Analog 3.3V

5V

5V

5V

Figure 2.7: The PCB power plane design. This is a negative fabrication image; black areas indicateremoval of copper. The plane is split into five region, labelled in the figure. There are analog anddigital 1.8V and 3.3V power planes as well as a 5V plane which serves to supply the four on-boardLDO voltage regulators. The PCB areas taken up by each voltage regulator and bypass capacitorsare shown outlined in dashed green lines.

2.2.3 Heat Dissipation

Power dissipation is an important consideration for the voltage regulators and the AD9912. BothICs have grounded thermal contacts which are to be soldered directly to copper fills on the top sideof the PCB. As recommended by both ICs’ datasheets, an array of thermal vias is located under eachof these pads and serves to conduct heat away from the ICs. All empty areas on the bottom side ofthe PCB are ground-filled and this serves to increase the heat capacity. Areas on the bottom layerwhich are to be in contact with the aluminium enclosure have the insulating soldermask removed,increasing heat transfer to the enclosure (as well as grounding the enclosure). Figures 2.10 and 2.11show the full PCB layout from the top and bottom sides.

2.2.4 Characteristic Impedance and Trace Width

Characteristic impedance is the instantaneous impedance of a PCB trace. It is the impedance thata high-speed signal will encounter as it propagates along a trance, charging up the metal of the traceas it goes. This charging is essentially charging a capacitor where the signal trace is the top of thecapacitor, the PCB prepreg is the dielectric and the ground plane is the bottom of the capacitor[1].As the signal’s edge travels along the trace, it charges the trace itself before encountering any otherelectrical components.

If the trace impedance is different from the source or destination impedance, it is possible that thesignal’s energy will not be completely transferred, with some of the energy returning back throughthe trace. This can cause constructive or destructive interference, resulting in a less accurate signal.

2. DISCUSSION 16

To avoid this, our design ensured that high-frequency signal traces were 50Ω. 50Ω is a commonstandard and matches the input impedance of the amplifier that the RF output is intended to drive.All other components along these signal paths should be 50Ω as well, including the RF transformers,BNC connectors and coaxial cables.

Equation 2.6 gives a formula for calculating the characteristic impedance of a rectangular trace[5],where W, T and H are in common units. εr is the dielectric constant of the PCB prepreg. Thisequation is an approximation and it most accurate for Z0 between 50 and 100 Ω[5]. It is the sameequation that Altium Designer uses by default for calculating the characteristic impedance of traces.

Z0(Ω) =87√

εr + 1.41ln

5.98H

0.8W + T(2.6)

Figure 2.8 shows the trace geometry assumed by Equation 2.6. This trace geometry is referredto as a microstrip.

Figure 2.8: Diagram of microstrip trace geometry. Use this figure for characteristic impedancecalculations following Equation 2.6. Reproduced from [5].

The situation is slightly more complicated for differential signals. Equation 2.7 can be used fordifferential signals [6]. S is the spacing between the two traces carrying the differential signal.

Zdiff = 2Z0(Ω)[1− 0.48e−0.96SH ] (2.7)

An alternative trace geometry is referred to as the stripline, and is shown in Figure 2.9. Striplineshave the advantage of having lower impedance than the equivalent microstrip and of providingnatural shielding for high-frequency signals, thus reducing emissions and reducing interference fromincoming signals[5]. Emissions and external interference is not a significant concern for us, as theboards are to be enclosed in a solid aluminium enclosure. Also, striplines are not accessible fromthe exterior of the board, making testing more difficult. We do not use striplines on our board.

Figure 2.9: Diagram of stripline trace geometry. This figure is shown for comparison only; striplinesdo not appear on our device. Reproduced from [5].

2. DISCUSSION 17

Using Equations 2.6 and 2.7 and the following parameters,

εr = 4.350 (FR-406 dielectric material)T = 2.8 mils (0.071 mm or the thickness of 2 oz/ft2 copper)

H = 9.6 mils (0.244 mm)S = 9.0 mils (0.229 mm)

trace widths giving 50Ω were calculated as 14.75mils (0.375mm) for single-ended signals and 26.5mils(0.673mm) for differential signals. Wherever practical13, these widths were used in the design.

2.3 Design and Fabrication Methods

This section describes the methods used in designing and fabricating the PCB and enclosure.

2.3.1 Schematic Design

Altium Designer was the software tool used to design the new device, both for a connectivity-levelschematics to the generation of layer-by-layer PCB fabrication files.

Due to similarities, the design was largely based upon the AD9912 reference board schematic.This included the schematic for the DDS output, including the Reconstruction Filter, but did notinclude digital input or power designs. These additional designs were based upon Todd Meyrath’sAD9852 design[9] but were extensively modified due to the differences between the AD9912 and theAD9852.

All schematic diagrams are shown in Appendix A.

2.3.2 PCB Design

As mentioned, Altium Designer was the software tool used design the PCB layout. Once the designwas complete, Altium was used to generate layer-by-layer PCB fabrication files (Gerber files) anddrill files. Printouts of these Gerber files are shown in Appendix B. The drill files instruct the PCBmanufacturer on the size and location of all holes to be drilled.

Section 2.2 discusses several considerations which influenced the PCB design.Figures 2.10 and 2.11 show the full PCB layout from the top and bottom sides. Figures 2.13

and 2.12 show assembly diagrams for the PCB. The top and bottom pastemasks and silkscreens areshown above the enclosure and IC mechanical drawings.

13Very close to the AD9912 it is nessessary to reduce the width of the traces, due to the small pin spacing of theIC.

2. DISCUSSION 18

Figure 2.10: Top Side PCB layout. The top copper layout is shown in red. The top pastemask isshown in purple (shown on top of the copper layer).

Figure 2.11: Bottom Side PCB layout. The bottom copper layout is shown in blue. The bottompastemask is shown in pink (shown on top of the copper layer). Notice the bottom of the PCBis ground-filled and that large areas of this ground fill have been exposed (see pink areas). Theseregions are located along the edges of the PCB and below the AD9912 IC and the voltage regulators.They allow the PCB to be grounded to the enclosure and improve heat dissipation.

2. DISCUSSION 19

Figure 2.12: Assembly diagram showing the top pastemask and silkscreen above the enclosure andIC mechanical drawings.

Figure 2.13: Assembly diagram showing the bottom pastemask and silkscreen above the enclosuredrawings.

2. DISCUSSION 20

2.3.3 PCB Fabrication

The PCB layout design was used to generate fabrication files. There is a drill file, eleven Gerberfiles and a README file with basic fabrication instructions. The eleven Gerber files are shown inAppendix B.

The boards are 5.3′′ × 3′′, which is the same size as the previous generation DDS devices. Theyare four-layer boards (top signal, ground, power, bottom signal), which is again the same as theprevious generation DDS devices. They were fabricated using FR-406 dielectric material (4.350dielectric constant, 9.6 mils (0.244 mm) thick). Each side of the board is protected and insulatedwith a green solder-mask and is annotated with a white silkscreen. The PCBs were fabricated byAdvanced Circuits. An electrical test was also performed by Advanced Circuits.

Most components were sourced by our team and ordered from Newark. At time of writing, theDepartment of Physics and Astronomy (PHAS) electronics shop was in the process of assemblinga single prototype device. The device is expected to be complete within two or three days of thesubmission of this report. We provided them with all necessary parts (except ferrite beads) andassembly instructions.

Figures 2.14 and 2.15 are photos of the top and bottom of the PCBs. These photos were takenafter the assembly process had begun. Several components are installed, including the AD9912 ICitself.

Figure 2.14: Photo of the PCB, top side. Some components have been installed.

2. DISCUSSION 21

Figure 2.15: Photo of the PCB, bottom side, no components.

2.3.4 Enclosures

The enclosure is made of aluminium and has two pieces: a body and a lid. The enclosure design wasbased upon Todd Meyrath’s work[9]. Due to the increased complexity of our design, it was found thatthe original enclosures would short many of the PCB vias. Avoiding these shorts through changingthe PCB was found to be impractical due to space constraints. For this reason, the original enclosurewas modified to minimize the metal surface in contact with the PCB while maintaining structuralintegrity. The decreased contact area provided adequate area for the vias.

The enclosure was grounded in a number of ways. The primary method of grounding is throughthe screws attaching the PCB to the enclosure, which ensures both a tight fit and adequate returnpaths. However, the areas of the bottom of the PCB in direct contact with the enclosure were alsoground filled and exposed to allow for further contact. This grounding is particular important, asthe BNC connectors used obtain their ground only from the enclosure itself.

The New Jersey-based on-line machine shop company eMachineShop was chosen as the sup-plier (www.emachineshop.com). eMachineShop was the supplier for the enclosures used for theAD9852-based DDSs (upon which the new design is based). The enclosures were designed usingeMachineShop’s proprietary software, also called eMachineShop. Fifteen enclosures have been or-dered from eMachineShop and are expected to arrive within two to three weeks of the submissionof this report.

Figure 2.16 is a labelled diagram of the enclosure body, shown from the top. Green dotted linesindicate the approximate outlines on the PCB of the four LDO voltage regulators and the AD9912IC. Shown are ten 4-40 threaded holes and fourteen 8-32 threaded holes, used for mounting theenclosure lid and the PCB, respectively. Gray dotted lines indicate sixteen 4-40 threaded mountingholes, twelve of which are for mounting three BNC receptacles and four of which are for mountingthe enclosure to a rack.

The lid is unchanged from the previous design and is shown in Figure 2.17. Shown are twelve4-40 clearance holes, used to mount the enclosure lid onto the body (two of these holes will be unusedas they have no matching hole in the body). Two spaces are cut into the lid to allow for the 50-pindata and 3-pin power connectors.

Designs for rack mounting brackets also exist. Each bracket allows up to eight DDS devices tobe mounted to the electronics racks in the QDG lab. The design was modified slightly from anexisting design; the spacing of mounting holes were changed to be compatible with the intended

www.emachineshop.com

2. DISCUSSION 22

racks. Five14 brackets have been ordered. At time of writing, the rack mounting brackets havealready been fabricated and are in transit.

Figure 2.18 shows a 3D rendering of the enclosure, created using eMachineShop software.

DDS

RF OUT

BNC

Digital

3.3V

Digital

1.8V

Analog

1.8V

Analog

3.3V

5V Conn.

50-pin

UTBus

Conn.

CMOS

OUT

BNC

SYSCLK

IN

BNC

Figure 2.16: Labelled diagram of the enclosure body (top view). Green dotted lines indicate theapproximate outlines on the PCB of the four LDO voltage regulators and the AD9912 IC.

14Not all of these brackets are intended for this project. Extra backets were ordered at the request of the QDG lab.

2. DISCUSSION 23

Figure 2.17: Diagram of the enclosure lid (top view). This design is unchanged from the design usedfor the previous generation DDS devices at the QDG lab.

Figure 2.18: 3D rendering of the enclosure, created using eMachineShop software.

2. DISCUSSION 24

2.4 Board Features

This section will begin by discussing the device’s available inputs and outputs, the 10-position switchused to specify the board address and AD9912 start-up configuration, and the possible configurationswhich are possible when the device is assembled.

2.4.1 Inputs and Outputs

Table 2.4 lists the connection pads available on the PCB for BNC Connector mounting. Note thatonly J3, J5 and J6 are intended for mass production, and the enclosure design reflects this (seeSection 2.3.4).

Table 2.4: List of connection pads available on the PCB designed for BNC Connector mounting.Note that only J3, J5 and J6 are intended for mass production, and the enclosure design reflectsthis.

Designator Name Mass Production? DescriptionJ1 SCLK No digital control clock inputJ2 DAC OUT No unfiltered RF signal, or input to reconstruction

filter for debuggingJ3 RF Yes filtered RF output signalJ4 FDBK IN No input to the AD9912’s on-chip comparatorJ5 SYSCLK Yes main clock inputJ6 CMOS Yes programmable clock output (CMOS-level)J7 OUT N No differential programmable clock output (nega-

tive)J8 OUT P No differential programmable clock output (posi-

tive)

2.4.2 DIP Switch

A 10-position DIP-package single-pole single-throw switch is shared between the six board addressbits and the four AD9912 start-up configuration bits (S1,S2,S3 and S4). Each switch is labeled onthe silkscreen on the top side of the PCB. With the switches closed, the connections are grounded.With the switches open, the connections are pulled to the 3.3V digital rail through 10kΩ resistors.

The AD9912 start-up configuration bits on the AD9912 allow control of the default start-upoutput frequency and the system clock input mode (PLL enabled or bypassed). A decoding of theconfiguration bits is reproduced from the AD9912 datasheet in Table 2.5[3].

2.4.3 Configuration Options

The DDS device has various functionality and options that may be enabled, disabled or switchedbetween by placing or not placing various components. Here we summarise all options of the boardand provide details on how to use them. Table 2.7 summarizes the key options and gives details onspecific components which need to be omitted for each option.

2.4.3.1 SYSCLK

The DDS device is intended to be clocked with an external clock source on BNC connector J5.However, the option is provided to use an onboard crystal oscillator.

In the QDG lab, the off-board SCLK will originate from a 10MHz rubidium clock with anotherDDS being used to increase the frequency as needed (the CMOS clock driver of the AD9912 orAD9852 equivalent are possible). For more information, see Section 2.1.5.2.

2. DISCUSSION 25

Table 2.5: Options for Power-Up Default Frequencies on the AD9912, for 1GHz System Clock.Adapted from the AD9912 datasheet[3]. These options can be changed on the device by togglingfour PCB-mounted switches.

S4 S3 S2 S1 SYSCLK Input Mode Output Frequency (MHz)0 0 0 0 Xtal/PLL 00 0 0 1 Xtal/PLL 38.879390 0 1 0 Xtal/PLL 51.834110 0 1 1 Xtal/PLL 61.431880 1 0 0 Xtal/PLL 77.758790 1 0 1 Xtal/PLL 92.147830 1 1 0 Xtal/PLL 122.879030 1 1 1 Xtal/PLL 155.517581 0 0 0 Direct 01 0 0 1 Direct 38.879391 0 1 0 Direct 51.834111 0 1 1 Direct 61.431881 1 0 0 Direct 77.758791 1 0 1 Direct 92.147831 1 1 0 Direct 122.879031 1 1 1 Direct 155.51758

2.4.3.2 SCLK

It is possible to use either a clock oscillator or an external clock source to drive SCLK. The intentionis to use an on-board clock oscillator (nominally 25MHz, but this will be determined after testing).For more information, see Section 2.1.5.1.

2.4.3.3 SCLK Enable Pin

If the on-board clock oscillator is to be used, one of W4, W5 and W6 must be installed in order toenable the clock oscillator.

The board provides jumpers allowing the SCLK enable pin to be connected to ground (W4), 3.3V(W5) or the address comparator output15 (W6). The address comparator output is LOW when theaddress matches.

2.4.3.4 CMOS Clock Driver Voltage

The CMOS clock driver output voltage can be configured to be either 1.8V or 3.3V, depending onthe supply voltage present on the VDD SCLK pin. The board provides two 0805 footprints (F4and W14) allowing a jumper or ferrite bead to connect the pin to either voltage rail. For moreinformation, see Section 2.1.1.

2.4.3.5 PLL

When the PLL is enabled, follow Table 2.6 when choosing values for the loop filter components.See the circuit schematic shown in Figure A.6 for context. The PLL can be enabled or bypassedon the AD9912 by writing a 0 or 1 to Register 0x0010, Bit 4[3]. The default can be controlledthrough startup pin S4. The N-divider should also be set (Register 0x0020, bits 4:0); see theAD9912 datasheet for more information. This N divider will be half of the PLL multiplier; since Nis restricted to 2 < N < 33, 4 <PLL multiplier< 66. For more information, see Section 2.1.5.3.

15We aren’t really sure if this is useful, but we thought it might be, so we included it. The idea is that the clockoscillator will turn off if the board isn’t being talked to by the UTBus. This would reduce power usage and possiblynoise, but may introduce new complication during programming.

2. DISCUSSION 26

Table 2.6: Recommended Loop Filter Values for a Nominal 1.5MHz SYSCLK PLL Loop Bandwidth.Adapted from the AD9912 datasheet[3]. Designators have been taken to match actual designatorsin PCB design. See the circuit schematic shown in Figure A.6.

Multiplier R4 Series C46 Shunt C458 390Ω 1nF 82pF10 470Ω 820pF 56pF20 1kΩ 390pF 27pF40 (default) 2.2kΩ 180pF 10pF60 2.7kΩ 120pF 5pF

2.4.3.6 RF Path

It is desirable to be able to characterise the reconstruction filter. To do so, the board provides anoption to connect BNC connector J2 directly to the input of the reconstruction filter. To use thisoption, place jumper W3 and do not place jumpers W2 or W7. To monitor the pre-filter single-endedAD9912 DAC output on BNC connector J2 instead, place W2. For normal operation, place onlyW7.

The jumper W8 can be used to connect the filtered DAC output to the AD9912 FDBK IN inputs(these drive the clock drivers). If either clock driver is to be used, install W8. If the clock driversare not used, W8 should be omitted, and T2 and R5 are unnecessary.

Table 2.7: List of all device configuration options. In general, all components should be installedexcept those listed beside the desired options.

Option Components to omit

SYSCLK(1) XTal C53 C54 R7 R8 R9 R14 T3 W151

(2) External W11 W12 X1 C48 C51 W161

SCLK(1) Clock Oscillator2 W1(2) External U2 W4 W5 W6CMOS Voltage(1) 1.8V F41

(2) 3.3V3 W141

PLL(1) Disabled C45 C46 R4 W10(2) Enabled4 R3 W9RF Signal Path5

(1) Clock Drivers Disabled C55 C60 C61 C63 R5 R6 R10 R11 R12 R13 T2 W2 W3 W8 W13(2) Clock Drivers Enabled W2 W31 These components are located on the bottom side of the PCB.2 The clock oscillator used has an enable pin that could be either active high or active low; see

Section 2.1.5.1.3 W14 uses the same (0805) package as the ferrite beads, allowing a ferrite bead to be used instead

of a jumper if desired. See Section 2.1.74 If PLL is enabled, the loop filter components must be chosen according to Table 2.65 These are the conventional options are for normal operation. There are several other possible

configurations available; see Section 2.4.3.6.

2. DISCUSSION 27

2.5 Breadboard Testing

In order to verify functionality of the parallel to serial converter, the circuit was constructed andtested on a breadboard. The PHAS electronics shop provided 8-bit shift registers (CD74HCT165E)and flip-flops (74HCT74N) in DIP packages for testing. The components used are functionally similarto the SN74HC166 shift registers and SN74HC74 flip-flops, which are the intended components.However, the HCT165E shift registers have an asynchronous load while the SN74HC166 have asynchronous load. The slight difference in shift register functionality does not fully compromise thetest, however it does lead to some undesirable output as discussed below.

Switches were used to statically simulate the address comparator output, the strobe and 16-bit data input (arbitrarily set to 1010 1010 1001 01012). The outputs were monitored with anoscilloscope. Results are shown in Figure 2.19. Note that, as expected, the CSB was held low whilethe data was clocked out on SDIO.

The undesirable output is indicated graphically on the SIO and CSB subplots of Figure 2.19.Both signals responded too soon to the SH/LD signal due to the asynchronous load of the HCT165Eshift registers.

The DDS device is designed to use the SN74HC74 shift registers, which have a synchronous load.The result will be that the output will not respond to a change in the SH/LD signal until a risingedge of the clock. The red lines shown in Figure 2.19 indicate the desired output.

2. DISCUSSION 28

−0.5 0 0.5 1 1.5 2 2.5 3 3.5 4

0

2

4SCLK (Clock)

Time (µs)

Vol

tage

(V

)

−0.5 0 0.5 1 1.5 2 2.5 3 3.5 4−2

0

2

4

6

SH/LD (Shift/Load)

Time (µs)

Vol

tage

(V

)

−0.5 0 0.5 1 1.5 2 2.5 3 3.5 4−2

0

2

4

6

SIO (Serial Data)

Time (µs)

Vol

tage

(V

)

−0.5 0 0.5 1 1.5 2 2.5 3 3.5 4−2

0

2

4

6

CSB (Chip Select Bit)

Time (µs)

Vol

tage

(V

)

Figure 2.19: Parallel-to-serial converter breadboard test results. This test simulates the writingof the (arbitrarily chosen) 16-bit number 1010 1010 1001 01012 to the AD9912 serial control port.The top graph shows the clock, which was operating at 5.642MHz. A function generator was used.Below this, the SH/LD graph illustrates the functioning of the load pin. When this signal is low,the 16-bits of data on the UTBus are latched into two 8-bit shift registers on the DDS device. Whenhigh, shift register contents are clocked into the AD9912. Second from the bottom, the SIO dataplot illustrates the data output from the shift registers. The results are not as desired, but this isexpected due to using parts not from the design (CD74HCT165E shift registers were used in placeof SN74HC74). The red lines illustrate the desired behaviour. The bottom graph shows that theCSB, which is implemented identically to the SIO and demonstrates the same issue.

3

Conclusions

This report studied the operation of the AD9912 and described in detail the elements of its operationwhich are relevant to the project.

A conceptual design satisfying the project requirements has been created and presented. Asrequired, the design is compatible with the existing UTBus control interface and is designed toprovide a sinusoidal output signal at frequencies from 8 to 400MHz.

The reconstruction filter design was borrowed from the design given for the AD9912 evalua-tion board, Rev. B. This design has been verified through a SPICE simulation and the resultingtheoretical transfer function has been presented. This transfer function meets the desired perfor-mance specifications: 400MHz cut-off frequency, a roll-off within 100MHz and a minimum of 60dBof attenuation in the stop-band.

Altium Designer was used as the software tool in creating connectivity-level schematics and PCBfabrication files. The new PCB design uses the same board dimensions, I/O connectors and layerstack-up as Todd Meyrath’s AD9852 design.

The functionality of the parallel to serial converter design has been verified through a physicalbreadboard test. Unfortunately, the exact components specified by the design were not availableat the time and so substitutes of similar functionally were used instead. This did lead to someundesirable output, however it did not fully compromise the test. The difference between the desiredoutput and actual output was minor and easily predictable given the functionality of the devices asdescribed in their datasheets.

Twenty PCBs have been fabricated by Advanced Circuits and are now in the possession of theQDG lab.

Enclosures for the devices were designed using eMachineShop’s proprietary software. The designis a modification of the previous generation AD9852 enclosure design. It is not conveniently compat-ible with the previous generation devices. Fifteen enclosures have been ordered from eMachineShopand are expected to arrive within two to three weeks of the submission of this report. Five rackmounting brackets have been ordered, each supporting up to eight DDS devices. The rack mountingbrackets have already been fabricated and at time of writing are in transit.

At time of writing, the PHAS electronics shop was in the process of assembling a single prototypedevice. The device is expected to be complete within two or three days of the submission of thisreport. Our team provided them with all necessary parts1 and assembly instructions.

Since the prototype device was not complete at time of writing, no testing has been done.As such, no claims are made regarding the actual functionality and performance of the device.Our team intends to test the prototype device and either verify correct basic operation or identifyany serious issues. Part II to this report will document testing procedures, testing results and allrecommendations. It will be submitted January 9, 2012.

1With the exception of ferrite beads.

29

4

Project Deliverables

At time of writing, a single PCB is in the PHAS electronics shop being assembled. The board isexpected to be complete during the week of January 9, 2012. Our team will test the device in orderto verify correct basic operation of the device or detect any serious issues. No extensive performancecharacterization will be performed. A Part II to this report will be submitted on January 20, 2012,documenting the testing procedures, the results and all recommendations.

4.1 List of Deliverables

The following is a list of the deliverables given in the original proposal for this project, Proposal toConstruct a Direct Digital Synthesizer. The description of each deliverable is copied verbatim. Foreach deliverable the current state is described.

• The results of the SPICE simulation of the low-pass filter. In particular, a plot showing thetransfer function of the circuit will be provided.

– The simulation is complete and shows that the filter should work as desired.

– The design was borrowed from the design given for the AD9912 evaluation board, Rev.B.

– Electronic copies of the files used for testing and the results will be provided.

• Schematic diagram of the DDS device and a full parts list.

– The schematics are complete and all parts have been chosen and sourced.

– Electronic copies of the schematics, parts list and a working Bill of Materials will beprovided electronically.

• PCB layout of the DDS device.

– The PCB layout is complete and has been used to build a PCB with no issues duringmanufacturing.

– The PCBs will be left in the drawer the QDG lab has provided for DDS parts.

• Detailed description of testing procedures and results. Performance of the device will bequantified wherever possible.

– The testing has not yet been completed due to time constraints.

– An assembled board should be received on January 9, 2012 and testing will begin then.

– Details of testing procedures and results will follow this report in a Part II.

• The functioning prototype device.

30

4. PROJECT DELIVERABLES 31

– The prototype device is expected to be received the week of January 9, 2012.

– Once testing is complete, the prototype device will be left in the DDS board drawer inthe QDG lab.

• Modified enclosure design, if required.

– Enclosures for the devices were designed.

– The design is a modification of the previous generation AD9852 enclosure design and isnot conveniently compatible with the previous generation design.

– Fifteen enclosures as well as rack mounting brackets have been ordered from eMachi-neShop and are expected to arrive within two to three weeks of the submission of thisreport.

• Eight or more finished DDS devices, ready for integration into the QDG labs electronic exper-iment control system.

– Due to time constraints, this milestone was not and will not be accomplished as part ofthis ENPH 479 project.

• Engineering recommendation report.

– This document, submitted January 9, 2012, is the Engineering recommendation report.

4.2 Financial Summary

See Table 4.2 for a brief financial summary of the project. See Table 4.2 for a breakdown of theenclosure costs.

Table 4.1: Summary of costs associated with this project. Enclosure costs do not include frontpanels. Extra PCBs were ordered since the marginal cost is very low. The evaluation board wasordered because it should be a useful benchmark during performance characterization.

Description Quantity Vendor Unit Cost Total CostPCBs 20 Advanced Circuits $44.92 $898.30Enclosures 15 eMachineShop $60.59 $908.85AD9912 15 Analog Devices $50 $750Other Components 15 sets Newark, Mousser, Digikey $43.35 $650.26Evaluation Board 1 Analog Devices $500 $500

Table 4.2: DDS Enclosure Costs. All parts were ordered from eMachineShop. Note that only 2 of 5front panels are intended for the AD9912 DDS devices.

Description Quantity Unit Cost Total CostLid 15 $10.87 $163.05Enclosures 15 $49.72 $745.73Front Panels 5 $67.29 $336.47

References

[1] Advanced Layout Solutions, Ltd., Control Impedance. 2009.

[2] Analog Devices CMOS 300 MSPS Complete DDS, Analog Devices 9852. 2007.

[3] Analog Devices, Analog Devices 9912 1 GSPS Direct Digital Synthesizer with 14 Bit DAC. 2010.

[4] Analog Devices, AD9912 Evaluation Board, Rev.0. 2008.

[5] Analog Devices, Microstrip and Stripline Design. 2009.

[6] Douglas Brooks, Differential Impedance. Miller Freeman, 1998.

[7] Keith Ladouceur, Experimental Advances toward a Compact Dual-Species Laser Cooling Appa-ratus. 2008.

[8] Sanaz Footohi, Control System of Quantum Degenerate Gases Laboratory. 2006.

[9] Todd P. Meyrath, Digital RF Synthesizer: DC to 135 MHz. 2005.

[10] Texas Instruments, PCB Design Guidelines For Reduced EMI. November 1999.

32

Appendix A

Schematic Diagrams

This section contains the full schematic diagrams for the DDS circuit. Altium Designer was used tocreate these figures.

1

1

2

2

3

3

4

4

D D

C C

B B

A A

FDBK_INBFDBK_IN

OUT_CMOSOUTB

OUTDAC_OUTB

DAC_OUT

SYSCLKSYSCLKBSCLK

CSBSDIO

S[4..1]

U_DDS_ICDDS_IC.SchDoc

FDBK_INBFDBK_IN

OUT_CMOSOUTBOUTDAC_OUTBDAC_OUT

U_AnalogAnalog.SchDoc

CSBSDIOSCLK

S[4..1]BRDSel

U_DigitalDigital.SchDoc

SYSCLKSYSCLKB

SCLKSCLK_EN

U_CLKCLK.SchDoc

U_PowerPower.SchDoc

Clock

Digital DDS

Analog

Power

Figure A.1: Schematic diagram, top level. Top Level.SchDoc

33

APPENDIX A. SCHEMATIC DIAGRAMS 34

1

1

2

2

3

3

4

4

D D

C C

B B

A A

SYSCLK

SYSCLKB

R725

R925

R825 (OPT)

C53

0.1uF

C54

0.1uF

1

34

5 T3

ETC1-1-13GND

SCLK

GND

GND

EN1

GND2

OUT 3

VDD 4

U2

TXC 7C

GND

VDD_DGT

Serial Input Clock

Primary Clock

J1SCLK_IN

GND

W10

13

X125MHz (OPT)

W11

0

W12

0

C48

10pF

C51

10pFGND

GND

Refer to crystal data sheet for capacitor values (C48 & C51).

Clock Oscillator (~25MHz)

Input BNC for Testing

GND

W4

0

SCLK_ENW6

0

SYSCLK_N

SYSCLK_P

J5SYSCLK_IN

W5

0VDD_DGT

R1425 (OPT)

GND Refer to AD9912 data sheet for a list of compatible crystal oscillators.

PIC4801 PIC4802

COC48

PIC5101 PIC5102

COC51

PIC5301 PIC5302

COC53

PIC5401 PIC5402

COC54

PIJ101

PIJ102

COJ1

PIJ501

PIJ502

COJ5PIR701

PIR702COR7

PIR801

PIR802COR8

PIR901

PIR902COR9

PIR1401

PIR1402COR14

PIT301

PIT303PIT304

PIT305COT3

PIU201

PIU202

PIU203

PIU204

COU2

PIW101

PIW102COW1

PIW401PIW402COW4

PIW501PIW502COW5

PIW601PIW602COW6

PIW1101PIW1102COW11

PIW1201PIW1202COW12 PIX101

PIX103 COX1

PIC4802

PIC5102

PIJ102

PIJ502

PIR702

PIR901

PIR1402

PIT304

PIU202

PIW402

PIX102PIX104

PIC4801PIW1101

PIX103

PIC5101PIW1201

PIX101

PIC5301

PIR701

PIR802PIT301

PIC5401

PIR801

PIR902PIT303

PIJ101

PIW101

PIJ501PIR1401

PIT305

PIU201

PIW401

PIW501

PIW601

PIU203 PIW102 POSCLK

PIW602POSCLK0EN

PIC5302 PIW1102

NLSYSCLK0N POSYSCLK

PIC5402 PIW1202

NLSYSCLK0PPOSYSCLKB

PIU204

PIW502 POSCLK

POSCLK0EN

POSYSCLK

POSYSCLKB

Figure A.2: Schematic diagram, clocks. CLK.SchDoc


1

1

2

2

3

3

4

4

D D

C C

B B

A A

12345678910

11121314151617181920212223242526272829303132333435363738394041424344454647484950

P2

Header 25X2

GND

DAT[15..0]

ADR[7..0]

CSB

SDIO

DAT[15..0]

SH/LD

SCLK

SZ

U_Par2SerPar2Ser.SchDoc

CSB

SDIO

STROBE50-Pin Molex Header (UTBus)

S[4..1]S[4..1]

ADR1

ADR0ADR1ADR2ADR3ADR4ADR5ADR6ADR7

DAT0DAT1DAT2DAT3DAT4DAT5DAT6DAT7DAT8DAT9DAT10DAT11DAT12DAT13DAT14DAT15

S1

S2

S3

S4

AD9912 Startup Config.

Parallel to Serial Data Converter

R21 10K

VDD_DGT

R22 10K

R23 10K

R24 10K

GND

SCLK

SH/LD

STROBE

ADR[7..2]

SCLK

BRDSel

U_BoardSelBoardSel.SchDoc

ADR[7..2]

Board Select

Address Buss Functionality:

ADR[7..2] Board address. In order for the strobe to be recognized, this must match the board address set with the DIP switch.

ADR1: Low => 16-bit data transfer High => 8-bit data transfer, DAT[15..8] ignored

ADR0: Unused

789

10

1778910

181920

SW1B

SDA10H0KD

BRDSel

CSB

PIP201PIP202

PIP203PIP204

PIP205PIP206

PIP207PIP208

PIP209PIP2010

PIP2011PIP2012

PIP2013PIP2014

PIP2015PIP2016

PIP2017PIP2018

PIP2019PIP2020

PIP2021PIP2022

PIP2023PIP2024

PIP2025PIP2026

PIP2027PIP2028

PIP2029PIP2030

PIP2031PIP2032

PIP2033PIP2034

PIP2035PIP2036

PIP2037PIP2038

PIP2039PIP2040

PIP2041PIP2042

PIP2043PIP2044

PIP2045PIP2046

PIP2047PIP2048

PIP2049PIP2050

COP2

PIR2101 PIR2102COR21




PISW107

PISW108

PISW109

PISW1010

PISW1017

PISW1018

PISW1019

PISW1020

COSW1B

POBRDSel

NLCSB POCSB

PIP202

PIP204

PIP206

PIP208

PIP2010

PIP2012

PIP2014

PIP2016

PIP2018

PIP2020

PIP2022

PIP2024

PIP2026

PIP2028

PIP2030

PIP2032

PIP2034

PIP2036

PIP2038

PIP2040

PIP2042

PIP2044

PIP2046

PIP2048

PIP2050

PISW107

PISW108

PISW109

PISW1010

POSCLK

POSDIO

PIP2049

NLSTROBE

PIR2102

PIR2202

PIR2302

PIR2402

PIP2033

NLADR070000NLADR0

PIP2035NLADR070000

NLADR1

PIP2037 NLADR070000

NLADR070020

NLADR2PIP2039

NLADR070000

NLADR070020

NLADR3PIP2041

NLADR070000

NLADR070020

NLADR4PIP2043

NLADR070000

NLADR070020

NLADR5PIP2045

NLADR070000

NLADR070020

NLADR6PIP2047

NLADR070000

NLADR070020

NLADR7

PIP201

NLDAT0150000

NLDAT0PIP203

NLDAT0150000

NLDAT1PIP205

NLDAT0150000

NLDAT2PIP207

NLDAT0150000

NLDAT3PIP209

NLDAT0150000

NLDAT4PIP2011

NLDAT0150000

NLDAT5PIP2013

NLDAT0150000

NLDAT6PIP2015

NLDAT0150000

NLDAT7PIP2017

NLDAT0150000

NLDAT8PIP2019

NLDAT0150000

NLDAT9PIP2021

NLDAT0150000

NLDAT10PIP2023

NLDAT0150000

NLDAT11PIP2025

NLDAT0150000

NLDAT12PIP2027

NLDAT0150000

NLDAT13PIP2029

NLDAT0150000

NLDAT14PIP2031

NLDAT0150000

NLDAT15

PIR2401

PISW1020

NLS040010NLS1 POS040010PIR2301

PISW1019

NLS040010NLS2

POS040010

PIR2201

PISW1018

NLS040010

NLS3

POS040010

PIR2101

PISW1017

NLS040010

NLS4

POS040010

POBRDSEL

POCSB

POS1POS2POS3POS4POS040010

POSCLK

POSDIO

Figure A.3: Schematic diagram, digital.


1

1

2

2

3

3

4

4

D D

C C

B B

A A

SH/LD

R15 10K

VDD_DGT

OE1

P02

Q03

P14

Q15

P26

Q27

P38

Q39

GND10

P411

Q412

P513

Q514

P615

Q616

P717

Q718

P=Q 19

VCC 20U1

SN74HC688DW

GND

GND

Board Address Comparator

GNDBoard Address DIP Switch

Byte Comparator

R16 10K

R17 10K

R18 10K

R19 10K

R20 10K

ADR2ADR3ADR4ADR5ADR6ADR7

GND

STROBE

ADR[7..2]

SCLK SCLK

ADR[7..2]

This active-low output will stay low for one period of SCLK after a 0-to-1 transistion on STROBE, if the board address matches.

VDD_DGT

4CLK3

D2

1

Q 5

Q 6CLR

PR

U3ASN74HC74D

10

CLK11

D12

13

Q 9

Q 8CLR

PR

U3BSN74HC74D

1 1123456

1213141516

123456

SW1A

SDA10H0KD

4

CLK3

D2

1

Q 5

Q 6CLR

PR

U4ASN74HC74D

VDD_DGT

VDD_DGTVDD_DGT

VDD_DGT

VDD_DGT

CLR and PRE are active-low asychronous clear and preset pins.

10

CLK11

D12

13

Q 9

Q 8CLR

PR

U4BSN74HC74D

VDD_DGT

VDD_DGT

GND

GND

BRDSel

Board SelectCan be used to turn the clock oscillator on or off.

Unused flip-flop







PISW101

PISW102

PISW103

PISW104

PISW105

PISW106

PISW1011

PISW1012

PISW1013

PISW1014

PISW1015

PISW1016

COSW1A PIU101

PIU102

PIU103

PIU104

PIU105

PIU106

PIU107

PIU108

PIU109

PIU1010

PIU1011

PIU1012

PIU1013

PIU1014

PIU1015

PIU1016

PIU1017

PIU1018

PIU1019

PIU1020

COU1

PIU301

PIU302

PIU303

PIU304PIU305

PIU306

COU3A

PIU308

PIU309

PIU3010

PIU3011

PIU3012

PIU3013 COU3B

PIU401

PIU402

PIU403

PIU404PIU405

PIU406

COU4A

PIU408

PIU409

PIU4010

PIU4011

PIU4012

PIU4013 COU4B

PISW101

PISW102

PISW103

PISW104

PISW105

PISW106

PIU101

PIU1010

PIU1015

PIU1016

PIU1017

PIU1018

PIU307

PIU407

PIU4011

PIU4012

PIR1501

PISW1011 PIU102

PIR1601

PISW1012 PIU104

PIR1701

PISW1013 PIU106

PIR1801

PISW1014 PIU108

PIR1901

PISW1015 PIU1011

PIR2001

PISW1016 PIU1013

PIU1019

PIU3012

POBRDSel

PIU302PIU309 PIU305

PIU3010POSH0L\D\

PIU306PIU308

PIU3011PIU405PIU402POSTROBE

PIU406

PIU408

PIU409

PIU303

PIU403

NLSCLKPOSCLK

PIR1502

PIR1602

PIR1702

PIR1802

PIR1902

PIR2002

PIU1020

PIU301

PIU304

PIU3013 PIU3014

PIU401

PIU404

PIU4010

PIU4013

PIU4014

PIU1014NLADR070020NLADR2

POADR070020

PIU1012

NLADR070020

NLADR3

POADR070020

PIU109

NLADR070020

NLADR4

POADR070020

PIU107

NLADR070020

NLADR5

POADR070020

PIU105

NLADR070020

NLADR6

POADR070020

PIU103

NLADR070020

NLADR7

POADR070020POADR2POADR3POADR4POADR5POADR6POADR7POADR070020

POBRDSEL

POSCLK

POSH0L\D\

POSTROBE

Figure A.4: Schematic diagram, flip-flops and board select comparator.


1

1

2

2

3

3

4

4

D D

C C

B B

A A

GND

GND

VDD_DGT

VDD_DGT

CSB

SDIO

DAT[15..0]

SH/LD

GND

VDD_DGT

VDD_DGT

GND

DAT[15..0]

GND

VDD_DGT

SH/LD

SCLK SCLK

DAT0DAT1DAT2DAT3DAT4DAT5DAT6DAT7

DAT8DAT9DAT10DAT11DAT12DAT13DAT14DAT15

GNDVDD_DGT

SCLK

SZ

SZ = 0 for 16-bit transferSZ = 1 for 8-bit transfer

GNDVDD_DGT

SCLK

GNDVDD_DGT

SCLK

GNDVDD_DGT

SCLK

SZ

8-Bit Shift Reg.

8-Bit Shift Reg.

8-Bit Shift Reg.

8-Bit Shift Reg.

SH/LD

SH/LD

SH/LD

SH/LD

CLR9 S/L15

CLK INH6

CLK7

SI1

A2

B3

C4

D5

E10

F11

G12

H14

QH 13

VCC 16

GND8

U7

SN74HC166D

CLR9 S/L15

CLK INH6

CLK7

SI1

A2

B3

C4

D5

E10

F11

G12

H14

QH 13

VCC 16

GND8

U9

SN74HC166D

CLR9 S/L15

CLK INH6

CLK7

SI1

A2

B3

C4

D5

E10

F11

G12

H14

QH 13

VCC 16

GND8

U8

SN74HC166D

CLR9 S/L15

CLK INH6

CLK7

SI1

A2

B3

C4

D5

E10

F11

G12

H14

QH 13

VCC 16

GND8

U5

SN74HC166D

PIU501

PIU502

PIU503

PIU504

PIU505

PIU506

PIU507

PIU508

PIU509

PIU5010

PIU5011

PIU5012

PIU5013

PIU5014

PIU5015 PIU5016

COU5

PIU701

PIU702

PIU703

PIU704

PIU705

PIU706

PIU707

PIU708

PIU709

PIU7010

PIU7011

PIU7012

PIU7013

PIU7014

PIU7015 PIU7016

COU7

PIU801

PIU802

PIU803

PIU804

PIU805

PIU806

PIU807

PIU808

PIU809

PIU8010

PIU8011

PIU8012

PIU8013

PIU8014

PIU8015 PIU8016

COU8

PIU901

PIU902

PIU903

PIU904

PIU905

PIU906

PIU907

PIU908

PIU909

PIU9010

PIU9011

PIU9012

PIU9013

PIU9014

PIU9015 PIU9016

COU9

PIU502

PIU503

PIU504

PIU505

PIU506

PIU508

PIU5010

PIU5011

PIU5012

PIU5014

PIU701

PIU706

PIU708

PIU806

PIU808

PIU906

PIU908

PIU501

PIU8013

PIU5013 POCSB

PIU7013

PIU901

PIU9013 POSDIO

PIU507

PIU707

PIU807

PIU907

NLSCLKPOSCLK

PIU5015

PIU7015

PIU8015

PIU9015

NLSH0L\D\POSH0L\D\

PIU802

PIU803

PIU804

PIU805

PIU8010

PIU8011

PIU8012

PIU8014

NLSZPOSZ

PIU509

PIU5016

PIU709

PIU7016

PIU801

PIU809

PIU8016

PIU909

PIU9016

PIU9014

NLDAT0150000

NLDAT0

PODAT0150000

PIU9012

NLDAT0150000

NLDAT1

PODAT0150000

PIU9011

NLDAT0150000

NLDAT2

PODAT0150000

PIU9010

NLDAT0150000

NLDAT3

PODAT0150000

PIU905

NLDAT0150000

NLDAT4

PODAT0150000

PIU904

NLDAT0150000

NLDAT5

PODAT0150000

PIU903

NLDAT0150000

NLDAT6

PODAT0150000

PIU902

NLDAT0150000

NLDAT7

PODAT0150000

PIU7014

NLDAT0150000

NLDAT8

PODAT0150000

PIU7012

NLDAT0150000

NLDAT9

PODAT0150000

PIU7011

NLDAT0150000

NLDAT10

PODAT0150000

PIU7010

NLDAT0150000

NLDAT11

PODAT0150000

PIU705

NLDAT0150000

NLDAT12

PODAT0150000PIU704

NLDAT0150000NLDAT13PODAT0150000 PIU703

NLDAT0150000 NLDAT14PODAT0150000PIU702NLDAT0150000

NLDAT15

PODAT0150000

POCSB

PODAT0PODAT1PODAT2PODAT3PODAT4PODAT5PODAT6PODAT7PODAT8PODAT9PODAT10PODAT11PODAT12PODAT13PODAT14PODAT15PODAT0150000

POSCLK

POSDIO

POSH0L\D\

POSZ

Figure A.5: Schematic diagram, parallel-to-serial converter.


1

1

2

2

3

3

4

4

D D

C C

B B

A AAVDD_211

AVDD_319

AVDD_423

AVDD_536

AVDD_624

AVDD_742

AVDD_825

AVDD_944

AVDD_1026

AVDD_1145

AVDD_1229

AVDD_1353

AVDD30

AVDD3_237

AVDD3_314

AVDD3_446

AVDD3_547

AVDD349

AVSS_233

AVSS_339

AVSS_443

AVSS52

DVDD_23

DVDD_35

DVDD7

DVDD_I/O1

DVSS_22

DVSS_34

DVSS_46

DVSS_58

DVSS_656

DVSS57

S19

S210

S354

S455

SDIO63

SDO62 PWRDOWN 58

DAC_OUT 50DAC_OUTB 51DAC_RSET 48

OUT 35OUTB 34

OUT_CMOS 38

LOOP_FILTER 31

IO_UPDATE 60

CSB 61

FDBK_IN 41FDBK_INB 40

RESET 59

CLKMODESEL 32SYSCLK 27SCLK 64SYSCLKB 28

EP 65

NC_2 12NC_3 13NC_4 15NC_5 16NC_6 17NC_7 18NC_8 20NC_9 21NC 22

U6AD9912

R28

10K

FDBK_INBFDBK_IN

OUT_CMOS

OUTBOUT

DAC_OUTBDAC_OUT

GNDGNDGNDGNDGNDGND

GNDGNDGNDGND

GND

AVDD_1

VDD_SYSCLK_2

VDD_SYSCLK_2

VDD_SYSCLK_1VDD_DACDEC

VDD_CMOSVDD_SIO

VDD_DAC3VDD_DAC3VDD_DAC3

DVDDDVDDDVDD

VDD_SIO

SYSCLK

SYSCLKBSCLK

GND

R3

OPT (1K)

W9

0

W10

0

R4

2.2K

C45

10pFC46

180pF

S[4..1]

CSB

SDIO

R29

510

W160

W150

GND

CRYSTAL

GNDS1S2S3S4

S[4..1]

Startup Config. Pins

IO Pin Summary:

All are 3.3V CMOS

IO_UPDATE (active high, internal 50k pull-down resistor)RESET (active high, ground with 10k resistor if not used)PWRDOWN (active high, internal 50k pull-down resistor)CSB (active low, internal 100k pull-up resistor)SDOSDIOSCLK (internal 50k pull-down resistor)

R26

10KGND

These pins are part of the fanout and are connected to vias to allow easier probing, but are otherwise unconnected:

IO_UPDATEPWRDOWNRESETSDO

GND

SDIOSDO PWRDOWN

LOOP_FILTER

IO_UPDATE

CLKMODESEL

RESET

R27

10KGND

R25

10K

DAC_RSET

VDD_SYSCLK_1

AVDD_1AVDD_1

AVDD_1AVDD_2

AVDD_2

AVDD_2

AVDD_2

VDD_SYSCLK_2

AVDD

The loop filter component values shown above (R4, C45 and C46) depend on the PLL multiplier used and should be chosen accordingly (see Table 6 of the AD9912 datasheet). Values shown are appropriate for the default multiplier (40).

EXTERNAL CLOCK OR OSCILLATOR

PIC4501 PIC4502

COC45

PIC4601 PIC4602

COC46

PIR301 PIR302COR3

PIR401PIR402COR4






PIU601

PIU602

PIU603

PIU604

PIU605

PIU606

PIU607

PIU608

PIU609

PIU6010

PIU6011

PIU6012

PIU6013

PIU6014

PIU6015

PIU6016

PIU6017

PIU6018

PIU6019

PIU6020

PIU6021

PIU6022

PIU6023

PIU6024

PIU6025

PIU6026

PIU6027

PIU6028

PIU6029

PIU6030

PIU6031

PIU6032

PIU6033

PIU6034

PIU6035

PIU6036

PIU6037

PIU6038

PIU6039

PIU6040

PIU6041

PIU6042

PIU6043

PIU6044

PIU6045

PIU6046

PIU6047

PIU6048

PIU6049

PIU6050

PIU6051

PIU6052

PIU6053

PIU6054

PIU6055

PIU6056

PIU6057

PIU6058

PIU6059

PIU6060

PIU6061

PIU6062

PIU6063

PIU6064

PIU6065

COU6

PIW901 PIW902COW9

PIW1001PIW1002COW10

PIW1501

PIW1502COW15

PIW1601

PIW1602COW16

PIW1602

PIU6011

PIU6019

PIU6023

PIU6024

PIU6036

PIU6042

PIU6044

PIU6045

PIR2901PIU6032NLCLKMODESEL

PIR2801PIU6048NLDAC0RSET

PIU603

PIU605

PIU607

PIR302

PIR2502

PIR2602

PIR2702

PIR2802

PIU602

PIU604

PIU606

PIU608

PIU6033

PIU6039

PIU6043

PIU6052

PIU6056

PIU6057

PIU6065

PIW1502

PIR2701PIU6060NLIO0UPDATE

PIU6031

PIW901

PIW1002NLLOOP0FILTER

PIC4501

PIR402PIW1001 PIC4601PIR401

PIR301PIW902

PIR2902PIW1501PIW1601

PIU6012

PIU6013

PIU6015

PIU6016

PIU6017

PIU6018

PIU6020

PIU6021

PIU6022

PIU6027POSYSCLK

PIU6028POSYSCLKB

PIU6034POOUTBPIU6035POOUT

PIU6038POOUT0CMOS

PIU6040POFDBK0INBPIU6041POFDBK0IN

PIU6050PODAC0OUTPIU6051PODAC0OUTB

PIU6061POCSB

PIU6064POSCLK

PIR2501PIU6058NLPWRDOWN

PIR2601PIU6059NLRESET

PIU6063NLSDIOPOSDIO

PIU6062NLSDO

PIU6037

PIU6046

PIU6047

PIU6049

PIU6053

PIU601

PIU6014

PIU6025

PIU6030

PIC4502

PIC4602

PIU6026

PIU6029

PIU609

NLS040010

NLS1

POS040010

PIU6010

NLS040010

NLS2

POS040010

PIU6054

NLS040010

NLS3

POS040010

PIU6055

NLS040010

NLS4

POS040010

POCSB

PODAC0OUTPODAC0OUTB

POFDBK0INPOFDBK0INB

POOUT

POOUT0CMOS

POOUTBPOS1POS2POS3POS4POS040010

POSCLK

POSDIO

POSYSCLK

POSYSCLKB

Figure A.6: Schematic diagram, AD9912.


1

1

2

2

3

3

4

4

D D

C C

B B

A A

123

P1

GND

5VGND

EN1

IN2

GN

D3

Out 4

Bypass 5

UP1TPS78618

EN1

IN2

GN

D3

Out 4

Bypass 5

UP3TPS78618

EN1

IN2

GN

D3

Out 4

Bypass 5

UP4TPS78633

GND

GND

C590.1uF

C570.01uF

5V

GND

C60.1uF

C80.01uF

5V

GND

C560.1uF

C580.01uF

5V

EN1

IN2

GN

D3

Out 4

Bypass 5

UP2TPS78633

GND

C70.1uF

C90.01uF

5V

AVDD

AVDD3DVDD

5V Molex Connector

Analog 1.8V

Analog 3.3V

Digtal 3.3V

Digital 1.8V

470uF

C64

T491X

10uF

C50T491B

10uF

C52T491B

10uF

C3T491B

10uF

C5T491B

10uF

C2T491B

10uF

C4T491B

10uF

C65T491B

10uF

C62T491B

DVDD3

U_Power2Power2.SchDoc

Power2

Bypass Capacitors and Ferrite Beads

PIC201

PIC202COC2 PIC301

PIC302COC3PIC401

PIC402COC4 PIC501

PIC502COC5

PIC601

PIC602COC6

PIC701

PIC702COC7

PIC801

PIC802COC8

PIC901

PIC902COC9

PIC5001

PIC5002

COC50 PIC5201

PIC5202

COC52

PIC5601

PIC5602COC56

PIC5701

PIC5702COC57

PIC5801

PIC5802COC58

PIC5901

PIC5902COC59

PIC6201

PIC6202

COC62

PIC6401 PIC6402

COC64

PIC6501

PIC6502

COC65

PIP101

PIP102

PIP103

COP1

PIUP101

PIUP102

PIUP103

PIUP104

PIUP105

COUP1

PIUP201

PIUP202

PIUP203

PIUP204

PIUP205

COUP2

PIUP301

PIUP302

PIUP303

PIUP304

PIUP305

COUP3

PIUP401

PIUP402

PIUP403

PIUP404

PIUP405

COUP4

PIC201 PIC301

PIC5001

PIC6401

PIC6501

PIP102

PIUP101

PIUP102

PIUP201

PIUP202

PIUP301

PIUP302

PIUP401

PIUP402

PIC5201 PIC5602

PIUP304

PIC501 PIC702

PIUP204

PIC401 PIC602

PIUP104

PIC5902PIC6201

PIUP404

PIC202 PIC302PIC402 PIC502PIC601 PIC701PIC801 PIC901

PIC5002 PIC5202 PIC5601PIC5701 PIC5801PIC5901PIC6202

PIC6402

PIC6502

PIP101

PIP103

PIUP103PIUP106

PIUP203PIUP206

PIUP303PIUP306

PIUP403PIUP406

PIC802

PIUP105

PIC902

PIUP205

PIC5702

PIUP405

PIC5802

PIUP305

Figure A.7: Schematic diagram, power 1 (voltage regulators).


1

1

2

2

3

3

4

4

D D

C C

B B

A A

AVDD

VDD_DAC3 AVDD3

VDD_DACDEC

DVDD

DVDD3VDD_SIO

Local Nets Main Net

Analog 1.8V

Analog 3.3V

Digtal 3.3V

Digital 1.8VDVDD

VDD_DGT

AD9912

Digital Input Logic

C310.1uF

DVDD3

GND

C490.1uF

C10.1uF

C400.1uF

C470.1uF

C100.1uF

C110.1uF

C120.1uF

DVDD

GND

C280.1uF

AVDD3

GND

C330.1uF

GND

C360.1uF

C270.1uF

C260.1uF

C380.1uF

C370.1uF

C300.1uF

C290.1uF

C320.1uF

C390.1uF

C440.1uF

C200.1uF

VDD_DACDEC

GND

C250.1uF

C340.1uF

DVDD3

GND

C410.1uF

C430.1uF

C420.1uF

C660.1uF

C350.1uF

C670.1uF

F1

Ferrite bead

VDD_SYSCLK_1

F6

Ferrite bead

F5

Ferrite bead

F2

Ferrite beadAVDD_1

VDD_CMOSVDD_SYSCLK_1

GNDGND

Pins 26, 29 & loop filter

Pins 25 & 30

Pin 53

Pin 36

Pins 3, 5 & 7

Pins 1 & 14

Pins 46, 47 & 49

Pins 11, 19, 23 & 24

AVDD_1

1206 footprint for logic IC bypass caps (these are shown in the top row: C31,C49,...,C12)

0402 footprint for AD9912 bypass caps

AVDD_2F3

Ferrite bead

Pins 36, 42, 44 & 45

VDD_SYSCLK_2

F4

Ferrite bead

All ICs except AD9912

W14

0

GND

AVDD_2

VDD_SYSCLK_2

VDD_CMOS

GND

Power Isolation Diagram Bypass Capacitors0805 footprint for all ferrite beads and W14

PIC101

PIC102COC1

PIC1001

PIC1002COC10

PIC1101

PIC1102COC11

PIC1201

PIC1202COC12

PIC2001

PIC2002COC20

PIC2501

PIC2502COC25

PIC2601

PIC2602COC26

PIC2701

PIC2702COC27

PIC2801

PIC2802COC28

PIC2901

PIC2902COC29

PIC3001

PIC3002COC30

PIC3101

PIC3102COC31

PIC3201

PIC3202COC32

PIC3301

PIC3302COC33

PIC3401

PIC3402COC34

PIC3501

PIC3502COC35

PIC3601

PIC3602COC36

PIC3701

PIC3702COC37

PIC3801

PIC3802COC38

PIC3901

PIC3902COC39

PIC4001

PIC4002COC40

PIC4101

PIC4102COC41

PIC4201

PIC4202COC42

PIC4301

PIC4302COC43

PIC4401

PIC4402COC44

PIC4701

PIC4702COC47

PIC4901

PIC4902COC49

PIC6601

PIC6602COC66

PIC6701

PIC6702COC67

PIF101PIF102

COF1

PIF201PIF202

COF2

PIF301PIF302

COF3

PIF401PIF402

COF4

PIF501PIF502

COF5

PIF601PIF602

COF6

PIW1401PIW1402COW14

PIF102

PIF202

PIF302

PIF502

PIF602

PIW1401

PIC2901PIC3001PIC3301

PIF402

PIC3201PIC3701PIC3801 PIC3901

PIF201

PIC3501PIC3601 PIC6701

PIF301


PIC101 PIC1001 PIC1101 PIC1201

PIC2501

PIC3101

PIC3401

PIC4001 PIC4701PIC4901

PIC102 PIC1002 PIC1102 PIC1202

PIC2002

PIC2502


PIC2902PIC3002

PIC3102

PIC3202

PIC3302

PIC3402

PIC3502PIC3602PIC3702PIC3802 PIC3902

PIC4002

PIC4102 PIC4202PIC4302PIC4402

PIC4702PIC4902

PIC6602

PIC6702

PIC6601

PIF401

PIW1402

PIC2001

PIF101

PIC4101 PIC4401

PIF501

PIC4201PIC4301

PIF601

Figure A.8: Schematic diagram, power 2 (bypass capacitors and ferrite beads).


1

1

2

2

3

3

4

4

D D

C C

B B

A A

RF_IN RF_OUT

U_Reconstruction FilterReconstruction Filter.SchDoc

1

2

34

5

6

T1

ADT2-1T-1P+

1

2

34

5

6

T2

ADT2-1T-1P+

R5100

R1OPT

R2OPT

GND

GND

J2

DUT OUT/FILTER INW20

W70

J3

DUT FILTER OUT

W80

J4

FDBK_IN

J8

OUT

J7

OUTB

R111K

R1310K

R1210K

R1010K

R610K

C61

10nF

C60

10nF

C55

0.1uFGND

GND

GND

J6

CMOS OUTW13

0C63OPT

FDBK_INB

FDBK_IN

OUT_CMOS

OUTB

OUT

DAC_OUTB

DAC_OUT

RF Transformer

RF Transformer

GND

GND

GND

GND

GND

GND

GNDGND

DAC_OUT_N

DAC_OUT_P

FDBK_IN_P

FDBK_IN_N

OUT_P

OUT_N

OUT_CMOS

OUT

OUTB

FILT_IN

FILT_OUT

FDBK_IN

W30

PIC5501PIC5502

COC55

PIC6001 PIC6002

COC60

PIC6101 PIC6102

COC61

PIC6301

PIC6302COC63

PIJ201

PIJ202

COJ2

PIJ301

PIJ302

COJ3

PIJ401

PIJ402

COJ4

PIJ601

PIJ602

COJ6

PIJ701

PIJ702

COJ7

PIJ801

PIJ802

COJ8

PIR101

PIR102COR1

PIR201

PIR202COR2

PIR501

PIR502COR5

PIR601

PIR602

COR6

PIR1001

PIR1002

COR10

PIR1101

PIR1102COR11

PIR1201

PIR1202

COR12

PIR1301

PIR1302

COR13

PIT101

PIT102

PIT103PIT104

PIT105

PIT106

COT1

PIT201

PIT202

PIT203PIT204

PIT205

PIT206

COT2

PIW201

PIW202

COW2PIW301

PIW302

COW3

PIW701

PIW702

COW7

PIW801

PIW802COW8

PIW1301 PIW1302COW13

PIR201PIT106

NLDAC0OUT0NPODAC0OUT

PIR102PIT104

NLDAC0OUT0PPODAC0OUTB

PIJ401PIT201

PIW801

NLFDBK0IN

PIR502 PIT204NLFDBK0IN0NPOFDBK0IN

PIR501PIT206

NLFDBK0IN0PPOFDBK0INB

PIJ201PIW201 PIW301NLFILT0IN

PIJ301

PIW802

NLFILT0OUT

PIC5502

PIC6301

PIJ202

PIJ302

PIJ402

PIJ602

PIJ702

PIJ802

PIR101PIR202

PIR1202

PIR1301

PIT101

PIT105

PIT203

PIC5501 PIR601PIR1002

PIJ601PIW1302

PIT102

PIT103PIW202PIW701

PIT202PIT205

PIW302

PIW702

PIC6102 PIJ801

PIR1102

PIR1302 NLOUT

PIC6302 PIW1301NLOUT0CMOS

POOUT0CMOS

PIC6001

PIR602NLOUT0NPOOUTB

PIC6101

PIR1001

NLOUT0PPOOUT

PIC6002 PIJ701

PIR1101

PIR1201NLOUTB

PODAC0OUT

PODAC0OUTB

POFDBK0IN

POFDBK0INB

POOUT

POOUT0CMOS

POOUTB

Figure A.9: Schematic diagram, analog.


1

1

2

2

3

3

4

4

D D

C C

B B

A A

RF_IN RF_OUT

C13

5.6pF

L1

18nH

C15

2.7pF

C18

1.0pF

C142.7pF

C165.6pF

C176.8pF

C193.9pF

C212.7pF

C225.6pF

C236.8pF

C243.9pF

L2

22nH

L3

27nH

GND GND GND GND

GND GND GND GND

400MHz 7th Order Elliptic Low-Pass Filter0402 footprint for all components shown here

PIC1301 PIC1302

COC13

PIC1401

PIC1402COC14

PIC1501 PIC1502

COC15

PIC1601

PIC1602COC16

PIC1701

PIC1702COC17

PIC1801 PIC1802

COC18

PIC1901

PIC1902COC19

PIC2101

PIC2102COC21

PIC2201

PIC2202COC22

PIC2301

PIC2302COC23

PIC2401

PIC2402COC24

PIL101 PIL102

COL1

PIL201 PIL202

COL2

PIL301 PIL302

COL3

PIC1402 PIC1602 PIC1702 PIC1902

PIC2101 PIC2201 PIC2301 PIC2401

PIC1301

PIC1401

PIC2102

PIL101

PORF0IN

PIC1302

PIC1501

PIC1601

PIC2202

PIL102

PIL201

PIC1502

PIC1701

PIC1801

PIC2302

PIL202

PIL301

PIC1802

PIC1901

PIC2402

PIL302

PORF0OUTPORF0IN PORF0OUT

Figure A.10: Schematic diagram, reconstruction filter.

Appendix B

PCB Fabrication Drawings

This section contains printouts generated from the Gerber files used for PCB fabrication. These files,along with hole/via drilling information provide the PCB manufacturer with most of the informationneeded to construct the boards. Unless noted in the caption, the Gerber files shown are positive,meaning that dark areas indicate that material should be present (either copper, the insulatingsoldermasks or the silkscreens). The ground and power plane files are negative, meaning that darkareas indicate that material should be removed.

Figure B.1: Fabrication Drawings, top copper layer.

43

APPENDIX B. PCB FABRICATION DRAWINGS 44

Figure B.2: Fabrication Drawings, ground plane (negative).

Figure B.3: Fabrication Drawings, power plane (negative).


Figure B.4: Fabrication Drawings, bottom copper layer.

Figure B.5: Fabrication Drawings, top silkscreen.


Figure B.6: Fabrication Drawings, bottom silkscreen.

Figure B.7: Fabrication Drawings, top soldermask.


Figure B.8: Fabrication Drawings, bottom soldermask.

Figure B.9: Fabrication Drawings, drill drawing.

Appendix C

3D PCB Renderings

This section contains 3D renderings of the top and bottom of the PCB. Altium Designer was usedto create these figures. Figures C.1 and C.2 use a somewhat realistic colour scheme.

Figure C.1: 3D Rendering of the DDS, top view. Created using Altium Designer.

48

APPENDIX C. 3D PCB RENDERINGS 49

Figure C.2: 3D Rendering of the DDS, bottom view. Created using Altium Designer.

APPENDIX C. 3D PCB RENDERINGS 50

Figure C.3: 3D Rendering of the DDS, angled view. Created using Altium Designer.

Appendix D

PCB Parts List

Table D.1: Bill of Materials

Comment Description Footprint Designator

0.1µF Capacitor 1206 C1, C6, C7,C10, C11, C12,C31, C40, C47,C49, C56, C59

T491B Solid Tantalum ChipCapacitor, StandardT491 Series - IndustrialGrade

B C2, C3, C4, C5,C50, C52, C62,C65

0.01µF Capacitor 1206 C8, C9, C57,C58

5.6pF Capacitor 0402 C13, C16, C222.7pF Capacitor 0402 C14, C15, C216.8pF Capacitor 0402 C17, C231.0pF Capacitor 0402 C183.9pF Capacitor 0402 C19, C240.1µF Capacitor 0402 C20, C25, C26,

C27, C28, C29,C30, C32, C33,C34, C35, C36,C37, C38, C39,C41, C42, C43,C44, C66, C67

10pF Capacitor 0402 C45, C48, C51180pF Capacitor 0402 C460.1µF Capacitor 0402 C53, C54, C5510nF Capacitor 0402 C60, C61OPT Capacitor 1206 C63T491X Solid Tantalum Chip

Capacitor, StandardT491 Series - IndustrialGrade

X C64

Ferrite bead Ferrite Bead 0805 F1, F2, F3, F4,F5, F6

SCLK IN BNC Elbow Connector BCNPads

J1

51

APPENDIX D. PCB PARTS LIST 52


DUTOUT/FILTERIN

BNC Elbow Connector BCNPads

J2

DUT FIL-TER OUT

BNC Elbow Connector BCNPads

J3

FDBK IN BNC Elbow Connector BCNPads

J4

SYSCLK IN BNC Elbow Connector BCNPads

J5

CMOS OUT BNC Elbow Connector BCNPads

J6

OUTB BNC Elbow Connector BCNPads

J7

OUT BNC Elbow Connector BCNPads

J8

18nH Inductor 0402 L122nH Inductor 0402 L227nH Inductor 0402 L370543-0107 Header, 3-Pin Power

HeaderP1

Header 25X2 N2550-5002RB UTBUS P250Ω Resistor 0402 R1, R21kΩ Resistor 0402 R32.2kΩ Resistor 0402 R4100Ω Resistor 0402 R510kΩ Resistor 0402 R6, R10, R12,

R1325Ω Resistor 0402 R7, R925Ω Resistor 0402 R81kΩ Resistor 0402 R1125Ω Resistor 1206 R1410kΩ Resistor 1206 R15, R16, R17,

R18, R19, R20,R21, R22, R23,R24, R25, R26,R27, R28

510Ω Resistor 1206 R29SDA10H0KD C&K SDA Series Low

Profile DIP Switches,10 Pos

DIPSW20 SW1

ADT2-1T-1P+

6-Pin Transformer CD542 T1, T2

ETC1-1-13 E-Series RF 1:1 Trans-mission Line Trans-former, 4.5-3000MHz

SM22 T3

SN74HC688DW8-Bit Identity Com-parator

DW020 M U1

TXC 7C TXC Clock Oscillator(SCLK)

4-pinSMD

U2

APPENDIX D. PCB PARTS LIST 53


SN74HC74D Dual D-Type Positive-Edge-Triggered Flip-Flop with Clear andPreset

D014 N U3, U4

SN74HC166D 8-Bit Parallel-LoadShift Register

D016 N U5, U7, U8, U9

AD9912 Direct Digital Synthe-sizer

64-pinSMD

U6

TPS78618 Texas Instruments 5-Pin Voltage Regulator

SOT223-6M

UP1, UP3

TPS78633 Texas Instruments 5-Pin Voltage Regulator

SOT223-6M

UP2, UP4

0Ω Jumpers 1206 W1, W2, W3,W4, W5, W6,W7, W8, W13,W15, W16

0Ω Jumpers 0402 W9, W10, W11,W12

0Ω Jumpers 0805 W14FoxHC49SDLF

25MHz Crystal Oscilla-tor (SYSCLK)

4-pinSMD

X1

A 400MHz Direct Digital Synthesizer with the AD9912 · DDS is a device capable of digitally generating sinusoidal waves with programmable frequency and phase. ferrite bead is a passive

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