A 2Gbps Optical Receiver with Integrated Photodiode in 90nm CMOS by Alain Rousson A thesis submitted in conformity with the requirements for the degree of Master of Applied Science Graduate Department of Electrical and Computer Engineering University of Toronto c Copyright by Alain Rousson 2011
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A 2Gbps Optical Receiver with Integrated Photodiode in
90nm CMOS
by
Alain Rousson
A thesis submitted in conformity with the requirementsfor the degree of Master of Applied Science
Graduate Department of Electrical and Computer EngineeringUniversity of Toronto
1.1 Optical receiver for long distance communications [1]. . . . . . . . . . 11.2 Cross section of a photodiode in a modified SiGe process [2]. . . . . . 31.3 Cross section of an unmodified photodiode that uses avalanche opera-
power and 8.5dB extinction ratio input into photodiode. The simula-tion covers 10000UIs. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1 Annotated photo of the photodiode n-well/p-substrate photodiode. Itis 72µm × 78µm. The n-well is connected to metal 2, while the p-substrate is connected to metal 1. . . . . . . . . . . . . . . . . . . . . 36
4.2 Photo of bare die. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374.3 Photo of the die after the ablation of the aluminium over the photodiodes. 384.4 Close-up photos of the photodiode (a) The photodiode after original
manufacturing is covered by aluminium. (b) The photodiode after theablation of the aluminium. . . . . . . . . . . . . . . . . . . . . . . . . 38
4.5 Photo of the PCB used to test the chip. . . . . . . . . . . . . . . . . 394.6 Test setup for electrical testing. . . . . . . . . . . . . . . . . . . . . . 394.7 Eye diagrams with an electrical PRBS7 input to the board of 200mVpp
(a) 1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps. . . . . . . . . 404.8 Eye diagrams with an electrical PRBS31 input to the board of 300mVpp
(a) 1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps. . . . . . . . . . . 414.9 Test setup for photodiode responsivity testing. . . . . . . . . . . . . . 414.10 Photodiode responsivity test structure. . . . . . . . . . . . . . . . . . 424.11 Test setup for the optical testing. . . . . . . . . . . . . . . . . . . . . 424.12 Photo of the test setup. . . . . . . . . . . . . . . . . . . . . . . . . . . 434.13 Photo of the optical probe coupling to the integrated photodiode. . . 444.14 Eye diagrams with an average input power of -3.0dBm at 2.5Gbps (a)
Archcom Technology AC6538 (b) NewFocus 1554-A. . . . . . . . . . 444.15 Eye diagrams with an average input power of -1.9dBm and extinction
ratio of 4.8dB at 2.5Gbps (a) NewFocus 1554-A (b) receiver chip. . . 464.16 Eye diagrams with an optical PRBS7 input with an average input
power of -3.7dBm and an extinction ratio of 9dB and a supply of 1.2V(a) 1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps. . . . . . . . . 47
4.17 Eye diagrams with an optical PRBS31 input with an average inputpower of -3.7dBm and an extinction ratio of 9dB and a supply of 1.2V(a) 1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps. . . . . . . . . . . 48
4.18 BER vs. average optical input for a constant 9dBm extinction ratioand a 1.2V supply (a) PRBS7 input (b) PRBS31 input. . . . . . . . . 49
vii
List of Figures
4.19 Eye diagrams with an optical PRBS7 input with an average inputpower of -3.7dBm and an extinction ratio of 9dB and supply voltageof 1.3V (a) 1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps. . . . . 50
4.20 Eye diagrams with an optical PRBS31 input with an average inputpower of -3.7dBm and an extinction ratio of 9dB and supply voltageof 1.3V (a) 1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps. . . . . . 51
4.21 BER vs. average optical input for a constant 9dBm extinction ratioand a 1.3V supply (a) PRBS7 input (b) Pseudo-Random Bit Sequence(PRBS)31 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.22 Spice simulation output of the linear amplifier, with the plot on theleft having a PRBS7 input, and the plot on the right having PRBS31input. The blue lines represent a possible threshold value. . . . . . . 52
4.23 Eye diagram after the output buffer with revised photodiode model,4.25Gbps PRBS7 -4dBm average power and 8.5dB extinction ratioinput into photodiode. The supply voltage is 1.2V and the simulationtemperature is 27oC (a) TT simulation corner (b) SS simulation corner. 54
viii
List of Tables
3.1 Simulation corner parameters. . . . . . . . . . . . . . . . . . . . . . . 183.2 Comparison of TIA design parameters with [4] and [7]. . . . . . . . . 213.3 TIA simulation summary. . . . . . . . . . . . . . . . . . . . . . . . . 223.4 TIA monte-carlo simulation summary. . . . . . . . . . . . . . . . . . 223.5 Linear amplifier simulation summary. . . . . . . . . . . . . . . . . . . 283.6 Power consumption breakdown by voltage rail, which are both set to
4.1 Measurement results for optical testing. The chip is built in a stan-dard 90nm CMOS. The wavelength used is 850nm. The simulationresults are for a 1.2V supply voltage with a temperature of 27oC. Theextracted simulation are for 1000UIs. It is not possible to infer theoptical sensitivity from that length of simulation. . . . . . . . . . . . 53
5.1 Comparison of non-SML optical receivers. . . . . . . . . . . . . . . . 565.2 Comparison of most recently published optical receivers. . . . . . . . 56
Figure 2.10: The input to the photodiode model is a 5Gbps PRBS13 signal (a) Out-put of the hysteresis latch (b) Hysteresis latch eye diagram (c) Equalizeroutput (d) Equalizer output eye diagram (e) Photodiode output (f) Pho-todiode output eye diagram.
16
50Ω
50Ω
Af 50Ω Vout
1.36kΩ
200Ω
300fF
Dummy
10pF
6MΩ
Photodiode TIA High-pass filter Hysteretic Comparator Output Buf.
Figure 3.1: Receiver block diagram.
3 Circuit/System Design and Simulation
This chapter presents the block and system level design of the optical receiver. The
system architecture is described in Section 3.1. Block level schematic design and
simulations are provided in Section 3.2 to Section 3.6. Section 3.7 details the full
system simulation results.
3.1 System Description
3.1.1 Circuit Description
The receiver is designed to handle signal data rates up to approximately 5Gbps, with
a change of input current signal of approximately 20µA.
The receiver block diagram is shown in Figure 3.1. The receiver begins with the
two photodiodes. The photodiode surrounded by the box is covered by metal, there-
fore it will not convert any optical power to electrical power. The purpose of this
photodiode is to balance the capacitance at both input nodes of the differential TIA.
The remaining photodiode will convert the optical signal to an electrical signal.
17
3 Circuit/System Design and Simulation
Table 3.1: Simulation corner parameters.
Corner Transistor Corner Temperature Supply VoltageTypical TT 27oC 1.2VSlow SS 85oC 1.2VFast FF 0oC 1.2V
The electrical signal is fed to the differential TIA, which converts the signal current
to a signal voltage. The TIA drives the high-pass filter described in Section 2.3, which
is used to remove ISI. The high-pass filter also acts as AC coupling between the TIA
and the linear amplifier stage, since they operate at different common-mode voltages.
The linear amplifier increases the signal swing. Any offset in the differential voltage
at the input will by amplified by the gain of this stage to overwhelm the signal at the
output. To solve this problem, offset compensation is included in this stage.
The hysteresis latch returns the signal to NRZ signalling levels, as described in
Section 2.3. The output buffer is included for testing. It needs to drive a 50Ω load
per side.
3.1.2 Technology
The design was implemented in the Taiwan Semiconductor Manufacturing Company
(TSMC) 90nm CMOS technology. It has 1 polysilicon layer, and 9 metal layers. The
supply voltage for this design is 1.2V.
3.1.3 Simulation Corners
The design was tested with three simulation corners, listed in Table 3.1, to ensure
that the circuit would operate properly despite process variations. The current den-
sities are controllable through external pins, and were kept constant across the three
simulation corners.
3.2 Transimpedance Amplifier
The TIA is the most critical block of the receiver design. The TIA is the first block,
meaning that its noise contributions dominate the total receiver noise. The other
18
3 Circuit/System Design and Simulation
Rf
Rf
1.36kΩ
1.36kΩ
VoutAf0.64V
Figure 3.2: TIA block diagram.
RD1 RD2
150Ω150Ω
Cm 135fF Vout
Vin
Vb
7.4mA7.4mA
100 × 2µm/0.12µm100 × 2µm/0.12µm
60 × 2µm/0.12µm60 × 2µm/0.12µm
VDD
M1 M2 M3 M4
M5 M6
Figure 3.3: TIA core amplifier schematic.
important specifications are the bandwidth, transimpedance and stability.
The TIA architecture is taken from [4]. The TIA block diagram is shown in Fig-
ure 3.2, and the core amplifier schematic is shown in Figure 3.3.
The transistor sizes have the format of Nf × Wf/Lf where Nf is the number of
fingers, Wf is the width of the fingers, and Lf is the length of the fingers. This
convention is used for all schematics.
19
3 Circuit/System Design and Simulation
In [4], the supply voltage for the TIA is 3.3V. In [7], the TIA uses the same
architecture as [4], but with a 1.2V supply voltage. Thus, the transistor sizing is
taken from [7], which is why the transistors do not have minimum lengths.
For this architecture, the bandwidth is
BWTIA =1
2πRin,T IACPD. (3.1)
where Rin,T IA is the input impedance of the TIA, and CPD is the parasitic capacitance
of the photodiode. The targeted bandwidth in [4] is 2.8GHz, while it is 3GHz in [7].
The input impedance of the TIA is
Rin,T IA =Rf
Af. (3.2)
where Rf is the feedback resistor, and Af is the gain of the core amplifier, both shown
in Figure 3.2. The core amplifier in [7] draws 9.3mW, and the core amplifier in [4]
draws 31.7mW. While the core amplifier gain is not specified in either work, the power
drawn suggests that the core amplifier in [4] has a higher gain, since the core gain is
given by
Af = (gmRD)2 . (3.3)
where gm is the transconductance of the transistors forming the differential pair,
and RD is the load resistances of the differential pair. Furthermore, the photodiode
capacitance in [4] is reported as 500fF, while the photodiode capacitance reported
in [7] is 2pF. To achieve the desired bandwidths, the feedback resistance, Rf , is 5.6kΩ
in [4], while it is only 300Ω in [7].
The transimpedance of the TIA is
RT =RfAf
Af + 1. (3.4)
and is approximately equal to Rf if the core amplifier gain is significantly higher
than 1. The transimpedance in [4] is 75dBΩ while it is only 49.5dBΩ in [7]. This
implies higher input-referred noise in [7], which is determined by integrating the TIA
output noise spectral density vn,out (f) from a low non-zero frequency (to ensure a
finite result in the presence of 1/f-noise) to twice the TIA bandwidth, and dividing it
20
3 Circuit/System Design and Simulation
Table 3.2: Comparison of TIA design parameters with [4] and [7].
Parameter [4] [7] This WorkPower Supply (V) 3.3 1.2 1.2
minimize overshoot and guarantee stability. From these simulation results, the phase
margin is 85o, significantly higher than the required 60o. A re-designed TIA could fea-
ture less phase margin for better bandwidth and input-referred noise. The bandwidth
could be increased by reducing Rf , although this would decrease the transimpedance
and increase the input-referred noise. In [17][19], the core amplifier of the TIA has
four stages. Additional stages could be added to the core amplifier of the TIA in
this work to increase the core amplifier gain, which would increase the bandwidth. A
combination of additional stages in the core amplifier, and an increase in Rf would
result in a similar bandwidth, but higher transimpedance and lower input-referred
noise, with lower phase margin.
A further area of improvement would be using minimum-length transistors in the
TIA. In fact, if the length was decreased by a factor of λ = 120nm/100nm = 1.2 to a
minimum size of 100nm, either the bandwidth, or the transimpedance/input-referred
noise could be improved.
If the transistor is kept at a minimum length, and the overdrive voltage stays
constant, the total current per stage, I, will increase by λ. If RD1 and RD2 are kept
constant, the input and output common mode will decrease by 0.5 × IRD2 (λ − 1),
which should still leave enough headroom to keep all six transistors in the saturation
region. Furthermore, the poles at the inner node and at the output will increase by
λ.
The core amplifier gain, Af , will increase by λ2. If the feedback resistor, Rf , is kept
constant, the bandwidth will increase by a factor of λ2. The inpact on input-referred
noise is hard to quantify analytically. Since the closed-loop bandwidth increases,
the phase margin might decrease. However, if the feedback resistor is also increased
by λ2, then the bandwidth will stay constant, but the transimpedance will increase
by λ2. The input-referred noise is still hard to quantify analytically, but since the
transimpedance increases, the input-referred noise should decrease.
3.3 High-Pass Filter
The high-pass filter converts the output of the TIA to pulse-signalling. It also doubles
as an AC interconnect between the TIA and the linear amplifiers, so they can operate
at different DC offsets. Furthermore, it removes the common-mode offset in the
differential output of the TIA caused by the single-ended input.
23
3 Circuit/System Design and Simulation
VIN VOUTVCM
CAC
CAC
300fF
300fF
R
R
100Ω
100Ω
Figure 3.5: High-pass filter schematic.
The high-pass filter is taken from the work presented in [8]. The schematic is
shown in Figure 3.5. The input common-mode voltage of the linear amplifiers is set
to 900mV using the VCM pin. The corner frequency is
f3dB =1
2π
1
CACR= 5.3GHz. (3.6)
The eye diagram shown in Figure 3.6 is generated using a spice simulation. The
input is a 5Gbps PRBS31 signal with 5ps rise and fall time. It has a 400µV DC offset,
and a 600µVpp swing, to emulate an optical signal with -4dBm average power, and
8.5dB extinction ratio. This signal is passed through the photodiode model developed
in Section 2.1. The output of the photodiode model modulates a current source at
the input of the TIA. The eye diagram covers 10000UIs, and is of the output of
the high-pass filter. There are three distinct levels, a high-pulse, a low-pulse and no
pulse. The high-pulse indicates a low-to-high data transition. A low-pulse indicates a
high-to-low data transition. A zero means there was no transition in the data signal.
3.4 Linear Amplifier
The output of the high-pass filter is only 5mVpk, and needs to be amplified to be
able to reliably trigger the hysteresis latch. This is accomplished by a multi-stage
linear amplifier. In order to amplify the 5mV signal outputted by the filter to at least
120mV for the hysteresis latch, the gain must be at least 28dB. If the gain is increased
significantly more than 28dB, there is greater power consumption without increasing
24
3 Circuit/System Design and Simulation
Figure 3.6: Eye diagram after the high-pass filter; 5Gbps PRBS31 -4dBm averagepower and 8.5dB extinction ratio input into the photodiode. The simula-tion covers 10000UIs.
the effectiveness of the receiver. Furthermore, the linear amplifiers contribute to the
total input-referred noise of the receiver, but this contribution is reduced with a higher
gain per stage [25].
The architecture is shown in Figure 3.7. The schematic for each gain stage is
shown in Figure 3.8. The transistors are sized to have a bandwidth greater than
the bandwidth of the TIA, and cumulative gain of 28dB. The resistors are sized to
maintain the 900mV output common-mode voltage. The input of the linear amplifier
is shown in Figure 3.9, and is also taken from [4].
Since any offset voltage in the linear amplifier would be amplified and saturate
other stages, offset cancellation is required, as seen in Figure 3.7. The low-pass filter
is made using a 6MΩ resistor and two 5pF capacitors connected differentially, which
are smaller than the values reported in [4]. In [4], the resistor is 11MΩ and the single-
ended capacitor is 70pF. The capacitor can be halved with a differential structure.
The components are smaller in order to meet the 250µm pitch requirement for multiple
optical lanes [26][27][28]. Spice simulations confirm that the corner frequency is low
enough to properly compensate an offset caused by a difference of 20% in the width
of the first gain stage input pair.
The frequency response of the linear amplifier is shown in Figure 3.10. The midband
25
3 Circuit/System Design and Simulation
Figure 3.7: Block diagram of offset compensation.
RD
150Ω
VIN
VOUT
VB
20 × 2µm/0.12µm
50 × 2µm/0.12µm
2.7mA
VDD
M1 M2
M3
Figure 3.8: Linear amplifier schematic for one stage.
26
3 Circuit/System Design and Simulation
RD
150Ω
VIN
VOUT
VB2
20 × 2µm/0.12µm 20 × 2µm/0.12µm
50 × 2µm/0.12µm 50 × 2µm/0.12µm
2.7mA
VIN,OC
VB1
3.3mA
VDD
M1 M2 M3 M4
M5 M6
Figure 3.9: Linear amplifier input schematic for offset compensation.
gain is 30.0dB. The total bandwidth is 4.50GHz, which is greater than the TIA
bandwidth. A summary of the linear amplifier performance is shown in Table 3.5.
The simulated differential output of the linear amplifier is shown in Figure 3.11.
The test input is the same as the input described in Section 3.3. The signal has
an opening of approximately 150mV, which is large enough to trigger the hysteresis
latch. An area of improvement would be using minimum-length transistors. The
linear amplifier power could be reduced while maintaining the same gain.
3.5 Hysteresis Latch
The hysteresis latch re-generates the low-frequency content of pulse-signalling, out-
putting NRZ signalling. The pulse signal is compared to a threshold value, which is
28
3 Circuit/System Design and Simulation
Figure 3.11: Eye diagram after the linear amplifiers; 5Gbps PRBS31 -4dBm aver-age power and 8.5dB extinction ratio input into the photodiode. Thesimulation covers 10000UIs.
Vin
Vout
RD1 RD2
RD3
gm−in gm−1
gm−2
Itail
Figure 3.12: Block diagram of the hysteresis latch [8].
set by a feedback path. The polarity is determined by the value of the most recent
pulse bit. The block diagram of the hysteresis latch, which is taken from [8][23], is
shown in Figure 3.12.
The hysteresis condition is [23]
gm−1R2gm−2R1 > 1. (3.7)
29
3 Circuit/System Design and Simulation
RD1
170Ω
RD2
200Ω
RD3
100Ω
VIN
VOUT
VB1VB2
10 × 2µm/0.12µm
10 × 2µm/0.12µm10 × 2µm/0.12µm
40 × 2µm/0.12µm40 × 2µm/0.12µm40 × 2µm/0.12µm
2mA Adjustable Adjustable
VDD
M1 M2 M3 M4
M5 M6
M7 M8 M9
Figure 3.13: Hysteresis latch schematic.
There is flexibility to minimize the settling time, since there are two gain stages, and
RD1 and RD2 can be manipulated. Furthermore, gm−2 works as a buffer between the
critical node and the next stage.
This design also uses a split-load [29], taking the feedback from the low-impedance
fast-settling node, and taking the output from the high-swing node. The feedback-
loop settling time is given by the time-constant RD1C1, where C1 is the capacitance
at the output of the feedback loop, and the output settling time is given by (RD2 +
RD3)CL, where CL is the output capacitance. See [23] for more details.
The schematic for the hysteresis latch is shown in Figure 3.13, which is the schematic
used in [8] to implement the hysteresis latch seen in Figure 3.12. The threshold volt-
age is set by changing the bias voltage VB2. A smaller current through M8 and M9
results in a smaller threshold voltage.
With the current through M8 and M9 set to approximately 1.5mA, the value of
gm−1 is 8.85mA/V and the value of gm−2 is 9.26mA/V. The hysteresis condition is
30
3 Circuit/System Design and Simulation
Figure 3.14: Threshold adjustments by changing Itail.
which is greater than 1, and leaves a large safety margin for process, voltage and
temperature variations.
A plot of the differential output versus the differential input voltage is shown in
Figure 3.14, which shows the receiver hysteresis. The threshold voltage increases with
the current through M8 and M9.
The simulated differential output of the hysteresis latch is shown in Figure 3.15.
The test input is the same as the input described in Section 3.3. The output has
been re-generated to NRZ signalling levels. An area of improvement would be using
minimum-length transistors. There would be more flexibility in choosing the values
of gm, RD1, RD2 and RD3 to minimize the settling time, while keeping the power
consumption constant.
3.6 Output Buffer
The receiver performance will be measured by an oscilloscope and Bit Error Rate
Tester (BERT) which have a 50Ω input resistance. In order to provide proper match-
31
3 Circuit/System Design and Simulation
Figure 3.15: Eye diagram after the hysteresis latch; 5Gbps PRBS31 -4dBm averagepower and 8.5dB extinction ratio input into photodiode. The simulationcovers 10000UIs.
ing and signal swing, an output buffer whose output resistance is matched to 50Ω is
included after the hysteresis latch.
The output buffer’s bandwidth must be greater than the TIA. Despite the fact
that the small-signal approximation isn’t very accurate because of the relatively large
input signal, it can still be used as an approximation [6].
The BERT requires a minimum swing of 100mVpp per side. The load output
impedance is 25Ω per side, as the 50Ω output impedance of the buffer is in par-
allel with the 50Ω input impedance of the oscilloscope/BERT. The output buffer is
driving a bondwire inductance of 2nH and a package pin capacitance of approximately
1pF.
The swing requirement means the output buffer must drive a large current, 100mV/25Ω =
4mA. Consequently, the transistors need to be large, which loads the output of the
hysteresis latch. To reduce the load, multiple differential stages are used. The hys-
teresis latch can drive the first stage. The second stage draws more current, to be
able to drive the larger final stage, which must drive the 25Ω load per side. The
schematic is shown in Figure 3.16.
The small-signal bandwidth is 4.2GHz, as seen in the frequency response shown
in Figure 3.17. The simulated single-ended output of the output buffer is shown in
32
3 Circuit/System Design and Simulation
RD1
170ΩRD2
85Ω
RD3
50Ω
VIN
VOUT
VB1 VB2 VB3
20 × 2µm/0.12µm20 × 2µm/0.12µm 30 × 2µm/0.12µm
50 × 2µm/0.12µm 80 × 2µm/0.12µm80 × 2µm/0.12µm
2.7mA 5.2mA 5.2mA
VDD
M1 M2 M3 M4 M5 M6
M7 M8 M9
Figure 3.16: Output buffer schematic.
107
108
109
1010
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
Frequency [Hz]
Gai
n [d
B]
Figure 3.17: Output buffer frequency response.
Figure 3.18. The test input is the same as the input described in Section 3.3. The
swing is approximately 150mVpp per side, which is greater than the 100mVpp per side
needed by the BERT.
33
3 Circuit/System Design and Simulation
Figure 3.18: Eye diagram after the output buffer; 5Gbps PRBS31 -4dBm averagepower and 8.5dB extinction ratio input into photodiode. The simulationcovers 10000UIs.
Table 3.6: Power consumption breakdown by voltage rail, which are both set to 1.2V.
The simulation results of the complete receiver are presented in this chapter. The dif-
ferential signal at different stages of the receiver (Figure 3.1) are shown in Figure 3.6,
Figure 3.9, Figure 3.15, and Figure 3.18.
The power consumption breakdown is shown in Table 3.6. The measurement results
are reported in Chapter 4.
34
4 Layout and Measurements
This chapter presents the layout, test setup, and the measurement results for the
optical receiver chip. The chip was built in TSMC’s 90nm CMOS process, as de-
tailed in Section 3.1. Section 4.1 details the chip layout and Section 4.2 presents the
measurement results.
4.1 Circuit Layout
4.1.1 Photodiode Layout
The photodiode is built using an n-well/p-substrate structure, as detailed in Sec-
tion 2.1. An annotated photo of the photodiode is shown in Figure 4.1. It uses two
columns of seven fingers in order to reduce the transit time of the diffusion and drift
current components from the doped region to the metal contacts. The photodiode is
approximately 72µm by 78µm to facilitate the alignment of the 50µm fibre.
The n-well is connected to metal 2, which appears dark purple in the photo. The
metal 2 strip is 0.5µm wide, and uses two rows of contacts to the n-well. The p-
substrate is connected to metal 1, which appears blue in the photo. The metal 1 strip
is 1µm wide, and uses four rows of contacts to the n-well.
4.1.2 Chip Layout
A photo of the bare die is shown in Figure 4.2. The chip’s dimensions are 1.5mm by
1.0mm, resulting in an area of 1.5mm2. In addition to the DC optical test structure,
the chip has two optical receiver lanes, and an electrical breakout lane. Existing
high-speed photodiode arrays which operate at 850nm wavelength have a 250µm
pitch [26][27][28]. In order to meet this pitch requirement, each optical lane has a
dimension of approximately 895µm by 220µm for an area of 0.197mm2.
There are three visible photodiodes on the chip, with two more photodiodes that
are not visible. The photodiodes that are not visible are used to balance the input
35
4 Layout and Measurements
Figure 4.1: Annotated photo of the photodiode n-well/p-substrate photodiode. It is72µm × 78µm. The n-well is connected to metal 2, while the p-substrateis connected to metal 1.
capacitive load to the TIA. The top two visible photodiodes create the two optical
receiver lanes, while the bottom photodiode is used in a DC test structure.
Figure 4.2 shows that the three photodiodes detailed above were covered in alu-
minium after the initial fabrication. The aluminium was placed over all passivation
layer openings, regardless of the actual aluminium layer definition. The aluminium
definition was only located under passivation openings used by the bond pads. This
aluminium blocked all light from entering the photodiodes, and had to be removed
using a Focused Ion Beam (FIB) which can do site-specific ablation of metal. The
die photo after the FIB process is shown in Figure 4.3. This figure also shows the
bondwires that connect the die to a 44 pin Quad Flat No leads (QFN) package. The
eighteen leftmost pads don’t have any electrical connections, and consequently are
not wirebonded. Close-up photographs of the photodiode before and after the FIB
process are shown in Figure 4.4.
36
4 Layout and Measurements
Figure 4.2: Photo of bare die.
4.2 Measurements
The QFN package was mounted on a custom Printed Circuit Board (PCB), which
can be seen in Figure 4.5, for electrical and optical testing. The supply and common-
mode voltages were generated using voltage regulators. The bias currents were set by
varying potentiometers. This section details an electrical breakout test, a photodiode
responsivity test, and an optical speed test.
4.2.1 Electrical Test
The block diagram of the electrical test setup is shown in Figure 4.6. For all test setup
optical connections, and dotted lines represent multimeter leads. The electrical test
was performed at a room temperature of 24oC. The PRBS generator has an output
impedance of 50Ω, but the input impedance of the TIA is significantly smaller, which
leads to a lot of reflections at the input. For this reason, it is hard to determine
the actual eye magnitude seen at the input of the TIA. The output of the electrical
breakout has a high BER if the input is smaller than 200mVpp for a PRBS7 input.
37
4 Layout and Measurements
Figure 4.3: Photo of the die after the ablation of the aluminium over the photodiodes.
(a) (b)
Figure 4.4: Close-up photos of the photodiode (a) The photodiode after original man-ufacturing is covered by aluminium. (b) The photodiode after the ablationof the aluminium.
38
4 Layout and Measurements
Figure 4.5: Photo of the PCB used to test the chip.
Figure 4.6: Test setup for electrical testing.
The eye diagrams of the electrical breakout are shown in Figure 4.7.
However, with a PRBS31 input, the input must be increased to 300mVpp, and there
are still obvious bit errors in the eye diagrams at 2.5Gbps and 3.125Gbps data rates.
The eye diagrams are shown in Figure 4.8.
4.2.2 Photodiode Responsivity Test
The block diagram for the photodiode responsivity test is shown in Figure 4.9. The
schematic of the test structure is shown in Figure 4.10. A 50µm/125µm optical
fibre couples the power emitted from a 850-nm VCSEL (Finisar HFE6192-562) to the
photodiode. The voltage drop across the resistor shown in Figure 4.10 is measured
39
4 Layout and Measurements
(a) (b)
(c) (d)
Figure 4.7: Eye diagrams with an electrical PRBS7 input to the board of 200mVpp
The overshoot shown in Figure 4.14(b) is due to the VCSEL turning on with such
a large extinction ratio, which causes relaxation oscillation [25]. The large extinction
ratio also causes the turn-on delay to experience random variations, meaning the
optical data has more jitter [25]. The extinction ratio and, hence, overshoot and
jitter, can be reduced by increasing the DC signal power while keeping the signal
swing constant. However, this increases the offset seen in the outputs of the TIA.
Furthermore, the power supply has to provide enough headroom for the TIA to
perform as expected despite this DC offset. For example, a 2.5Gbps optical signal
with -1.9dBm output and an extinction ratio of 4.8dB output has the same optical
swing as the previous setup, and the output of the NewFocus 1554-A photodiode/TIA
shown in Figure 4.15(a) shows the eye has significantly less ringing. Furthermore, the
rms-jitter decreases from 5.3psrms to 4.4psrms. However, Figure 4.15(b) is the output
of the chip, and the eye diagram is closed, since there is too much DC offset at the
output of the TIA. This suggests that offset compensation should act right on the
input of the TIA to remove the signal-dependent DC offset as in [28][30][31]. On the
other hand, offset cancellation right at the input would add input-referred noise.
The measured output eye diagrams with an average input power of -3.7dBm and
an extinction ratio of 9dB with a 1.2V supply is shown for various data rates with
a length-(27 − 1) pseudo-random pattern PRBS7 in Figure 4.16 and with a length-
(231 − 1) pseudo-random pattern PRBS31 in Figure 4.17.
Figure 4.18 shows a plot of BER against average input power for both the PRBS7
and PRBS31 input. These plots indicate the input optical sensitivity is -3.7dBm for
a 2Gbps PRBS31 input and -4.9dBm for a 2.5Gbps PRBS7 input. Hence, the optical
sensitivity can be greatly improved through the use of data encoding schemes, such
as 8b/10b. Furthermore, the BER at 4.25Gbps for the PRBS7 input, and the BER
at 3.125Gbps for the PRBS31 input, improve very little with an increase of input
optical power. This suggests that the receiver is limited by bandwidth, not noise.
The eye diagram measurements were repeated with the supply voltage increased to
45
4 Layout and Measurements
(a) (b)
Figure 4.15: Eye diagrams with an average input power of -1.9dBm and extinctionratio of 4.8dB at 2.5Gbps (a) NewFocus 1554-A (b) receiver chip.
1.3V and all other measurement conditions that same as in Figure 4.16 and 4.17. The
results are shown in Figure 4.19 for a PRBS7 input and Figure 4.20 for a PRBS31
input.
Figure 4.21 shows a plot of BER against average input power for both the PRBS7
and PRBS31 inputs with the supply voltage increase to 1.3V. The BER gets better for
the PRBS31 inputs, but worse for the PRBS7 inputs. This suggests that the increased
supply voltage improves bandwidth (the main limitation in PRBS31 patterns) but
that the increased noise bandwidth hurts the PRBS7 patterns.
Hysteresis Threshold Dependence on Data Rate
The hysteresis threshold level was optimized to minimize BER for each data rate,
with an average input power level of -3.7dBm. This resulted in a higher hysteresis
threshold for lower bit rates. Figure 4.22 shows the spice simulation output of the
linear amplifiers with a PRBS7 input on the left, and a PRBS31 input on the right.
There is no noise in this simulation. The blue line shows one possible threshold value,
with the distance A showing the distance between the threshold value and the lowest
possible logic-1 pulse value. The distance B shows the distance between the threshold
value, and the highest possible ’no-transition’ value.
A higher hysteresis threshold, which increases the distance B, makes the receiver
less sensitive to noise. The pulses created by the PRBS31 input have a wider range
46
4 Layout and Measurements
(a) (b)
(c) (d)
Figure 4.16: Eye diagrams with an optical PRBS7 input with an average input powerof -3.7dBm and an extinction ratio of 9dB and a supply of 1.2V (a)1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps.
of amplitudes compared to the pulses created by PRBS7. This is because the pulses
created by the PRBS31 input suffers from more baseline wander before the high-pass
filter. This decreases the distance A in the case of the PRBS31 input. Furthermore,
the pulse amplitudes decrease when the data rate is increased. The threshold value
is decreased to keep a similar value A.
This hysteresis threshold configuration leads to the BER of the receiver with a
small average input power being occasionally lower for higher input data rates, as
seen in Figure 4.21. For instance, in Figure 4.21(a), the BER of the 3.125Gbps signal
is lower than the 2.5Gbps signal at input average powers below -6dBm.
The reason this happens is that while a higher hysteresis threshold is less sensitive
47
4 Layout and Measurements
(a) (b)
(c) (d)
Figure 4.17: Eye diagrams with an optical PRBS31 input with an average input powerof -3.7dBm and an extinction ratio of 9dB and a supply of 1.2V (a)1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps.
to noise, it won’t trigger properly with a very small input signal. However, a lower
hysteresis threshold is more sensitive to noise, but it will trigger properly for very
small input signals.
Analysis of Simulation Results
Increasing the supply voltage from 1.2V to 1.3V, and optimizing the TIA bias current
to minimize BER doesn’t change the TIA DC input bias from 0.63V. The photodiode
capacitance, responsivity, and intrinsic bandwidth are unchanged. The power drawn
by the core amplifier increases from 18.2mW to 23.2mW, using the calculation below
and the schematic shown in Figure 3.3.
48
4 Layout and Measurements
−7 −6.5 −6 −5.5 −5 −4.5 −4 −3.510
−12
10−10
10−8
10−6
10−4
10−2
Average Optical Input Power [dBm]
Bit
Err
or R
ate
1.25 Gbps2.5 Gbps3.125 Gbps4.25 Gbps
(a)
−7 −6.5 −6 −5.5 −5 −4.5 −4 −3.510
−12
10−10
10−8
10−6
10−4
10−2
Average Optical Input Power [dBm]
Bit
Err
or R
ate
1.25 Gbps2 Gbps2.5 Gbps3.125 Gbps
(b)
Figure 4.18: BER vs. average optical input for a constant 9dBm extinction ratio anda 1.2V supply (a) PRBS7 input (b) PRBS31 input.
IM5 = IM6 = 2 ×1.2V − 0.63V
150Ω= 7.6mA (4.9)
PTIA = 1.2V × (2 × 7.6mA) = 18.2mW (4.10)
The increase in power leads to an increase in the core amplifier gain, which will
decrease the input impedance. Since the photodiode capacitance is unchanged, the
TIA bandwidth increases. The transimpedance is unchanged. Since the output noise
spectral density is now integrated over a wider bandwidth, the total input-referred
noise increases. Spice simulations suggests the input-referred noise increases from
1.1µArms to 1.13µArms, and the bandwidth increases from 3.6GHz to 3.9GHz.
The change in supply voltage also increases the gain per stage of the linear am-
plifiers. Spice simulations also suggest that the linear amplifiers bandwidth remains
approximately constant, which is still significantly higher than the TIA bandwidth.
From these results, it is probable that the signal-to-noise ratio at the input of the
TIA degrades slightly with the change in power supply voltages.
The receiver had sufficient bandwidth with a 1.2V supply to equalize a PRBS7
input pattern. Hence, the increase in bandwidth with a 1.3V supply doesn’t improve
the performance. The higher input-referred noise degrades the BER. However, the
increase in bandwidth does improve the performance of the receiver with a PRBS31
input pattern, since this kind of pattern is more bandwidth dependent than a PRBS7
49
4 Layout and Measurements
(a) (b)
(c) (d)
Figure 4.19: Eye diagrams with an optical PRBS7 input with an average input powerof -3.7dBm and an extinction ratio of 9dB and supply voltage of 1.3V(a) 1.25Gbps (b) 2.5Gbps (c) 3.125Gbps (d) 4.25Gbps.
input pattern. The bandwidth dependence of a PRBS31 input is due to the additional
baseline wander before the high-pass filter. This causes the pulses after the filter to
have a wider range of amplitudes, as shown in Figure 4.22. Increasing the bandwidth
of the TIA decreases the total amount of baseline wander, since the output signal
settles to its final value faster. This in turn decreases the vertical spread of the
pulse signal after the high-pass filter, resulting in a greater distance A, as seen in
Figure 4.22.
The measurement results are presented in Table 4.1. The simulation and measure-
ment results agree with respect to power consumption.
DC optical measurement results show that the DC responsivity is 0.141A/W instead
50
4 Layout and Measurements
(a) (b)
(c) (d)
Figure 4.20: Eye diagrams with an optical PRBS31 input with an average input powerof -3.7dBm and an extinction ratio of 9dB and supply voltage of 1.3V(a) 1.25Gbps (b) 2Gbps (c) 2.5Gbps (d) 3.125Gbps.
of the 0.4A/W of the photodiode model. While the effect of the FIB process on the
optical responsivity is hard to measure, the difference is likely due to the inaccuracies
of the analytical model of the photodiode presented in Section 2.1. The analytical
model depends on dopant concentrations and diffusion lengths that are not published,
so they can only be estimated. A device simulator or actual photodiode measurement
results would provide a significantly more accurate model.
The intrinsic bandwidth of the photodiode can’t be measured using this prototype.
Furthermore, the bias currents are lower than the bias currents seen in TT simulations,
suggesting that the die is slower than the TT corner.
Figure 4.23 shows a new circuit simulation, where the response of the photodiode
51
4 Layout and Measurements
−7 −6.5 −6 −5.5 −5 −4.5 −4 −3.510
−12
10−10
10−8
10−6
10−4
10−2
Average Optical Input Power [dBm]
Bit
Err
or R
ate
1.25 Gbps2.5 Gbps3.125 Gbps4.25 Gbps
(a)
−7 −6.5 −6 −5.5 −5 −4.5 −4 −3.510
−12
10−10
10−8
10−6
10−4
10−2
Average Optical Input Power [dBm]
Bit
Err
or R
ate
1.25 Gbps2 Gbps2.5 Gbps3.125 Gbps
(b)
Figure 4.21: BER vs. average optical input for a constant 9dBm extinction ratio anda 1.3V supply (a) PRBS7 input (b) PRBS31 input.
(a)
Figure 4.22: Spice simulation output of the linear amplifier, with the plot on the lefthaving a PRBS7 input, and the plot on the right having PRBS31 input.The blue lines represent a possible threshold value.
52
4 Layout and Measurements
Table 4.1: Measurement results for optical testing. The chip is built in a standard90nm CMOS. The wavelength used is 850nm. The simulation results arefor a 1.2V supply voltage with a temperature of 27oC. The extractedsimulation are for 1000UIs. It is not possible to infer the optical sensitivityfrom that length of simulation.
Simulation 1.2V Supply 1.3V SupplyTotal chip area 1.5mm2
Receiver area 0.197mm2
Receiver power (minus output buffers) 50.0mW 46.3mW 55.2mWOutput buffer power 17.4mW 19.6mW 22.4mWOptical Sensitivity - -3.7dBm -4.7dBm
@ 2Gbps @ 2Gbps
is shifted down to the measured value, with the bandwidth left unchanged. This is
a complete noise transient simulation done using a full RC-extraction. The simula-
tion shows 1000UIs with a PRBS7 input. It is impossible to simulate the 1012UIs
necessary to measure a 10−12 BER. However, the eye opening is smaller with the
full RC-extraction and updated photodiode model than the eye shown in Figure 3.18.
Measurement results show that the BER should be approximately 10−4 with this
setup, according to Figure 4.18.
53
4 Layout and Measurements
(a)
(b)
Figure 4.23: Eye diagram after the output buffer with revised photodiode model,4.25Gbps PRBS7 -4dBm average power and 8.5dB extinction ratio in-put into photodiode. The supply voltage is 1.2V and the simulationtemperature is 27oC (a) TT simulation corner (b) SS simulation corner.
54
5 Conclusion
5.1 Summary
Photodiodes in standard CMOS have intrinsic bandwidths that are at most in the
tens of megahertz, and very poor optical responsivity, resulting in small input current
swing, and long tail currents. There have been multiple methods explored to enable
multi-Gbps communications, but there are two solutions in particular that are the
most cost-effective and reliable, and consequently the most common in recent work.
The first is the use of SML photodiodes, which increase the intrinsic bandwidth of
the photodiode, but greatly reduce the optical responsivity [6][14][15]. The second
is the use of some method of equalization [6][5][16][17][18]. These two solutions are
frequently used together [6][16][17][18].
The objective of this work was to integrate an optical receiver in modern standard
technologies in a form amenable to multiple lanes. To accomplish this goal, the
photodiode was integrated with the receiver in a standard 90nm CMOS process and
the nominal process voltage was not exceeded. Two optical lanes were integrated on
chip with a pitch compatible with existing industry photodiode arrays.
The design uses a non-SML photodiode in order to provide higher optical respon-
sivity. The receiver uses a high-pass filter and hysteresis latch instead of an analog
equalizer to remove the long tail currents, since the severe bandwidth restrications
caused by th enon-SML photodiode make using an analog equalizer very difficult.
A chip was fabricated in TSMC’s 90nm CMOS to validate this design. The photo-
diodes were originally covered in aluminium, which was removed using a FIB process,
allowing optical communications. The measurement results of the optical receiver are
compared to other recent non-SML photodetector receivers in Table 5.1 and to the
most recently published optical receivers in Table 5.2.
55
5 Conclusion
Table 5.1: Comparison of non-SML optical receivers.
[5] [3] This work This workTechnology 0.18µm 0.18µm 90nmArea N/A 0.53mm2 0.197mm2
The next step is to conduct multi-channel testing to determine how simultaneous
operation of the two channels will effect the optical sensitivity. To do so, a more
specialized package is required to align a fiber optic multi-channel ribbon cable. The
two photodiodes have a separation of 250µm, the same as the channels in a standard
fiber optic ribbon [26][27][28].
To increase the data rate to at least 5Gbps, the receiver blocks should be re-designed
to be faster, with the main design objective being to reduce the settling time of the
hysteresis latch and increase the TIA bandwidth. The input-referred noise at the
input of the TIA also needs to be reduced.
This receiver operated with a small supply voltage, so there was less voltage head-
room to handle the DC offset in differential output of the TIA created by the single-
ended input. Hence, the VCSEL had to be operated with a large extinction ratio,
distorting the input eye. Adding offset compensation at the input of the TIA would
solve this problem.
Finally, it has been argued that scaled CMOS technologies degrade the intrinsic
photodiode bandwidth [1][5], but since the nominal supply voltage and the p-substrate
dopant concentration is very similar in both the 65nm and 90nm CMOS technology
nodes, the effect on the intrinsic bandwidth won’t be drastic. Consequently, an
integrated optical receiver should be validated in a standard CMOS technology with
a feature size of 65nm or smaller.
57
Layout Considerations
Pin Number Pin Name Pin Description
1 NC
2 NC
3 NC
4 NC
5 NC
6 NC
7 NC
8 NC
9 NC
10 NC
Continued on Next Page. . .
58
Layout Considerations
Continued
Pin Number Pin Name Pin Description
11 NC
12 NC
13 NC
14 NC
15 Vinp Differential input of electrical test structure.
16 Vinn Differential input of electrical test structure.
17 PDtest Output of photodiode DC test structure. The
schematic is shown in Figure 4.10.
18 Vdd Power supply. Nominal current is 116mA with a
1.2V supply.
19 Vcm Common-mode voltage. 900mV.
20 Vss Ground.
21 Vss Ground.
22 oVdd Output buffer power supply. Nominal current is
49mA with a 1.2V supply.
23 NC
24 Vss Ground.
25 Voutp3 Differential output of electrical test structure.
26 Voutn3 Differential output of electrical test structure.
27 Vss Ground.
28 Voutp2 Differential output of the second optical receiver.
29 Voutn2 Differential output of the second optical receiver.
30 Vss Ground.
31 Voutp1 Differential output of the first optical receiver.
32 Voutn1 Differential output of the first optical receiver.
33 Vss Ground.
34 oVdd Output buffer power supply. Nominal current is
49mA with a 1.2V supply.
35 oVdd Output buffer power supply. Nominal current is
49mA with a 1.2V supply.
Continued on Next Page. . .
59
Layout Considerations
Continued
Pin Number Pin Name Pin Description
36 bias1 Current that sets the biasing of the TIA. Nomi-
nal current is 230µA with a 1.2V supply, however,
it should be set so that the input common mode
voltage is approximately 630mV.
37 bias3 Current that sets the strength of the positive feed-
back in the hysteresis latch. The nominal cur-
rent is 395µA for a 1.25Gbps input, 380µA for a
2.5Gbps input and 310µA for a 3.125Gbps input,
all with a supply voltage of 1.2V
38 bias2 Current that sets the biasing of the remaining cir-
cuitry. The nominal current is 340µA with a 1.2V
supply.
39 Vcm Common-mode voltage. 900mV.
40 Vdd Power supply. Nominal current is 116mA with a
1.2V supply.
41 Vdd Power supply. Nominal current is 116mA with a
1.2V supply.
42 NC
43 NC
44 NC
60
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