A 240ps 64b Carry-Lookahead A 240ps 64b Carry-Lookahead Adder in 90nm CMOS Adder in 90nm CMOS Faezeh Montazeri Faezeh Montazeri [email protected][email protected]Advanced VLSI Course Presentation Advanced VLSI Course Presentation University of Tehran University of Tehran December 2006 December 2006 Based on : Based on : A 240ps 64b Carry-Lookahead Adder in 90nm A 240ps 64b Carry-Lookahead Adder in 90nm CMOS CMOS Sean Kao, Radu Zlatanovici, Borivoje Nikolić Sean Kao, Radu Zlatanovici, Borivoje Nikolić University of California, Berkeley University of California, Berkeley
27
Embed
A 240ps 64b Carry-Lookahead Adder in 90nm CMOS Faezeh Montazeri [email protected] Advanced VLSI Course Presentation University of Tehran December.
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
A 240ps 64b Carry-Lookahead A 240ps 64b Carry-Lookahead Adder in 90nm CMOSAdder in 90nm CMOS
Advanced VLSI Course PresentationAdvanced VLSI Course PresentationUniversity of TehranUniversity of Tehran
December 2006December 2006
Based on :Based on :A 240ps 64b Carry-Lookahead Adder in 90nm CMOSA 240ps 64b Carry-Lookahead Adder in 90nm CMOS
Sean Kao, Radu Zlatanovici, Borivoje NikolićSean Kao, Radu Zlatanovici, Borivoje NikolićUniversity of California, BerkeleyUniversity of California, Berkeley
2
0
10
20
30
0 10 20 30 40 50 60
Normalized Delay [90nm 1V FO4]
No
rma
lize
d E
ne
rgy
[r.
u.]
500 nm
350 nm
250 nm
180 nm
130 nm
90 nm
What Is an Optimal Adder?What Is an Optimal Adder?
Optimal adder:• Minimum delay for given energy• Minimum energy for given delay
64-bit Adders on IEEE Xplore 1995-2005
[1]
3
This WorkThis Work
Multi-issue 64-bit microprocessor environment:
• Optimize a set of representative 64-bit adders in
the energy – delay space
• Analyze the design tradeoffs
• Implement the optimal adder in
1.0V 90nm GP CMOS
4
OutlineOutline
• Energy – delay optimization
• Design tradeoffs for 64-bit adders
• Test chip implementation
• Measured results
• Summary
5
Energy – Delay OptimizationEnergy – Delay Optimization
Delay
Ene
rgy Domino CLA Adder
• Goal: obtain the energy – delay optimal adder • CAD tool: optimize custom digital circuits in the