1 A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18µm CMOS in out V DD V DDV V GP V PW V NW slpd S tandard cell Body Bias Driver V DD Power switch V PW (M1) V NW (M1) Combinational circuit V DD (M3) GND (M3) V DDV (M3) Flip-Flop GND (M3) V DDV (M3) in V P V DD V DD 1 0 1 0 CLK int CLK ext pslpi pvgp pslpi pvgp V P V GP slpd BF1 BF1 sleep mode wakeup mode M P4 M P2 M P3 active mode V DD D-NPSBB Split-Style Clock Generator Multi-Rail Standard Cells
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A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18 µm CMOS
A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18 µm CMOS. D-NPSBB. Split-Style Clock Generator. Multi-Rail Standard Cells. 32b RISC Core and Sub-V T Operation. Chip Photo and Summary. Vibrations on V DD and V DDV. 230mV (Sub-V T ) Operation. ULV-CMOS Performance and Summary. - PowerPoint PPT Presentation
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A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18µm CMOS
in out
VDD
VDDV
VGP
VPW
VNW slpd
Standard cell Body Bias Driver
VDD
Power switch
VPW (M1)
VNW (M1)
Combinational circuit
VDD (M3)
GND (M3)
VDDV (M3)
Flip-Flop
GND (M3)
VDDV (M3)
inVP
VDD VDD
1
0
1
0
CLKint
CLKext
pslpi
pvgp
pslpi
pvgp
VPVGP
slpd
BF1 BF1
sleep mode
wakeup mode
MP4
MP2
MP3
active mode
VDD
D-NPSBB
Split-Style Clock Generator Multi-Rail Standard Cells