A lV, 2.4GHz Fully Integrated LNA Using 0.18pm CMOS Technology Lilo Zheiying, S.C.Rustngi’, A F. Li, ong Linn Signal Processi ng and VLSI Design Lab, Department of Electrical and Computer Engineering National University of Singapore, Singapore 1 19260 * Institute of Microelectronics, Singapore 117685 Correspondence Author: Professor M .F. Li [email protected]ABSTRACT A 11: ?.4GHz fully integi-ated CMOS Low Noise Amplifier (LNA) including the 500 referenced input output matching ne tworks is implemented using 0 . Spin technology within a chip area of4.1mm2. The amplifier h k he noise figure NF) f 3.8dB and a forward gain of more tlian ZOdB. The details of the LNA analysis and design procedure are presented in this paper. 1. INTRODUC.I’ION The first stage of a wireless receiver is typically an LNA, whose main function is to provide enough gain to ~vercome he noise of subsequent stages. Many LNA designs are published so’farl most of them use off-chip nework [3] or bolid wire inductor [GI to accomplish the matching. In this paper, a fully integrated CMOS LNA without off-chip matching network is proposed. Section 2 provides the detail design procedures and the measurement sesultq are shown in section 3 2. LNA DESI cg p*ucL ig 1 LNA Gnd. ingmm lhe proposed LNA diagram is shown in Fig 1. We have used extiacted RF models for all the components to achieve a “first silicon success’’ The main difficulty arises from the limited number of spiral inductors for which the extracted models are available. This puts a premium on the careful c hoice of the inductor to be used. The situation however eases out somewhat with the help of MIM capacitors as the lumped component values of the MIM capacitor R F models are observed to scale with the capacitance value. Noise Figure Optimization For the two stages LNA structue, the input MOSFET of the first stage is the main noise cont nh to r [2] and its size needs to be optimally chosen for noise considera tions. The input matching network is shown in Fig 2(a) and is simplified into Fig 2 b) under the assumption that C , is chosen small enough tc avoid the large amount input signal shunt to ground, thus the diflerence from R, to Re, or from Lx o L,, is not significant. This leads to the conclusion that the optimum size of MI in Fig 2 b) will not vmy much from that of MI in Fig 2(a). A --L a) - @ - Fig 2 Input structwc The noise factor of the simplified input structure of Fig 2(b) is shown in equation (I), its detail expression can be found in [3], wherePD is the power dissipation of the input stage; yis the channel themial noise coefficient, vrvr and are the carrier saturation velocity and electrical field respectively. We can also find W the channel width of MI, as a function of p and PD a s shown in (2). f we solve p as an expression of C V and PD as shown in (3) and substitute it into (I), the noise factor can be exprzssed in (4) a s a function of Wand PD. The curves of NF versus Wunder some fixed PD are shown in Fig 1. By using powerful mathematical softwares, the complicated delivation of the detail expression of (4) is avoided. Parametel- values used in (4) c m be found in the Appendix. 1062 0-7803-7Sd9-X/03/$17.00~2003 EEE.
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A 1V, 2.4GHz Fully Integrated LNA Using 0.18μm CMOS Technology
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7/26/2019 A 1V, 2.4GHz Fully Integrated LNA Using 0.18μm CMOS Technology