A 128Gb 3b/cell NAND Flash Design Using 20nm Planar-Cell Technology. Speaker : Naso Giovanni – Micron Flash Design Center Avezzano Italy ISSCC 2013 paper 12.5. Design team. Micron Flash Design Center Italy : - PowerPoint PPT Presentation
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Micron Flash Design Center Italy :G. Naso, L. Botticchio, M. Castelli, C. Cerafogli, M. Cichocki, P. Conenna, A. D’Alessandro, L. De santis, D. Di Cicco, W. Di Francesco, M.L. Gallese, G. Gallo, M. Incarnati, C. Lattaro, A. Macerola, G. G. Marotta, V. Moschiano, D. Orlandi, F. Paolini, S. Perugini, L. Pilolli, P. Pistilli, G. Rizzo, F. Rori, M. Rossini, G. Santin, E. Sirizotti, A. Smaniotto, U. Siciliani, M. Tiburzi, T. Vali
Micron Flash Design Center S. Jose (California) : :M. Helm, R. Ghodsi
Micron Flash Product/Process Engineering Boise (Idaho) : :R. Meyer, A. Goda, B. Filipiak
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Planar NAND CellControl gate wrap-around design has a gap filling issue between floating gates as cell dimension further shrinks beyond 2X nm.
HfO2 High-K inter-gate dielectric (IGD) is used to achieve the improved cell coupling factor which is decreased in planar floating gate cell.(HfO2 dielectric constant is about 6x greater than SiO2 dielectric constant).
Planar technology has a reduced poly floating gate (FG) thickness to minimize cell-to-cell interference.
Metal control gate (W tungsten with Ta/HfO2 interface) is used to engineer the work function preventing the erase saturation and balancing program and erase capability. It also allows to reduce the control gate resistivity which is an important factor when geometries are very small.
Air gap isolation between word lines and bit lines is used to reduce cell cross-talk.
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Ramped sensing concept
Digital progressive values are generated by a counter and :1)Fed into all page buffers (PB)2)Converted into analog ramp by a digital to analog converter (DAC) and applied to Word Line (WL)Sensing /verify is performed at each ramp step
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Ramped sensing to read threshold VT
PB(i)PBDAC
out
SABL
WLen
en
saout
BL charged -> saout =0BL discharged -> saout =1
At each WL step the Bit Line (BL) is pre-charged andthe current flowing into string is sensed by Sensamp (SA). If it is greater than a limit the digital value (PBDAC) is stored into each Page Buffer PB(i) and available at the output (out) and subsequent sensings are disabled.
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Pre compensation to mitigatefloating gate to floating gate interference
Pre-compensation is a technique that can be applied during a program operation of a page and is performed internally to the chip.
Its purpose is to mitigate the floating-gate to floating-gate interference on the actual page to be programmed coming from next surrounding pages in a stream.
The external controller must provide the content of nextpages to be programmed in order to account for possibleaggressions on the actual page.
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Pre compensation to mitigatefloating gate to floating gate interference
Pre compensation can take into account interference coming either from adjacent bit lines (odd page programmed after even page) or from adjacent word lines to be programmed next.
Cells that will not be aggressed are programmed at their target value.
Cells that will be aggressed are programmed at lower level in a way that they will be read at the target value after the aggression.
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Corrective read to mitigatefloating gate to floating gate interference
Corrective read is a feature having the purpose to perform data correction needed to compensate floating-gate tofloating-gate interference after data (both victims and aggressors) have been programmed.
Different flavors of corrective read are possible : aggression from upper WL, from single or both adjacent BLs.
The corrective read features is activated by the external controller when error level is greater than the ECC capability and it is performed internally to the NAND.
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Channel calibration to minimize BER
Purpose of Channel Calibration is to detect a read level corresponding to the maximum separation (minimum overlap)between two consecutive distributions.
It can mitigate overlaps due to different reasons :1)Retention (down shift on upper distributions)2)Cycling (distributions sigma widening : upper tail shift)3)Temperature
Channel Calibration is performed upon user request when the BER (Bit error Rate) level is considered too high for theselected ECC technique.
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Channel calibration to minimize BERChannel Calibration is organized in two phases :1)Optimum read level detection2)Calibrated read using the optimized levels
The optimum read level detection can be performed in two ways (they have different accuracy and different performing penalties) :1) Single optimum read level detection (usually between two consecutive higher distributions). In this case, all the remaining read levels are rebalanced using a model to account for optimum read levels of the lower distributions.2) Multiple optimum read level detection : the optimum value
is detected for all the read levels
Channel Calibration can be performed once per block and usedfor all the pages of the block.
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Summary
A 3bit/cell 128Gb NAND Flash at 20nm planar NANDtechnology was presented.
The planar NAND technology allows to perform a shrink in word line and bit line directions while reducing floating gate to floating gate interference compared to the WRAPtechnology.
Design techniques :- Pre conditioning- Read compensation- Channel calibration allow to minimize the Bit Error Rate due to interference,cycling, endurance.