A 1: 128 multiplexing rate Time Domain SQUID Multiplexer D. Prêle, F. Voisin, M. Piat, T. Decourcelle, C. Perbost, D. Rambaud, S. Maestre, W. Marty, L. Montier Low Temperature Detectors - LTD16 20 - 24 July 2015 - Grenoble
Nov 30, 2020
A 1: 128 multiplexing rateTime Domain SQUID Multiplexer
D. Prêle, F. Voisin, M. Piat, T. Decourcelle, C. Perbost,D. Rambaud, S. Maestre, W. Marty, L. Montier
Low Temperature Detectors - LTD1620 - 24 July 2015 - Grenoble
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
Q & U Bolometric Interferometer for Cosmology - QUBICCosmology experiment for B-mode polarization of the Cosmic Microwave Background
Bolometric Fizeau interferometer
45cm window / 14°field-of-view
400 back/back horn (looking sky)
400 switches (self calibration)
Off-axis Gregorian (combiner)
2×1024 filled array (150/220GHz)
A. Tartari QUBIC : A Fizeau interferometer for B-ModesThursday 23 - Session 5
NbSi TES focal plane imager
Interference fringes (synthesized image)
1024 NbSi TES on 4 wafers (×2 freq.)C. Perbost A 248 TES Array for CMB B-mode detection Poster
Present work, sub-system :
256 TESs, 256 SQUIDs (TDM), 2 ASICs (LNA + bias)
[email protected] 2 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
Outline
1 1 : 128 TDM multiplexer topology
2 Readout chainSQUID stageCryogenic integrated circuit
3 Multiplexed signal, FLL and demultiplexing
[email protected] 3 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
Outline
1 1 : 128 TDM multiplexer topology
2 Readout chainSQUID stageCryogenic integrated circuit
3 Multiplexed signal, FLL and demultiplexing
[email protected] 4 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
×32
CBiasTES
TES
RFB
TES
Vout
mux (4 : 1)LNA+ Integrator
mu
x(3
2:1
)dif
f.SQ
UID
bias
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
×32
CBiasTES
TES
RFB
TES
Vout
mux (4 : 1)LNA+ Integrator
mu
x(3
2:1
)dif
f.SQ
UID
bias
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
×32
CBiasTES
TES
RFB
TES
Vout
mux (4 : 1)LNA+ Integrator
mu
x(3
2:1
)dif
f.SQ
UID
bias
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
+
+
1
×32
CBiasTES
TES
RFB
TES
Vout
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
-
-
2
×32
CBiasTES
TES
RFB
TES
Vout
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
+
+
3
×32
CBiasTES
TES
RFB
TES
Vout
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
-
-
4
×32
CBiasTES
TES
RFB
TES
Vout
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
+
+
5
×32
CBiasTES
TES
RFB
TES
Vout
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
-
-
6
×32
CBiasTES
TES
RFB
TES
Vout
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
+
+
7
×32
CBiasTES
TES
RFB
TES
Vout
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
-
-
8
×32
CBiasTES
TES
RFB
TES
Vout
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
32 lines
CBiasTES
TES
RFB
TES
Vout
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
+
+
125
×32
CBiasTES
TES
RFB
TES
Vout
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
-
-
126
×32
CBiasTES
TES
RFB
TES
Vout
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
+
+
127
×32
CBiasTES
TES
RFB
TES
Vout
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
-
-
128
×32
CBiasTES
TES
RFB
TES
Vout
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
+
+
1
×32
CBiasTES
TES
RFB
TES
Vout
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
TES readout topology based on 2D multiplexing scheme
×32
CBiasTES
TES
RFB
TES
Vout
mux (4 : 1)LNA+ Integrator
mu
x(3
2:1
)dif
f.SQ
UID
bias
biasTES
TES
TES
TES
TES
TES
TES
TES
TES
TES
[email protected] 5 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
SQUID stageCryogenic integrated circuit
Outline
1 1 : 128 TDM multiplexer topology
2 Readout chainSQUID stageCryogenic integrated circuit
3 Multiplexed signal, FLL and demultiplexing
[email protected] 6 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
SQUID stageCryogenic integrated circuit
Time domain SQUID multiplexer for QUBICQUBIC Readout sub-system : 256 TES, 256 SQUID, 2 ASIC
Sub-system : NbSi TES Wafer (300 mK) + 256 SQUIDs (1K) + 2 ASICs (40K)
Integration of this sub-system in a dilution fridge for readout test
[email protected] 7 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
SQUID stageCryogenic integrated circuit
SQUID glued and wire bonded on a PCBStarCryoelectronics SQ680 specific design.
Solder plated track (no parasitic resistances)Shunt resistor and filter devices
[email protected] 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
SQUID stageCryogenic integrated circuit
32 SQUIDs glued and wire bonded on a PCB
[email protected] 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
SQUID stageCryogenic integrated circuit
32 SQUIDs glued and wire bonded on a PCB
[email protected] 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
SQUID stageCryogenic integrated circuit
64 SQUIDs glued and wire bonded on a PCB
[email protected] 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
SQUID stageCryogenic integrated circuit
96 SQUIDs glued and wire bonded on a PCB
[email protected] 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
SQUID stageCryogenic integrated circuit
128 SQUIDs glued and wire bonded on a PCB
[email protected] 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
SQUID stageCryogenic integrated circuit
128 SQUIDs glued and wire bonded on a box
[email protected] 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
SQUID stageCryogenic integrated circuit
SQUIDs glued and wire bonded on a box
[email protected] 8 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
SQUID stageCryogenic integrated circuit
ASIC Stage (Application Specific Integrated Circuit)
[email protected] 9 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
SQUID stageCryogenic integrated circuit
SiGe ASIC for cryogenic 1 :128 TD SQUID M32
SQU
IDb
ias
33
Row
MU
X
Ck
Vd
dG
nd
32 AD
R
4
I SQ
VC
MI A
mp
CM
FB
OS F
B
3
Serial link
Mu
x
4
input (from SQUID)
Dif
f
mux output 1 : 128
1 2
3
BiCMOS SiGe ASIC350nm AMS technology
1 SQUID rows addressing :Biasing throughcapacitors with ACmultiplexed currentsources (1 : 32)
2 Low noise amplifier withmultiplexed inputs :FLL preamplifiercolumn mux. (1 : 4)
3 Digital addressing circuitcontrolled by external Ck
[email protected] 10 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
Outline
1 1 : 128 TDM multiplexer topology
2 Readout chainSQUID stageCryogenic integrated circuit
3 Multiplexed signal, FLL and demultiplexing
[email protected] 11 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
Multiplexed time line
1 :128 multiplexing rate
[email protected] 12 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
Multiplexed time line
1 :128 multiplexing rate
The ASIC allows to reduce the part of the array readout
[email protected] 12 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
Flux Locked Loop (FLL) in multiplexed mode
FLL to linearize the "sine-like" SQUID transfer function
Analog FLL
bias ∫Vout
Rfb
φfb
φext
[email protected] 13 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
Flux Locked Loop (FLL) in multiplexed mode
FLL to linearize the "sine-like" SQUID transfer function
Multiplexed analog FLL
bias ∫Vout
Rfb
φfb
φext
Multiplexed mode : FLL operating point jump a φ0 between samples
[email protected] 13 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
"digital" FLL
biasG ADC
DAC∫ t −1 fb value (memory)
error signal ≈ 0
Rfb
φfb
φext
digital FLLoperating point storing
Warm readout/acquisition (FPGA + ADC/DAC)
Realtime feedback compensationimplemented into the FPGA
Series link with ASIC
Power supply ASICIRAP collaboration
[email protected] 14 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
Demultiplexing software
IRAP collaboration
[email protected] 15 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
Demultiplexing software
IRAP collaboration
[email protected] 15 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16
1 : 128 TDM multiplexer topologyReadout chain
Multiplexed signal, FLL and demultiplexing
Conclusion and outlook
Implementation and operation of a 1 : 128 TDM
2D multiplexing : SQUID stage + ASIC stage
Demultiplexing and digital FLL in a FPGA
To be done soon :1 Increase of multiplexing frequency2 Noise measurements without aliasing
[email protected] 16 / 16 A 1:128 multiplexing rate Time Domain SQUID Multiplexer - LTD16