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Feb 25, 2018

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    EKT 121/4ELEKTRONIK DIGIT 1

    Kolej Universiti

    Kejuruteraan Utara Malaysia

    Introduction to

    Programmable Logic Devices

    (PLD)

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    Introduction

    Fixed function devices a specific logic

    function is contained in the IC, it can never be

    changed.

    Programmable Logic Devices (PLDs) the

    logic function is programmed by the user

    PLDs in some cases can be programmed

    many times.

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    Digital Systems Family Tree

    Digitalsystems

    Standard

    logic ASICsMicroprocessors

    and DSP

    TTL CMOS ECL PLDsGate

    arraysStandard

    cell

    Full

    custom

    CPLDsSPLDs FPGAs

    Fuse EPROM EEPROM EPROM EEPROM Flash SRAM Flash Antifuse

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    Digital System Categories

    Three major categories :

    1. Standard Logic ((LogikLogikPiawaiPiawai))- TTL , CMOS, ECL

    2. Application-Specific Integrated Circuits (ASICs)((LitarLitarBersepaduBersepaduPenggunaanPenggunaan--TentuTentu))

    - PLDs, Gate Arrays, Standard Cells, Full

    Custom

    3. Microprocessors and Digital Signal Processing (DSP)

    (MikropemprosesMikropemproses dandanPemprosesanPemprosesanIsyaratIsyaratDigit)Digit)

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    1.Standard Logic

    Basic functional digital components (gates, FF,decoders, MUX, register, counter,etc.)

    Available as SSI and MSI chips(refer to page 20 of your text book for details)

    3 majors families of standard logic :

    1) TTL

    2) CMOS

    3) ECL (for higher-speed designs)

    Most popular is CMOS.

    Why ????? because low power consumption.

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    2.Application-Specific Integrated

    Circuits (ASICs)

    Represents modern hardware design solution for

    digital systems

    An IC is designed to implement a specific desired

    application

    Four subcategories of ASICs devices :

    1) PLDs

    2) gate arrays

    3) standard cell

    4) full-custom

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    3.Microprocessor and DSP

    Contain of various type of functional blocks

    Devices can be controlled electronically, data can be

    manipulated by executing a program of instructions.

    Flexibility all you have to do is change a program

    Major downfall is SPEED.

    Hardware solution of digital system design is

    always faster that a software solution

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    Programmable Logic Devices

    (PLDs) What is PLDs?

    - IC that contains a large number of interconnectedlogic functions.

    - Users can program the IC for a specific functionby selectively breaking the appropriate

    interconnections.- PLD has replaced the hard-wired fixed-function

    logic device in many applications.

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    Programmable Arrays

    All PLDs consists of programmable arrays

    Essentially a grid of conductors that forms rows and

    columns with a fusible link at each cross point OR arrayOR array original diode array evolved into the

    integrated OR array, which consists of an array ofOR gates connected to a programmable matrix withfusible links at each cross point of a row and

    column. AND arrayAND array an array consists of AND gates

    connected to a programmable matrix with fusiblelinks at each cross point.

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    Example : a basic programmable AND array.

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    Type of PLDs

    3 major types of programmable logic:

    1) Simple Programmable Logic Devices(SPLD)(SPLD)

    2) Complex Programmable Logic Devices

    (CPLD)(CPLD)

    3) Field Programmable Logic Array (FPGA)(FPGA)

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    1.Simple Programmable Logic Devices

    (SPLD) The least complex form of PLDs

    An arrays of AND gates and OR gates that canbe programmed to achieve logic function

    Typical package has 24 to 28 pins

    Four types :

    1) PROM (Programmable Read-Only Memory)

    2) PLA (Programmable Logic Array)

    3) PAL (Programmable Array Logic)

    4) GAL (Generic Array Logic)

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    PROM (Programmable Read-Only

    Memory).

    A fixed AND array and programmable OR array.

    Used as a memory device and normally not as a logic

    circuit

    Block diagram

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    PLA (Programmable Logic Array)

    Block diagram

    Programmable AND and OR array

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    PAL (Programmable Array Logic)

    Block diagram

    Programmable AND array and a fixed OR arraywith programmable output logic

    One-time programmable (OTP)

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    The structure allows any SOP logic expression with

    a defined number of variables to be implemented.

    PAL Operation

    Basic structure of PAL

    cell

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    PAL Operation contd

    PAL implementation of SOP expression

    A simple array is programmed so that product term

    AB is produced AND1 gate, AB by AND2 gate and

    AB by AND3 gate.

    AND1

    AND2

    AND3

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    PAL Operation contd

    Simplified diagram of a programmed PAL

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    PAL Operation contd

    Block diagram of

    PAL16L8

    Programmable

    Array Logic

    16 inputs

    Active-LOW

    output

    8 outputs

    Block diagram of

    PAL16L8

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    GAL (generic array logic)

    Block diagram

    Reprogrammable AND array, a fixed OR array, and

    programmable output logic macrocells.

    (E(E22CMOSCMOSprogrammableprogrammable

    AND array)AND array)(OLMC)(OLMC)

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    GAL Operation contd

    This structure allowsany SOP logic

    expression with a

    defined number of

    variables to be

    implemented. Essentially a grid of

    conductors formingrows and column with

    electrically erasable

    CMOS (E2CMOS) cellat each cross point.

    Basic E2CMOS array structure

    of a GAL

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    GAL Operation contd

    A simple GAL

    array isprogrammed sothat product term

    AB is producedAND1 gate, AB

    by AND2 gate

    and AB by AND3gate.

    GAL implementation of SOP expression

    AND3

    AND2

    AND1

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    GAL Operation contd

    GAL is programmed for the 3-variable logic function:

    X = ABC + ABC + BC +AB

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    General Concept of SPLD Programming

    From the hardware standpoint, programming fallsinto 2 major categories:

    1) Conventional method2) In-system programming (ISP)(ISP)

    From the software standpoint, a logic design isprogrammed into a PLD using either schematicentry software , HDL software or combination of

    both.

    E l Fl h t f SPLD ti l

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    Example: Flow chart of an SPLD conventional

    programming sequence.

    G l C t f SPLD P i

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    Typical configuration for

    conventional PLD

    programming

    General Concept of SPLD Programming

    contd

    Typical configuration for in-

    system programming of a

    PLD.

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    2.Complex Programmable Logic Devices

    (CPLD)

    Have a much higher capacity than SPLDs

    Permitting more complex logic circuits to be

    programmed into them.

    Several forms of CPLD, which vary in complexity

    and programming capability

    Typically come in 44-pins to 160-pin packagesdepending on the complexity

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    Basic diagram of a CPLD

    B i L i bl k i

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    Basic Logic array block in a

    CPLD

    3 Field Programmable Grid Array

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    3.Field Programmable Grid Array

    (FPGA)

    Different from SPLDs and CPLDs in their

    internal organization and have the greatest logic

    capacity

    Consists of an array anywhere from 64 to

    thousands of logic-gates group (logic blocks)

    Two basic classes :

    1) course grained (has large logic blocks)

    2) fined-grained (has much smaller logic blocks)

    Come in packages ranging up to 1000 pins

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    PLD Programming

    2 basic methods used to enter a logic design for a PLDs:

    1) Schematic entry1) Schematic entry

    - the software allows user to enter a logic design usinglogic components and to interconnect them on the

    computer screen to form schematic diagram

    2) Text2) Text--based entrybased entry (language-based entry)

    - the software allows user to enter a logic design in the

    form of text using HDL (hardware descriptionlanguage)

    VHDL & Verilog are widely used for programming

    CPLDs and FPGAs.

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    Advantages of PLDs

    Save a lot of space - many more logic circuits can

    be stuffed into a much smaller area compared to

    fixed function logic devices

    Reduce the actual number and cost of device.

    Logic design can be readily changed without

    rewiring or replacing components.

    Generally, a PLDs design can be implementedfaster than one using fixed-function ICs once the

    required language is mastered.

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    - Thank you -