90nm technology

7/29/2019 90nm technology

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Session Title p 2

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– IR Drop

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Steiner tree:minimum length tree

Global routing: Set of steiner treesminimizing total wire length andcongestion.

Global routing computes the topology of each net on a coarse grid(routing bin). The detailed routing (track assignment) is not know.

Primary goal is to compute wire length..

ÎGlobal routing can predict wire length but cannot predict coupling effect.



Session Title p 9

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Variation is +/- 30% for 1MMwire and +80%/-60% for 3MMwires.



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– How can we get early access to detail routing.

– How can we iterate fast enough when detailed routing is required.



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Session Title p 13

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Delay calculator: computes delay between gate output and gateinputs based on extracted RCs.

– Static Timing Analysis engine: propagate the delay in the cells andin the interconnect to check for timing violations.

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– IR Drop

– Cross talk impact on delay.

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– Gates dominate delay. Wire delay can be estimated using wire load model. Synthesisand place and route are two different steps.

QP– Wire delay starts dominating overall delay. Better accuracy is needed in wire delay

estimation:– Placement and Synthesis merge (Physical Compiler, PKS) at the block level

– Floorplanner to estimate top level wires.

QPDQGEHORZ– Wire delay dominates the design. Wire delay depends on cross couplingÎPerformance is unknown before routing.

– Introduction of tools and flow that generate wires as soon as possible (“time to wire”).



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Equivalencechecking

Simulation

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Extraction

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Timing Verification

Wire Load Models







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Design methodology must minimize time to wire and full chip iteration time: Continuousconvergence methodology.

In nanometer designphysical synthesis isused only on thoseblocks that full chipdetailed routingidentifies as notmeeting timing.



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Session Title p 26

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Performance

– Crosstalk

– IR Drop

Reliability

– Hot Electron

– Electromigration

– Wire Self Heat

Manufacturability

– Process Antenna Effect (PAE)

– Metal Density

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Session Title p 29

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Aggressor & Victim Relationship

6SDWLDO– Proximity and Width of conductors

(Capacitance and resistance)

– Coupling location distance from drivers

Failures Caused

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–Signal slews and time of switch



Session Title p 30

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Analysis Requirements– Driver Strength

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Routing topology and RC’s– Timing Analysis to identify slew relationship and edge alignment

– Victims’ net receiver noise margin

Avoidance– Separate victim from Aggressor

– Shield Aggressor

– Reduce victim slew, Increase aggressor slew

– Change Temporal relationship





Session Title p 32

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Failures Caused

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– IR drop in power grid will create variations in delay across the chip

– Performance of a chip roughly varies by 7-9% when vdd is varied by 10%

– Affect clock skew in the clock network

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Session Title p 37


Analysis Requirements

– Characterization of cells’ current consumption

– Power supply network RC’s extraction

– Wire DC and peak current densities based on the current consumption of each

cell and the resistance of the power grid.

– DC current densities are compared to the process limits.

Avoidance

– General estimation of power network using DC or average DC current drawn

per cell and row utilization.

– Network resistance reduction (adding via cuts and increasing or tapering wire

width).









Session Title p 41


Analysis Requirements

– Metal Area to Gate Area ratio

– Metal Side Area to Gate Area ratio– Layer Only Vs Cumulative

Avoidance

– Layer hoping

– Diode insertion during routing

– Diode embedded in cell

– Buffer/Repeater insertion right on the pin inside the block

–

Force pin assignment to last metal on critical nets.

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90nm technology

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