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No. 8-1

Chapter #8: Finite State Machine Design

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No. 8-2

Motivation

Counters:Sequential Circuits where State = Output

General izes to Finite State Mach ines:Outputs are Function of State (and Inputs)Next States are Functions of State and InputsUsed to implement circuits that control other circuits"Decision Making" logic

Appl icat ion of Sequent ial Lo gic Design Techn iquesWord ProblemsMapping into formal representations of FSM behaviorCase Studies

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No. 8-3

Chapter Overview

Concept of the State Machine

Partitioning into Datapath and Control

When Inputs are Sampled and Outputs Asserted

Basic Design A pproach

Six Step Design Process

Alternative State Machine Representation s

State Diagram, ASM Notation, VHDL, ABEL Description Language

Moore and Mealy Machines

Definitions, Implementation Examples

Word Problems

Case Studies

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No. 8-5


Example: Odd Pari ty Checker

Even

[0]

Odd

[1]

Reset

0

0

1 1

Assert output whenever input bit stream has odd # of 1's

StateDiagram

Present State

Even

Even

Odd

Odd

Input

0

1

0

1

Next State

Even

Odd

Odd

Even

Output

0

0

1

1

Symbolic State Transition Table

Output

0

0

1

1

Next State

0

1

1

0

Input

0

1

0

1

Present State

0

0

1

1

Encoded State Transition Table

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No. 8-6


Examp le: Odd Pari ty Checker

Next State/Output Functions

NS = PS xor PI; OUT = PS

D

R

Q

Q

Input

CLK PS/Output

\Reset

NS

D FF Implementation

T

R

Q

Q

Input

CLK

Output

\Reset

T FF Implementation

Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0

Clk

Output

Input 1 0 0 1 1 0 1 0 1 1 1 0

110100110111

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No. 8-7

Concept of State Machine

Timing:When are inputs sampled, next state computed, outputs asserted?

State Time:Time between clocking events

Clocking event causes state/outputs to transition, based on inputs

For set-up/hold time considerations:

Inputs should be stable before clocking event

After propagation delay, Next State entered, Outputs are stable

NOTE: Asynchronous signals take effect immediatelySynchronous signals take effect at the next clocking event

E.g., tri-state enable: effective immediatelysync. counter clear: effective at next clock event

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Concept of State Machine

Example:Positive Edge Triggered Synchronous System

On rising edge, inputs sampled

outputs, next state computedAfter propagation delay, outputs and

next state become stable

Immediate Outpu ts:affect datapath immediately

could cause inputs from datapath to change

Delayed Outp uts:take effect on next clock edgepropagation delays must exceed hold timesOutputs

State Time

Clock

Inputs

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Communicat ing State Machines

Fragment state diagramsInitial inputs/outputs: X = 0, Y = 0

One machine's output is another machine's input

CLK

FSM1

X

FSM2

Y

A A B

C D D

FSM 1 FSM 2

X

Y

A

[1]

B

[0]

Y=0

Y=1

Y=0,1

Y=0

C

[0]

D

[1]

X=0

X=1

X=0

X=0

X=1

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Basic Design Approach

Six Step Process

1. Understand the statement of the Specification

2. Obtain an abstract specification of the FSM

3. Perform a state minimization

4. Perform state assignment (or encoding)

5. Choose FF types to implement FSM state register

6. Implement the FSM

1, 2 covered now; 3~6 covered later (Chap. 9);5 and 6 general ized from the counter design pro cedure

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Basic Design Approach

Example:Vending Machine FSM

General Machine Concept:

deliver package of gum after 15 cents deposited

single coin slot for dimes (10 cents), nickels (5 cents)

no change

Bloc k Diagram

Step 1. Understand the problem:

VendingMachine

FSM

N

D

Res et

Clk

OpenCoin

SensorGum

Release

Mechanis

Draw a picture!

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Vending Machine Example

Tabulate typical input sequences:

three nickelsnickel, dimedime, nickeltwo dimestwo nickels, dime

Draw state diagram:

Inputs: N, D, reset

Output: open

Step 2. Map into m ore sui table abstract representat ion

Reset

N

N

N

D

D

ND

[open]

[open] [open] [open]

S0

S1 S2

S3 S4 S5 S6

S8

[open]

S7

D

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Step 3: State Minimization

Reset

N

N

N, D

[open]

15

0

5

10

D

D

reuse states

wheneverpossible Symbolic State Table

PresentState

0

5

10

15

D

0011001

10011X

N

0101010

10101X

Inputs NextState

0510X51015

X101515X

15

OutputOpen

000X000

X000X1

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Step 4: State Encoding

Next StateD1 D0

0 00 11 0X X0 11 01 1

X X1 01 11 1X X1 11 1

1 1X X

Present StateQ1 Q0

0 0

0 1

1 0

1 1

D

0011001

1001100

11

N

0101010

1010101

01

Inputs OutputOpen

000X000

X000X11

1X

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Parity Checker Example

Step 5. Choo se FFs for implementat ion

D FF easiest to use

D1 D0 Open

D1 = Q1 + D + Q0 N

D0 = N Q0 + Q0 N + Q1 N + Q1 D

OPEN = Q1 Q0

8 Gates

CLK

OPEN

CLK

Q0

D

R

Q

Q

D

R

Q

Q

\ Q1

\reset

\reset

\ Q0

\ Q0

Q0

Q0

Q1

Q1

Q1

Q1

D

D

N

N

N

\ N

D1

D0

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Parity Checker Example

Step 5. Choo sing FF for Imp lementat ion

J-K FF

Remapped encoded state transition table

Next StateD1 D0

0 00 11 0X X

0 11 01 1X X1 01 11 1

X X1 11 11 1X X

Present StateQ1 Q0

0 0

0 1

1 0

1 1

D

00110011001

10011

N

01010101010

10101

Inputs K1

XXXX

XXXX000

X000X

K0

XXXX

010XXXX

X000X

J1

001X

011XXXX

XXXXX

J0

010X

XXXX011

XXXXX

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Implementat ion:

J1 = D + Q0 N

K1 = 0

J0 = Q0 N + Q1 D

K0 = Q1 N

7 Gates

OPENQ1

\ Q0

N

Q0 J

KR

Q

Q

J

KR

Q

Q

Q0

\ Q1

\ Q1

\ Q0

Q1

\reset

D

D

N

N

CLK

CLK

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Alternative State Machine Representations

Why State Diagrams A re Not Enoug h

Not flexible enough for describing very complex finite state machines

Not suitable for gradual refinement of finite state machine

Do not obviously describe an algor i thm:that is, well specifiedsequence of actions based on input data

algorithm = sequencing + data manipulation

separation of control and data

Gradual shi f t tow ards prog ram-like representat ion s:

Algorithmic State Machine (ASM) Notation

Hardware Description Languages (e.g., VHDL)

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Algo r i thm ic State Machine (ASM) Notat ion

Three Primitive Elements:

State Box

Decision Box

Output Box

State Machin e in one statebloc k per state t ime

Single Entry Poin t

Unambig uous Exi t Pathfor each combinat ion

of inputs

Outpu ts asserted high (.H)or low (.L); Immediate (I)or delayed t i l next clock

State

Entry Path

StateName

State Cod e

State Box

ASM

B loc k

State

Output Lis t

Condition

Bo xCondit ional

Output Lis t

Output

Bo x

Ex its to

other ASM Block s

Condition

* ***

T F

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ASM Notat ion

Condition Boxes:

Ordering has no effect on final outcome

Equivalent ASM charts:A exits to B on (I0 & I1 = 1) else exit to C

A 010

I0

I1

T

T

F

F

B C

A 010

I0

T

T

F

F

B C

I1

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Examp le: Pari ty Checker

Nothing in output list implies Z not asserted

Z asserted in State Odd

Input X, Output Z

InputFTFT

Present

StateEvenEvenOddOdd

Next

StateEvenOddOddEven

Output

AA

Symbolic State Table:

Input0101

PresentState

0011

NextState

0110

Output0011

Encoded State Table:

Trace paths to derivestate transition tables

Ev en

Odd

H.Z

X

X

0

1

F

T

TF

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ASM Chart for Vending Machine

0

15

H.Open

D

Reset

00

11

T

T

F

NF

T

F

10

D

10

T

NF

T

F

5

D

01

TN

F T

F

0

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Moore and Mealy Machine Design Procedure

Defini t ions

Moore Machine

Outputs are funct ion

solely of the currentstate

Outputs changesynchronous ly wi th

state changes

Mealy Machine

Outputs depend on

state AND inp uts

Input change causesan immediate output

change

Asynchronous outputs

State Register Clock

State

Feedback

Combinational

Logic for

Outputs a ndNext State

X

Inputsi

Z

Outputsk

Clock

state

feedback

Combinational

Logic for

Next State

(Flip-flop

Inputs)

State

Register

Comb.

Logic forOutputs

Z

Outputsk

X

Inputsi

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State Diagram Equ ivalents

Outputs are associatedwith State

Outputs are associatedwith Transitions

Reset/0

N/0

N/0

N+D/1

15

0

5

10

D/0

D/1

(N D + Reset)/0

Reset/0

Reset/1

N D/0

N D/0

MooreMachine

Reset

N

N

N+ D

[1]

15

0

5

10

D

[0]

[0]

[0]

D

N D + Reset

Reset

Reset

N D

N D

Mealy

Machine

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States vs . Trans it ion s

Mealy Machine typically has fewer states than Moore Machinefor same output sequence

EquivalentASM Charts

Asserts its outputwhenever at least two1s in sequence

Same I/O behavior

Different # of states

1

1

0

1

2

0

0

[0]

[0]

[1]

1/0

0

1

0/0

0/0

1/1

1

0

F F

F F

T

T

T

T

T

F

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Tim ing Behavior of Moore Machines

Reverse engineer the following: why Moore ???

Input XOutput ZState A, B (= Z)

Two Techniques for Reverse Engineering:

Ad Hoc: Try input combinations to derive transition table

Formal: Derive next state/output functions by analyzing the circuit

JC

K R

Q

Q

FFa

J

CK R

Q

Q

FFb

X

X

X

X

\Reset

\Reset

A

Z

\A

\A\B

\B

Clk

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Ad Hoc Reverse Eng ineer ing

Behavior in response to input sequence 1 0 1 0 1 0:

Partial ly DerivedState Transit io n

Table

A0

0

1

1

B0

1

0

1

X0

10101

01

A+?

10?10

11

B+?

10?01

10

Z0

01100

11

X = 1AB = 00

X = 0AB = 11

X = 1AB = 11

X = 0AB = 10

X = 1AB = 10

X = 0AB = 01

X = 0AB = 00

ResetAB = 00

100

X

Clk

A

Z

\Reset

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Formal Reverse Engineer ing

Derive transition table from next state and output combinationalfunctions presented to the flipflops!

Ja = XJb = X

Ka = X BKb = X xor A

Z = B

FF excitation equations for J-K flipflop: Q+ = J \Q +\K Q

A+ = Ja A + Ka A = X A + (X + B) A

B+ = Jb B + Kb B = X B + (X A + X A) B

Next State K-Maps:

State 00, Input 0

State 00State 01, Input 1 State 11

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Complete ASM Chart for the Mystery Moore Machine

Note: Al l Outputs Ass ociated With State Bo xesNo Separate Outpu t Boxes, Intr insic in Moo re Machines

S0 00

X

H.Z

S1 01

X

S3 11

S2 10

H.Z

X

X

0 1

10

0

1

01

M d M l M hi

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Reverse Eng ineering a Mealy Machine

Input X, Output Z, State A, B

State register consists of D FF and J-K FF

D

CR

Q

Q

J

C

KR

Q

Q

X

X

X

Clk

A

A

A

B

B

B

Z

\Reset\Reset

\ A

\ A

\ X

\ X

\ X\ B

DA

DA

M d M l M hi

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Moore and Mealy Machine

Ad Hoc Method

Signal Trace of Input Sequence 101011:

Note gl i tchesin Z!

Outpu ts val id atfo l lowing fal l ing

clock edge

Partial ly completedstate transi t ion tablebased on the signal

trace

A0

0

1

1

B0

1

0

1

X010

1010

1

A+00?

1?01

?

B+10?

1?10

?

Z00?

0?11

?

ResetAB=00

Z =0

X =1AB=00

Z =0

X =0AB=00

Z =0

X =1AB=01

Z =0

X =1AB=10

Z =1

X =0AB=11

Z=1

X =1AB=01

Z =0

X

Clk

A

B

Z

\Reset

100

M d M l M hi

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Formal Method

A+ = B (A + X) = A B + B X

B+ = Jb B + Kb B = (A xor X) B + X B= A B X + A B X + B X

Z = A X + B XMissing Transitions and Outputs:

State 01, Input 0 -> State 00, Output 1

State 10, Input 0 -> State 00, Output 0State 11, Input 1 -> State 11, Output 1A+

B+

Z

M d M l M hi

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ASM Chart for Mystery Mealy Machine

S0 = 00, S1 = 01, S2 = 10, S3 = 11

NOTE: Some Outputs in Output Boxes as well as State BoxesThis is intrinsic in Mealy Machine implementation

S0 00

X

H. ZS1 01

S2 10

X

H.Z

H.Z

S3 11

XX

0

1

0

0 1

1

01

M d M l M hi

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Synchronous Mealy Machine

latched state AND outputs

avoids glitchy outputs!

State Register Clock

Clock

Combinational

Logic for

Outputs and

Next State

state

feedback

X

Inputsi Z

Outputsk

Finite State Machine Word Problems

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Mapping Eng l ish Langu age Descr ipt ion to Formal Speci f icat ions

Four Case Studies:

Finite String Pattern Recognizer

Complex Counter with Decision Making

Traffic Light Controller

Digital Combination Lock

We wi l l use state diagrams and ASM Charts


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Finite String Pattern Recog nizer

A finite string recognizer has one input (X) and one output (Z).The output is asserted whenever the input sequence 010has been observed, as long as the sequence 100 has never been

seen.

Step 1. Understanding the problem statement

Sample input/output behavior:

X: 00101010010Z: 00010101000

X: 11011010010Z: 00000001000


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Finite String Recog nizer

Step 2. Draw State Diagrams/ASM Charts for the strings that must berecognized. I.e., 010 and 100.

Moore State DiagramReset signal places

FSM in S0

Outputs 1 Loops in State


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Exit conditions from state S3:if next input is 0 then have 0100 (state S6)if next input is 1 then have 0101 (state S2)


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Exit conditions from S1: recognizes strings of form 0 (no 1 seen)loop back to S1 if input is 0

Exit conditions from S4: recognizes strings of form 1 (no 0 seen)loop back to S4 if input is 1


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Fini te Str ing Recognizer

S2, S5 with incomplete transitions

S2 = 01; If next input is 1, then string could be prefix of (01)1(00)

S4 handles just this case!

S5 = 10; If next input is 1, then string could be prefix of (10)1(0)S2 handles just this case!

Final State Diagram


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Fini te String Recognizer

Review of Process:

Write down sample inputs and outputs to understand specification

Write down sequences of states and transitions for the sequencesto be recognized

Add missing transitions; reuse states as much as possible

Verify I/O behavior of your state diagram to insure it functionslike the specification


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Complex Coun ter

A sync. 3 bit counter has a mode control M. When M = 0, the countercounts up in the binary sequence. When M = 1, the counter advancesthrough the Gray code sequence.

Binary: 000, 001, 010, 011, 100, 101, 110, 111Gray: 000, 001, 011, 010, 110, 111, 101, 100

Valid I/O behav ior :

Mode Input M0011100

Current State000001010110111101110

Next State (Z2 Z1 Z0)001010110111101110111


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Complex Counter

One state for each output combinationAdd appropriate arcs for the mode control

S0 000

S1 001H.Z 0

M

S3 011

H.Z 1H.Z 0

H.Z1

S2 010

M

M

S6 110

H.Z 2H.Z 1

H.Z 2H.Z 1H.Z 0

S4 100

M

H.Z 2

H.Z 2H.Z 0

M

S5 101

M

S7 111

0 1

0 1

0

1

0

1

0

1

0 1


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Traff ic Ligh t Contro l ler

A busy highway is intersected by a little used farmroad. DetectorsC sense the presence of cars waiting on the farmroad. With no car

on farmroad, light remain green in highway direction. If vehicle onfarmroad, highway lights go from Green to Yellow to Red, allowingthe farmroad lights to become green. These stay green only as longas a farmroad car is detected but never longer than a set interval.When these are met, farm lights transition from Green to Yellow toRed, allowing highway to return to green. Even if farmroad vehiclesare waiting, highway gets at least a set interval as green.

Assume you have an interval timer that generates a short time pulse(TS) and a long time pulse (TL) in response to a set (ST) signal. TSis to be used for timing yellow lights and TL for green lights.


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Picture of Highway/Farmroad Intersection:

Highway

Highway

Farmroad

Farmroad

HL

HL

FL

FL

C

C


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Tabulation of Inputs and Outputs:

Inp ut Signal

resetCTSTL

Outpu t SignalHG, HY, HR

FG, FY, FRST

Descr ipt ion

place FSM in initial statedetect vehicle on farmroadshort time interval expiredlong time interval expired

Descr ipt ionassert green/yellow/red highway lights

assert green/yellow/red farmroad lightsstart timing a short or long interval

Tabulation of Unique States: Some light configuration imply others

StateS0

S1S2S3

Descr ipt ionHighway green (farmroad red)

Highway yellow (farmroad red)Farmroad green (highway red)Farmroad yellow (highway red)


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Refinement of ASM Chart:

Start with basic sequencing and outputs:

S0 S3

S1 S2

H.HGH.FR

H.HRH.FY

H.HRH.FG

H.HYH.FR


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Determine Exit Conditions for S0:Car waiting and Long Time Interval Expired- C TL

Equivalent ASM Chart Fragments

S0 S0

H.HGH.FR

H.HGH.FR

TL TL C

H.STC

H.ST S1

H.HYH.FR

S1

H.HYH.FR

0

0

1

1

0

1

C TL


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S1 to S2 Transition:Set ST on exit from S0Stay in S1 until TS asserted

Similar situation for S3 to S4 transition

S1

H.HYH.FR

TS

H.ST

S2

H.HRH.FG

0 1


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S2 Exit Condition: no car waiting OR long time interval expired

Complete ASM Chart for Traff ic Ligh t Contro l ler

S0 S3H.HGH.FR H.ST

H.HRH.FY

TSTL C

H.ST H.ST

S1 S2H.HY

H.FRH.ST H.HR

H.FG

TS TL + C

0 01

1

10

1

0


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Compare with state diagram:

Advantages of ASM Charts:

Concentrates on paths and conditions for exiting a state

Exit conditions built up incrementally, later combined intosingle Boolean condition for exit

Easier to understand the design as an algorithm

S0: HG

S1: HY

S2: FG

S3: FY

Reset

TL + C

S0

TLC/ST

TS

S1 S3

S2

TS/ST

TS/ST

TL + C/ST

TS

TL C


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Digi tal Combinat ion Lock

"3 bit serial lock controls entry to locked room. Inputs are RESET,ENTER, 2 position switch for bit of key data. Locks generates an

UNLOCK signal when key matches internal combination. ERRORlight illuminated if key does not match combination. Sequence is:(1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) &(3) two more times."

Problem speci f icat ion is incomplete:

how do you set the internal combination?

exactly when is the ERROR light asserted?

Make reason able assumption s:

hardwired into next state logic vs. stored in internal register

assert as soon as error is detected vs. wait until full combinationhas been entered

Our design: registered combination plus error after full combination


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Digital Combinat ion Lock

Understanding the problem: draw a block diagram

InternalCombination

Operator Data

Inputs :Reset

EnterKey-InL0, L1, L2

Outputs :Unlock

Error

UNLOCK

ERR OR

RESET

ENTER

KEY-IN

L0

L1

L2

CombinationLock F SM


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Enumeration of states:

what sequences lead to opening the door?

error conditions on a second pass

START state plus three key COMParison states

START entered on RESET

Exit START when ENTER is pressed

Continue on if Key-In matches L0

START

Reset

Enter

COMP0

KI = L0N

Y

1

0

0

1


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Path to unlock:

Wait forEnter Key press

Compare Key-IN

COMP0

NKI = L0

YIDLE0

Enter

COMP1

N

Y

KI = L1

IDLE1

COMP2

Enter

NKI = L2

YDONE

H.Unlock

Reset

START

1

0

0

1

0

1


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Digi ta l Combinat ion Lo ck

Now consider error paths

Should follow a similar sequence as UNLOCK path, except

asserting ERROR at the end:

COMP0 error exits to IDLE0'

COMP1 error exits to IDLE1'

COMP2 error exits to ERROR3

IDLE0'

Enter

ER ROR1

IDLE1'

Enter

ER ROR2

ERROR3

H.Error

Reset

START

0 0 0

111

Finite State Machine Word ProblemsReset + Enter

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Digi ta l Combinat ion Lo ck

Equivalent State Diagram

Reset

Reset + Enter

Reset Enter

Start

Comp0KI = L0 KI L0

Enter

Enter

Enter

Enter

Idle0 Idle0'

Comp1 Error1

KI L1KI = L1

EnterEnter

EnterEnter

Idle1 Idle1'

Comp2 Error2

KI L2KI = L2

Done

[Unlock]

Error3

[Error]

Reset

Reset Reset

Reset

StartStart

Chapter Review

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Basic Timing Behavior an FSM

when are inputs sampled, next state/outputs transition and stabilize

Moore and Mealy (Async and Sync) machine organizationsoutputs = F(state) vs. outputs = F(state, inputs)

First Two Steps of th e Six Step Procedure for FSM Design

understanding the problem

abstract representation of the FSM

Abstract Representat ions o f an FSM

ASM Charts

Word Problems

understand I/O behavior; draw diagrams

enumerate states for the "goal"; expand with error conditions

8.CH08.rev

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