8254

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§11-5 8254 PROGRAMMABLEINTERVAL TIMER

• Three independent 16-bit programmable counters (timers).– Each capable of counting in binary or BCD

with a maximum frequency of 10MHz.

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In the PCDecoded at port address 40H-43H and has

following functions:1. Generates a basic timer interrupt that occurs at

approximately 18.2Hz.– Interrupts the micro at interrupt vector 8 for a clock

tick.2. Causes DRAM memory system to be refreshed.

– Programmed with 15µs on the PC/XT.3. Provides a timing source to the internal speaker

and other devices.

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8253/4 Timer in the PC CLK0

GATE0

OUT0

CLK2

GATE2

OUT2SPEAKER

BIT1 OF PORT 61HBIT0 OF PORT 61H

1.193M Hz

+5V

8254

18.2 Hz to IRQ0 of 8259[INT 8]

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WHY IS THE DEVICE NEEDED?• It generates accurate time delays under software

control. – Instead of setting up timing loops in software, the

programmer configures the interval timer to match system requirements and programs the counter for the desired delay or for the desired output.

• Some common timer/counter/output functions which microprocessors require are: – real time clock, – event counter, – programmable rate generator, – square wave generator, – complex wave form generator.

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BASIC OPERATION1. The user inputs a Control Word and then an initial

count. – The Control Word itself specifies which Counter is

being programmed and which counting Mode is desired.

2. Counting is enabled via the GATE (G) input.3. Either at the end of a count or during the count,

transitions occur on the Counter OUT pin.– These OUT pin transitions are used to do things in the

system.– The types of OUT pin transitions depend on the Mode

which was programmed.

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pp.430-431 8254 Functional Description

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8254 SYSTEM INTERFACE

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Pin Definitions• A1, A0: The address inputs select one of the

four internal registers with the 8254 as follows:

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Pin Definitions (Cont’d)

• *CS: Chip Select enables the 8254 for programming, and reading and writing.

• *RD/*WR: Read/Write causes data to be read/written from/to the 8254 and often connects to the *IORC/*IOWC.

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Pin Definitions (Cont’d)• CLK: The clock input is the timing source for

each of the internal counters.• GATE (G): The gate input controls the operation

of the counter in some modes.• OUT: A counter output is where the wave-form

generated by the timer is available.

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MAJOR DEVICE BLOCKS

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CONTROL WORD REGISTER• This register is selected by the Read/Write Logic

when A1,A0=11.• If the CPU then does a write operation to the 8254,

the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the counters.

• The Control Word Register can only be written to. – Status information is available with the Read-Back

command.

• There are three Counters. Each is fully independent of the others.– Each Counter may operate in a different Mode.

• Each counter is a 16-bit synchronous down counter.• After power-up, the count value and output of all

Counters are undefined.– Each counter must be programmed before it can be used. – Unused counters need not be programmed.

• Counters are programmed by writing a Control Wordand then an initial count.

• GATE=1 enables counting, GATE=0 disables counting.

COUNTERS

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Internal Block Diagram of a Counter

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CE; OLm, OLl, OL• The actual Counter is “CE(Counting Element)”• OLm and OLl are two 8-bit latches.

– OL is "Output Latch“. – The subscripts m and l stand for "Most significant byte" and

"Least significant byte". – Both are normally referred to as one unit and called just OL. – These latches “follow” the CE as it counts.

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CE; OLm, OLl, OL (Cont’d)• If a suitable Counter Latch Command is sent to the 8254,

the latches capture the present count until read by the CPU. – Once read, the latches return to “following” the CE.

• Note that the CE itself cannot be read. – If the user wants to read the count, it is the OL that is being

read.

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CRm, CRl, CR• There are two 8-bit registers called CRm and CRl.

– These are the Count Register (Most significant byte and Least significant byte.)

– Both are normally just called the CR.• When a new count is written to the counter, the count

is stored in the CR and later transferred to the CE.• If the Counter has been programmed for one byte

counts (either LSB or MSB only) the other byte will be zero.

• Note that the CE cannot be written into. – Whenever a count is written, it is written into the CR.

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pp.431-436 Programming the 8254 • Each counter is individually programmed by writing a

control word, followed by the initial count.• Control Words are written into the Control Word

Register, which is selected when A0,A1=11. – The Control Word itself specifies which Counter is being

programmed.• Initial counts are written into the Counters, not the

Control Word Register. – The A0,A1 inputs are used to select the Counter to be written

into.– The format of the initial count is determined by the Control

Word used.

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WRITE OPERATIONS• For each Counter, the Control Word must be written

before the initial count is written.– The initial count must follow the count format specified in

the Control Word (LSB only, MSB only, or LSB then MSB).

• A new initial count may be written to a Counter at any time without affecting the Counter's programmed Mode in any way.

• However, the actual counting in the Counter will be affected as described in the various Mode definitions.

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Control Word• The Control Word allows the programmer to select the

counter, model of operation, binary or BCD count and type of operation (read/write).

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Control Word Format

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SC – Select Counter

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RW – Read/Write

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M – MODE

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BCD

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Programming the 8254 (Cont’d)• Each counter may be programmed with a count of

1 to FFFFH.– Minimum count is 1 all modes except 2 and 3 with

minimum count of 2.• Each counter has a program control word used to

select the way the counter operates.– If two bytes are programmed, then the first byte (LSB)

stops the count, and the second byte (MSB) starts the counter with the new count.

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MODE DEFINITIONS• The following are defined for use in describing

the operation of the 82C54.– CLK PULSE: a rising edge, then a falling edge, in that

order, of a Counter's CLK input.– Trigger: a rising edge of a Counter’s GATE input.– Counter loading: the transfer of a count from the CR

to the CE.

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ConventionsThe Following Conventions Apply to All Mode Timing Diagrams:• Counters are programmed for binary (not BCD) counting and for

Reading/Writing Least Significant Byte (LSB) only.• The counter is always selected (*CS always low).• CW stands for “Control Word”'; CW = 10 means a control word of

10, hex is written to the counter.• Numbers below diagrams are count values.

– The lower number is the least significant byte. – The upper number is the most significant byte. – Since the counter is programmed to Read/Write LSB only, the most

significant byte cannot be read. – N stands for an undefined count. – Vertical lines show transitions between count values.

There are 6 modes of operation for each counter:

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Mode 0• An events counter enabled with G.• The output becomes a logic 0 when the control

word is written and remains there until N plus the number of programmed counts.

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MODE 0: INTERRUPT ON TERMINAL COUNT

Event counting:• After the Control Word is written, OUT is

initially low and remains low.• When the counter reaches zero, OUT then goes

high and remains high until a new count or a new Mode 0 Control Word is written into the Counter.

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CW=10 LSB=4

After the Control Word and initial count are written to a Counter, the initial count will be loaded on the next CLK pulse.

•This CLK pulse does not decrement the count, so for an initial count of l, OUT does not go high until l + 1 CLK pulses after the initial count is written.

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GATE = 1 enables counting; GATE = 0 disables counting. GATE has no effect on OUT.

LSB=3CW=10

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If a new count is written to the Counter, it will be loaded on the next CLK pulse and counting will continue from the new count.

LSB=3 LSB=2CW=10

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Mode 1Retriggerable One-shot单稳.• The G input triggers the counter to output a 0

pulse for ‘count’ clocks.• Counter reloaded if G is pulsed again.

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MODE 1: HARDWARE RETRIGGERABLE ONE-SHOT

• OUT will be initially high. • OUT will go low on the CLK pulse following a

trigger to begin the one-shot pulse, and remain low until the Counter reaches zero.

• OUT will then go high and remain high until the CLK pulse after the next trigger.

•After writing the Control Word and initial count, the Counter is armed. •A trigger results in loading the Counter and setting OUT low on the next CLK pulse, thus starting the one-shot pulse. •An initial count of l will result in a one-shot pulse l CLK cycles in duration.

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•The one-shot is retriggerable, hence OUT will remain low for l CLK pulses after any trigger.•The one-shot pulse can be repeated without rewriting the same count into the counter.

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•If a new count is written to the Counter during a one-shot pulse, the current one-shot is not affected unless the Counter isretriggered.

–In that case, the Counter is loaded with the new count and the one-shot pulse continues until the new count expires.

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Mode 2Counter generates a series of pulses 1 clock pulse wide.• The separation between pulses is determined by the

count.• The cycle is repeated until reprogrammed or G pin set to

0.

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MODE 2: RATE GENERATOR• Functions like a divide-by-N counter and used to

generate a Real Time Clock interrupt.– OUT will initially be high.– When the initial count has decremented to one, OUT

goes low for one CLK pulse.– Out then goes high again, the Counter reloads the

initial count and the process is repeated.• MODE 2 is periodic. The same sequence is repeated

infinitely.

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•After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse.

–This allows the Counter to be synchronized by software.

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•GATE = 1 enables counting; GATE = 0 disables counting.

•A trigger reloads the Counter with the initial count on the nextCLK pulse; Thus the GATE input can be used to synchronize the Counter.

•Writing a new count while counting does not affect the current counting sequence.

•If a trigger is received after writing a new count but before the end of the current period, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count.

•Otherwise, the new count will be loaded at the end of the current counting cycle. 43

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Mode 3Generates a continuous square-wave with G set to 1.• If count is even, 50% duty cycle otherwise OUT is

high 1 cycle longer.

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MODE 3: SQUARE WAVE MODE

• Typically used for baud rate generation.– Out will initially be high.– When half the initial count is expired, OUT goes low

for the remainder of the count.• MODE 3 is periodic. The same sequence is

repeated infinitely.• An initial count of l results in a square wave with

a period of l CLK cycles.

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Mode 4Software triggered strobe (G must be 1).

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MODE 4: SOFTWARE TRIGGERED STROBE

• OUT will initially be high.• When the initial count expires, OUT will go low

for one CLK pulse and then go high again.• The counting sequence is “triggered” by writing

the initial count.• The Counter is loaded on the next CLK pulse

following writing a Control Word and initial count.

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After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse.

•This CLK pulse does not decrement the count, so for an initial count of l, OUT does not strobe low until l + 1 CLK pulses after the initial count is written.

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GATE = 1 enables counting; GATE = 0 disables counting. GATE has no effect on OUT.

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If a new count is written during counting, it will be loaded on the next CLK pulse and counting will continue from the new count.

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Mode 5Hardware triggered strobe (retriggerable)

• OUT will initially be high.• Counting is triggered by a rising edge of GATE.• When the initial count expires, OUT will go low

for one CLK pulse and then go high again.• The difference between MODE 4 and MODE 5 is

that in MODE 5 the count will not be loaded until the CLK pulse after a trigger.

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•After writing the Control Word and initial count, the counter will not be loaded until the CLK pulse after a trigger. •This CLK pulse does not decrement the count, so for an initial count of l, OUT does not strobe low until l+1 CLK pulses after a trigger.

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The counting sequence isretriggerable.

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•If a new count is written during counting, the current counting sequence will not be affected.

•If a trigger occurs after the new count is written but before the current count expires, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there.

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READ OPERATIONSThe value of a Counter can be read by any one of

the following three methods:

1. A simple READ operation:

a. Select the Counter with the A1,A0 inputs.b. Inhibit the CLK of the selected counter by using

either the GATE input or external logic. • The CLK must be inhibited or the count may be in the

process of changing when it is read, giving an undefined result.

• Note that stopping the CLK stops the count.

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READ OPERATIONS (Cont’d)2. Counter Latch Command (does not disturb the

count in progress):a. It is written to the Control Word Register like a

Control Word, but two bits (D5,D4) distinguishthis command from a Control Word.

b. The selected Counter's OL latches the count at the time the Counter Latch Command is received.

c. The count is held in the latch until it is read by the CPU.

d. The count is then unlatched automatically and the OL returns to “following” the CE.

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READ OPERATIONS (Cont’d)3. Read-Back Command:

a. This command allows the user to check the count value, programmed Mode, and current states of the OUT pin and Null Count flag of the selected counter(s).

b. This command is similar to several Counter Latch Commands, one for each counter latched.

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Read-Back Command Example

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Status Byte

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Gate PinOperations Summary

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OPERATION COMMON TO ALL MODES

• When a Control Word is written to a Counter, all Control Logic is immediately reset and OUT goes to the initial state.

• In some MODES the GATE input is levelsensitive and some are rising-edge sensitive. In some MODES the GATE input is both edge and level sensitive.

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OPERATION COMMON TO ALL MODES (Cont’d)

• The Counter does not stop when it reaches zero. – In MODES 0, 1, 4, and 5 the Counter wraps around

to the highest count (FFFFH or 9999BCD) and continues counting.

– In MODES 2 and 3 (which are periodic) the Counter reloads itself with the initial count and continues counting from there.

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Homework1. Name and briefly explain the mode of operation

for the 8254 given the following timing diagram for the CLK, GATE and OUT connections of one of the counters.

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Homework (Cont’d)2. Give the timing diagram for the OUT pin given that

the gate is held at 1. The 8254 is programmed in Mode 4 (software triggered strobe) and a count of 8 is loaded.

3. Page 456 Problem 59.