8/23-25/05 ELEC5970-001/6970-001 Lecture 2 1 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Power Consumption in a CMOS Circuit Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal [email protected]
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8/23-25/05ELEC5970-001/6970-001 Lecture 21 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.
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8/23-25/05 ELEC5970-001/6970-001 Lecture 2 1
ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic Circuits
Power Consumption in a CMOS Circuit
Vishwani D. AgrawalJames J. Danaher Professor
Department of Electrical and Computer EngineeringAuburn University
Class Projects• Study of leakage dynamic power in nanometer devices• Low leakage technologies• Charge recovery and adiabatic switching circuits• Simulation-based power estimation tool• Transistor-sizing for low power• Logic and flip-flop design for low power• Low power clock distribution• Low power arithmetic circuits• Low power memory design• Benchmarking of low power microprocessors• Low power system design
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 3
Components of Power• Dynamic
– Signal transitions• Logic activity• Glitches
– Short-circuit
• Static– Leakage Ptotal = Pdyn + Pstat
Ptran + Psc + Pstat
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 4
Power of a Transition: Ptran
VVDDDD
GroundGround
CL
Ron
R=large
vi (t) vo(t) ic(t)
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 5
Charging of a Capacitor
V C
R
i(t) v(t)
Charge on capacitor, q(t) = C v(t)
Current, i(t) = dq(t)/dt = C dv(t)/dt
t = 0
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 6
i(t) = C dv(t)/dt = [V – v(t)] /R dv(t) V – v(t) ─── = ───── dt RC
dv(t) dt∫ ───── = ∫───── V – v(t) RC
-t ln [V – v(t)] = ── + A
RC
Initial condition, t = 0, v(t) = 0 → A = ln V -t
v(t) = V [1 – exp(───)]
RC
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 7
-t v(t) = V [1 – exp( ── )]
RC
dv(t) V -ti(t) = C ─── = ── exp( ── )
dt R RC
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 8
Total Energy Per Charging Transition from Power Supply
∞ ∞ -t V -t∫ v(t) i(t) dt = ∫ V [1-exp( ── )] ─ exp( ── ) dt0 0 RC R RC
1= ─ CV2
2
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 11
Transition Power• Gate output rising transition
– Energy dissipated in pMOS transistor = CV2/2– Energy stored in capacitor = CV2/2
• Gate output falling transition– Energy dissipated in nMOS transistor = CV2/2
• Energy dissipated per transition = CV2/2• Power dissipation:
Ptrans = Etrans α fck = α fck CV2/2
α = activity factor
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 12
Short Circuit Current, isc(t)
Time (ns)0 1
Amp
Volt
VDD
isc(t)
0
Vi(t)Vo(t)
VDD - VTp
VTn
tB tE
Iscmaxf
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 13
Peak Short Circuit Current
• Increases with the size (or gain, β) of transistors
• Decreases with load capacitance, CL
• Largest when CL= 0
• Reference: M. A. Ortega and J. Figueras, “Short Circuit Power Modeling in Submicron CMOS,” PATMOS’96, Aug. 1996, pp. 147-166.
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 14
Short-Circuit Energy per Transition
• Escf =∫tB
tE VDD isc(t)dt = (tE – tB) IscmaxfVDD /2
• Escf = tf (VDD- |VTp| -VTn) Iscmaxf /2
• Escr = tr (VDD- |VTp| -VTn) Iscmaxr /2
• Escf = 0, when VDD = |VTp| + VTn
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 15
Short-Circuit Energy
• Increases with rise and fall times of input
• Decreases for larger output load capacitance
• Decreases and eventually becomes zero when VDD is scaled down but the threshold
voltages are not scaled down
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 16
Short-Circuit Power Calculation
• Assume equal rise and fall times
• Model input-output capacitive coupling (Miller capacitance)
• Use a spice model for transistors– T. Sakurai and A. Newton, “Alpha-power Law
MOSFET model and Its Application to a CMOS Inverter,” IEEE J. Solid State Circuits, vol. 25, April 1990, pp. 584-594.
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 17
Short Circuit Power
Psc = α fck Esc
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 18
Psc vs. C
C (fF)
Decreasing Input rise time3ns
0%
45%
0.5ns
Psc
/Pto
tal
0.7μ CMOS
35 75
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 19
Psc, Rise Time and Capacitance
VVDDDD
GroundGround
CL
Ron
R=large
vi (t) vo(t) ic(t)+isc(t)
tftr vo(t)───
R↑
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 20
isc, Rise Time and Capacitance
-tVDD[1- exp(─────)]
vo(t) R↓tf (t)CIsc(t) = ──── = ──────────────
R↑tf (t) R↑tf (t)
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 21
iscmax, Rise Time and Capacitance
Small C Large C
tf
1────R↑tf (t)
iscmax
vo(t) vo(t)
i
t
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 22
Psc, Rise Times, Capacitance
• For given input rise and fall times short circuit power decreases as output capacitance increases.
• Short circuit power increases with increase of input rise and fall times.
• Short circuit power is reduced if output rise and fall times are smaller than the input rise and fall times.
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 23
Technology Scaling
• Scale down by factors of 2 and 4, i.e., model 0.7, 0.35 and 0.17 micron technologies
• Constant electric field assumed
• Capacitance scaled down by the technology scale down factor
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 24
Bulk nMOSFET
n+
p-type body (bulk)
n+
L
W
SiO2
Thickness = tox
Gate
SourceDrain
Polysilicon
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 25
Scaling Factor, α• Constant electric field• L = L / α• W = W / α• tox = tox / α• VDD = VDD/α• Capacitance → 1/α• Gate delay → 1/α• Area → 1/α2
• Power dissipation → 1/α2
• Power density constant• Doping → α
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 26
Technology Scaling Results
Input tr or tf (ns)1%
70%
Psc
/Pto
tal
L=0.7μ, C=40fF
0.4 1.6
12%
L=0.35μ, C=20fF
L=0.17μ, C=10fF
60%
4%
16%
37%
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 27
Effects of Scaling Down
• 1-16% short-circuit power at 0.7 micron
• 4-37% at 0.35 micron
• 12-60% at 0.17 micron
• Reference: S. R. Vemuru and N. Steinberg, “Short Circuit Power Dissipation Estimation for CMOS Logic Gates,” IEEE Trans. on Circuits and Systems I, vol. 41, Nov. 1994, pp. 762-765.
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 28
Summary: Short-Circuit Power
• Short-circuit power is consumed by each transition (increases with input transition time).
• Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power).
• Increasing the output load capacitance reduces short-circuit power.
• Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power.
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 29
Components of Power
• Dynamic– Signal transitions
• Logic activity• Glitches
– Short-circuit
• Static– Leakage
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 30
Leakage Power
IG
ID
Isub
IPT
IGIDL
n+ n+
GroundVDD
R
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 31
Leakage Current Components
• Subthreshold conduction, Isub
• Reverse bias pn junction conduction, ID
• Gate induced drain leakage, IGIDL due to
tunneling at the gate-drain overlap
• Drain source punchthrough, IPT due to short
channel and high drain-source voltage
• Gate tunneling, IG through thin oxide
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 32
Subthreshold Current
Isub = μ0 Cox (W/L) Vt2 exp{(VGS-VTH)/nVt}
μ0: carrier surface mobility
Cox: gate oxide capacitance per unit area
L: channel lengthW: gate widthVt = kT/q: thermal voltage
n: a technology parameter
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 33
IDS for Short Channel Device
Isub = μ0 Cox (W/L) Vt2 exp{(VGS-VTH+ηVDS)/nVt}
VDS = drain to source voltage
η: a proportionality factor
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 34
Increased Subthreshold Leakage
0 VTH’ VTH
Lo
g I
sub
Gate voltage
Scaled device
Ic
8/23-25/05 ELEC5970-001/6970-001 Lecture 2 35
Summary: Leakage Power
• Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power.
• For a gate it is a small fraction of the total power; it can be significant for very large circuits.
• Scaling down features requires lowering the threshold voltage, which increases leakage power; roughly doubles with each shrinking.
• Multiple-threshold devices are used to reduce leakage power.