8.1Pipelining.pdf

Shankar Balachandran*

Associate Professor, CSE Department

Indian Institute of Technology Madras

*Currently a Visiting Professor at IIT Bombay

Digital Circuits and Systems

Spring 2015 Week 8 Module 43

Pipelining

Acknowledgements

MITs Open Course Contents of 6.004

Intro. to Pipelining 2

A Real World Problem

Intro. to Pipelining 3

One Load at a Time

Not a smart thing to do

Intro. to Pipelining 4

Doing N Loads of Laundry

The combinational way

Intro. to Pipelining 5

Doing it the Smart Way

Pipelining

Technically,

N*60 + 30 mins

Steady state:

Infinite supply of inputs

N*60 >> 30, so ignored

Intro. to Pipelining 6

Performance Measures

Intro. to Pipelining 7

(Combinational

(Pipelined

(Combinational

(Pipelined

Back to Circuits For combinational logic:

We cannot get faster

answer

Are we using hardware

effectively?

Intro. to Pipelining 8

Pipelined Circuits

Use registers to keep inputs stable

When H is working on Xi, F and G can work on Xi+1.

This is called a 2-stage pipeline

A valid input at X in clock cycle j

P(X) will have valid output at cycle j+2

Intro. to Pipelining 9

Pipelined Circuits (contd.)

Consider the delays inside the blocks and assume that

the flipflops have zero delays

Intro. to Pipelining 10

Pipeline Diagram

Intro. to Pipelining 11

Results related to a particular input set moves diagonally

through the pipeline diagram

Processed inputs progress through one pipeline stage

each cycle

End of Week 8: Module 43

Thank You

Intro. to Pipelining 12