8096or8097 microcontroller.pdf

15.1 Introduction

The 8096 is a 16 bit microcontroller. It is specially suited for embedded control

applications.

It has all the features of 8051, except bit addressing and bit manipulation.

The additional features present in 8096 are A/D converter, high speed inputs, high

speed outputs, generation of analog output analog voltage and mechanism for self-

checking in runtime.

It has a powerful instruction set and addressing modes.

15.2 Features of 8096

.PU - Dec. 2010, May 2012, Dec. 2012.

(i) It is a 16 bit microcontroller.

(ii) 8096 is been designed for high speed/high performance control applications.

(iii) It has 8 multiplexed input analog to digital converter with 10 bit resolution.

(iv) The high speed I/O section of 8096 comprises a 16 bit timer, a 16 bit counter and 4

input programmable edge detector, 4 software timers and 6 output programmable

event generator.

(v) Its serial port support different modes of operation with programmable baud rates.

(vi) It supports register to register architecture which increases processing speed.

(vii) It is programmable pulse width modulation (PWM) output signals can be used as

control signals to drive a motor or any other application.

(viii) It has 100 instructions that can operate on bit, byte, word, double words.

(ix) It consists of a complete set of 16 bit arithmetic instructions that include multiply

and divide operations.

(x) It allows bit operations. They are done on any bit in the register file or in the special

function register.

(xi) Logical are arithmetic instructions support byte and word operations.

(xii) The watchdog timer can be used to reset the system if software fails to operate

properly.

15.3 Architecture

8096 Microcontroller

CHAPTER

15

.PU - Dec. 2010, May 2011, Dec. 2011, Dec. 2012.

The 8096 family of microcontrollers has several sections, all of which work in an

integrate manner to obtain high performance computing and control.

The major sections include a 16 bit CPU, a programmable high speed input/output

unit, on-chip RAM, on-chip ROM, analog to digital converter, serial port and pulse-

width modulated output for analog to digital converter.

Fig. 15.3.1 shows the internal architecture of 8096 microcontroller. It consists of

several functional units. They are.

(i) CPU with 232 byte register file and register ALU.

(ii) 8KB internal ROM.

(iii) Programmable high speed I/O unit.

(iv) Two 16 bit timers/counters.

(v) Serial ports.

(vi) Pulse width modulator.

(vii) Watchdog timer

(viii) Memory controller.

(ix) Eight multiplexed inputs A/D converter with 10 bit resolution.

Fig. 15.3.1 : 8096 Architecture Block Diagram

The two main buses address bus and data bus are used for inter-processor

communication.

The address bus is 8 bit and data bus is 16 bit.

The data bus transfers data between RALU and register file or special function

registers. (SFRs).

The address bus provides addresses for multiplexed address/data bus connecting to

the memory controller.

The memory controller provides the addresses for the internal ROM and external

memory.

15.4 Memory Organization

.PU - Dec. 2012.

The 8096 can access up to 64 KB memory. The scratch pad register (called as

register file), special function registers, on-chip RAM, on-chip ROM and external

memory space are the main constituents of memory.

Fig. 15.4.1 shows the map of 64kB addressable memory space.

The basic blocks are :

(i) Internal RAM containing

(a) Special function registers (00 to 17H).

(b) Stack pointer (18H and 19 H)

(c) Register file (1AH to EFH)

(d) Power down RAM (F0H to FFH)

This memory area is accessed as data memory. No code can be executed from this

area. The program memory area of 00 to FFH is reserved for internal use of intel

development systems.

(ii) Internal ROM

If the chip has on-chip ROM then it has interrupt vectors, factory test code, internal

program storage. It is available at addresses (2000H 3FFFH).

If the chip does not contain ROM, then these are defined in the external memory.

(iii) External memory or I/O are available at addresses (0100H 1FFDH) and (4000H FFFFH).

(iv) Port 3 and 4 locations (1FFEH and IFFFH) for the reconfiguration if they are not

used as address/data lines.

When the 8096 is reset, address 2080H is loaded to the program counter to give

8 KB of contiguous memory.

GS modiHighlight

GS modiHighlightScratch pad register or register file is said to be a kind of l1 cache, in working, because it just for the storage of the data, calculation etc. temporarily. the main difference between these two is that the data stored in cache is the copied from RAM while in other one it is obtained during processing.

.PU - Dec. 2012.

Fig. 15.4.1 : Memory Map

15.5 CPU Section

.PU May 2011, Dec. 2011.

The central processing unit is responsible for processing arithmetic and logical

operations and for generation of control signals.

The different control signal are generated depending on the instruction being

executed.

The CPU comprises of the following :

(i) Register file

(ii) Register Arithmetic and logic unit (RALU)

(iii) Control unit.

15.5.1 Register File PU - Dec. 2012.

Fig. 15.5.1 shows the complete internal RAM memory map.

The CPU register file has 256 bytes of memory from location 00H to FFH.

No code can be executed from these CPU register file locations. If an attempt is

made to execute instructions from these locations, the instructions will be

automatically fetched from the external memory.

Two 8 bit temporary registers are provided by CPU hardware. They are used to

access the locations from the CPU file.

Fig. 15.5.1 : Internal Ram Structure in 8096

Of the 256 locations, first 24 memory locations 00H 17H are special function registers (SFRs).

SFRs are used to control the on-chip I/O section.

The remaining 232 are RAM locations. These locations can be accessed as bytes,

words or double words.

Each of these 232 locations can be used by the RALU. Hence, there are 232

accumulators.

The first word in the RAM locations 18H and 19H is stack pointer. They can be used

as part of the register file if stack operation is not done. The stock pointer must be

initialized by user program. It can point anywhere in 64 KB (external) memory

space.

The upper 16 bytes (0F0 0FFH) are kept alive, even when the power fails. This

feature is described under power down RAM. These locations receive their power

from VPD pin in power down mode. Hence, only in the power down mode these

locations are alive.

15.5.2 Special Function Registers (SFRs) PU - Dec. 2012.

The CPU communicates with the other resources of 8096 through special function

registers (SFRs) defined in the internal RAM space 00H 19H.

Through these SFRS, the CPU controls the various timers, high speed I/O points,

interrupts, ADC, stack and I/O ports.

Fig 15.5.1 shows the locations and names of SFRs. Many of the SFRs service two

functions, one if they are read and other if they are written.

A brief description of SFRs is given in Table 15.5.1.

Table 15.5.1

Register Description

R0 Zero register. It always reads as zero, useful for a base when

indexing a constant for calculations and comparisions.

AD_RESULT AD_RESULT HI/LO : Low and high order result of A/D converter.

AD_COMMAND Controls the operation of the A/D converter.

HSI_MODE HSI mode set Register-Sets the mode of high speed input (HSI)

HSI_TIME HSI time HI/LO : Contains the time at which high speed input was

triggered.

HSO_TIME HSO time HI/LO : Sets the time for high speed output to execute

the command in the command register.

HSO_COMMAND HSO command Register : Programs what will happen at the time

loaded into HSO time registers.

HSI_STATUS HSI status registers : Indicates which HSI pins were detected at

the time in the HSI time register and current status of pins.

SBUF(TX) Transmit buffer for the serial port. Holds the contents to be

outputted.

SBUF(RX) Receive buffer for the serial port. Holds byte received by serial port.

INT_MASK Interrupt Mask Register enables or disables individual interrupts.

INT_PENDING Interrupt pending register indicates that an interrupt signal

occurred on one of the sources and has not been serviced.

WATCHDOG Watchdog Timer Register : Written periodically to hold off

automatic reset every 64K state times.

Register Description

TIMER1 Timer HI/LO : Timer/high and low bytes.

TIMER2 Timer 2 HI/LO : Timer 2 high and low bytes.

IO PORT0 Port 0 register-levels on pins of port 0.

BAUD_RATE Register that contains the baud rate. It is loaded sequentially such

that lower byte is first placed.

IO PORT 1 Port 1 Register-used to read or write to port 1.

IO PORT 2 Port 2 register used to read or write to port 2.

SP_STAT Serial port status indicates the status of serial port.

SP_CON Serial port control is used to set mode of serial port.

IOS0 I/O status Register 0 : Contains information on the HSO status.

IOS1 I/O status Register 1 : Contains information on the status of timers

and HSI.

IOC0 I/O control Register 0 contains alternate functions of HSI pins.

IOC1 I/O control Register 1 : Control the alternate function of port 2 pins,

timer interrupts and HSI interrupts.

PWM_CONTROL Pulse width modulation control Register : Sets the duration of

PWM pulse.

15.5.3 CPU Buses

There are two buses A (address) and D (data) bus. The different units of CPU

interact with each other through these buses.

The address bus is 8 bit wide and data bus is 16 bit wide. Data bus is used for

sending/receiving data information.

The reason for making address bus 8 bit wide is that internal on-chip RAM

containing SFRs and register file is 256 bytes long and can be directly addressed by

using on 8 bit address.

For 16 bit transfer two memory cycles will be needed.

15.5.4 RALU

The register arithmetic and logic unit (RALU) contains :

(i) 17 bit ALU

(ii) Program counter + incrementer.

(iii) Program status word.

(iv) Loop counter (5 bit).

(v) Two shift registers (17 bit).

(vi) Temporary registers (17 bit).

Fig. 15.5.2 show RALU internal block diagram.

Fig. 15.5.2 : RALU Internal Logic Diagram

For instruction requiring shift for execution, shift registers are provided. e.g. : shift

left, shift right, normalize, multiply, divide etc.

When a 16 bit data is to be shifted, an upper word register/shifter is used. The lower

word/shifter is used along with upper word register/shifter in case of 32 bit shift.

For the instructions that require repetitive shifts (e.g. shift right by 5 bits), a 5 bit

loop counter is useful.

For execution of two operand instructions, a temporary register is provided. This

temporary register stores the multiplier during the execution of multiplication

instruction, or divisor during execution of division instruction.

For the execution of increment/decrement instructions some constants are defined.

The constants 0,1,2 are stored in RALU to execute the instruction faster.

The A bus (address bus) is 8 bit wide. It is used to transfer 16 bit address or data

information to memory controller or other units. A delay circuit is provided. It

facilitate transfer of lower byte followed by delay followed by upper byte to the

memory controller.

Program counter and incrementer are provided in RALU to increment the PC after

execution of each instruction. Thus, it points to the next instruction to be executed.

In case of jump instructions being executed, the program counter is modified

through ALU.

15.5.4.1 Program Status Word

The program status word signifies the status of interrupt flags as well as condition

flags at any instant. Fig. 15.5.3 show PSW.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Z N V VT C I ST Interrupt Mask Register

Fig. 15.5.3 : Program Status Word (PSW)

Z : Indicates that the result of last arithmetic/logic instruction was zero.

N : Indicates that the last instruction generated negative result.

V : Result generated in outside the range that can be expressed in the destination data

type thus causing overflow.

VT : When the V flag is set, VT (overflow trap) is also set. However, it can be reset by

certain explicit instructions. It is useful in debugging the program.

C : Indicates that a bit is shifted out of MSB or ISB position because of arithmetic or

shift operations.

ST : Can be used for controlling rounding after right shift called sticky bit. It indicates that 1 has been shifted first to c flag and then out during right shift.

I : It is set by EI instruction and cleared by DI instruction. It indicates global interrupt

enable/disable.

These conditional flags (except I) can be used in conditional jump instructions.

15.5.5 Control Unit

The control unit contains the instruction register, the decoder and timing unit to

generated various control signals. The instruction is transferred to the control unit

through A bus and is stored in the instruction register. The instruction is decoded

and the required signals are generated for RALU control.

15.5.6 Memory Controller

The memory controller is used as the interface between RALU and external memory

or on-chip ROM.

The 8 bit wide address bus is used to transfer the address and data between RALU

and memory controller.

Whenever RALU wants an instruction/data from memory it should send the lower

byte of address on address bus followed by the upper byte of address.

The memory controller interacts with the external memory through an external

address/data bus AD0 AD15 (ports 3, 4).

15.6 I/O Section

.PU May 2011, Dec. 2011.

All of the on-chip I/O feature of 8096 can be accessed through the special function

registers.

There are seven major I/O functions.

Table 15.6.1 lists these I/O functions.

Table 15.6.1 : Major I/O Functions

I/O functions

High speed input unit Provides Automatic recording of events.

High speed output unit Provides automatic triggering of events and real time

interrupts.

Pulse width

modulation

Output to drive motors or analog circuits.

A to D converter Provides analog to digital conversion

Watchdog Timer Resets 8096 if a malfunction occurs.

Serial port Provides synchronous or asynchronous link.

Standard I/O lines Provide interface to external world.

15.6.1 Timers

There are two 16 bit-timers : Timer 1 and Timer 2.

Timer 1 is a 16 bit free running timer. It is used to synchronize events to real time.

Timer 2 can be clocked externally. It synchronizes events to external occurrences.

The high speed I/O unit is coupled to the timers. HSI records the value when

transitions occurs on timer 1. HSO causes transitions to occur based on values of

Timer 1 or Timer 2.

15.6.1.1 Timer 1

Timer 1 is used to provide real time clock for external events that are recorded on

High Speed Input (HSI) lines or which are generated on High Speed Output (HSO)

lines of 8096.

The input clock is

XTAL frequency

24 i.e. it is clocked once every eight state times.

(e.g. : for a 12 MHz, the state time is 0.25 s. Hence period of Timer 1 clock is 2 s).

It can be reset only by executing a reset.

The only other way to change its value is by writing to 000CH. But it is a test mode

that sets both the timers to 0FFFXH and should not used in programs.

15.6.1.2 Timers 2

Timer 2 is an event counter as if uses an external clock source. It can have on of

following sources as clock :

(i) Timer 2 clock (port p 2.3)

(ii) High speed input line no. 1.

The selection of clock source can be done by the user programming the bit 7 of I/O

control register 0. (IOC0.7).

Timer 2 is used for generating high speed outputs. The maximum speed of timer 2 is

once per eight state times.

Timer 2 is incremented by transitions (one count by each falling edge or rising edge).

GS modiHighlight

GS modiHighlight

GS modiHighlight

GS modiHighlight

GS modiHighlight

GS modiHighlight

GS modiHighlight

GS modiHighlight

GS modiHighlightPurpose of timer.Its period.How to reset it.

GS modiHighlight

GS modiHighlightAbout th timer 1 and timer2.about there application.about there about her period.about how to reset them.about the timer interrupt.

Timer 2 can be reset by the following methods.

(i) by executing a reset.

(ii) by setting IOC0, 1

(iii) triggering the HSO channel 14 (0EH).

(iv) by setting HIS.0 = 1 or IOC0.3 = 1 and pulling TRST.

Fig. 15.6.1 shows different methods of manipulating Timer 2.

Fig. 15.6.1 : Timer 2 Clock and Reset Options

15.6.1.3 Timer Interrupts

The two Timers 1 and Timer 2 can be used to trigger a timer overflow interrupt and

set a flag in the I/O status register 1 (IOS1). The interrupts are controlled by IOC1.2

and IOC1.3.

The flags are set in IOS1.5 and IOS1.4. The enabling and disabling of timer

interrupts are controlled by the interrupt mass register bit 0. In all cases, setting a

bit enables a function while clearing a bit disables it.

15.6.2 High Speed Inputs (HSI)

The HSI unit can be used to record the time at which and event occurs with respect

to Timer 1.

There are 4 lines. (HSI.0, HSI.1, HSI.2 and HSI.3). These are used in this mode to

record upto 8 events.

HSI.2 and HSI.3 are bidirectional pins. They can be used as HSO.4 and HSO.5.

The I/O control registers IOC0 and IOC1 are used to determine the functions of

these pins.

Fig. 15.6.2 shows HSI unit block diagram.

Fig. 15.6.2 : HSI Unit

It can measure pulse widths and record times of events with a 2 s resolution.

15.6.2.1 HSI Modes

For each HSI there are 4 modes of operation.

The HSI mode register is used to control the pins that look for type of events.

Fig. 15.6.3 shows the HSI mode register.

Where each 2-bit mode control field

Defines one of 4 possible modes :

00 8 positive transitions

01 Each positive transition

10 Each negative transition

11 Every transition (Positive and negative)

Fig. 15.6.3 : HSI Mode Register

The information is then stored in a sevel level FIFO for later retrieval.

High and low levels of inputs require to be held for 1 state time to ensure proper

operation.

The maximum input speed is 1 event every 8 state times except when the

8 transition mode is used, is which one transition per state is allowed.

GS modiHighlight

The HSI lines can be enabled and disabled using bits IOC0 at location 0015H.

Fig. 15.6.4 shows the bit locations that control the HSI pins.

Fig. 15.6.4 : IOC0 Control of HSI Pins

15.6.2.2 HSI FIFO

When an HSI event occurs, a 8 20 FIFO stores the 16 bits of Timer 1 and 4 bits

indicating the state of 4 HSI lines at the time the status is read.

It can take upto 8 state times for the information to reach the holding register.

Hence, 8 state times are allowed between consecutive reads of HSI_TIME.

When the FIFO is full, an additional event for a total of 8 events can be stored

considering the holding register as a part of FIFO.

If the FIFO and holding register are full, any additional event will not be recorded.

It will cause an overflow condition.

15.6.2.3 HSI Interrupts

HSI unit generates interrupts in one of two methods determined by IOC1.7.

If a bit is 0, then an interrupt is generated each time a value is loaded into the

holding register. If bit is 1 an interrupt is generated when the FIFO has six entries

in it.

All the interrupts are rising edge triggered. Hence, if IOC1.7 = 1 then the processor

will not be re-interrupted till the FIFO contains 5 or less records.

The interrupts can also be generated by HSI.0 pin that has its own interrupt vector

location 2008H. Thus, an HSI unit generates interrupts in 3 methods.

15.6.2.4 HSI Status

The status of HSI FIFO is shown by bits 6 and 7 of the I/O status register 1 (IOS1).

If bit 6 is 1, the FIFO contains atleast 6 entries. If bit 7 is 1, the FIFO contains

atleast one entry and the holding register has been located.

The FIFO can be read after verifying it contains valid data. While reading or testing

bits in IOS1 it is essential to store the byte and then test the stored value.

The HSI can be read in two steps. Initially the HSI status register is read inorder to

obtain the current state of the HSI pins and which pins have changed at the

recorded time.

Fig. 15.6.5 shows the HSI status register.

Where for each 2 bit status field the low bit indicates whether or not an even has occurred on this

pin at the time in HSI time and the upper bit indicates the current status of the pin.

Fig. 15.6.5 : HSI Status Register

Then the HSI time register is read. Reading the time register unloads one word of

the FIFO, so if the time register is read before the status register, the information in

the status register is lost.

It is at location 06 H. The HSI time registers are at located 04 and 05H.

If the HSI time and status registers are read without the holding register being

loaded, the values read will be undeterminable.

15.6.3 HSIO Shared Pins

The lines HSO.0 and HSO.5 are sheared with HSI lines. HSO.4 and HSO.5 are

sheared with HSI.2 and HSI.3.

The bits 4 and 6 of I/O control register 1 (IOC 1) are used to enable HSO.4 and

HSO.5 as outputs.

15.6.3.1 HSO CAM

Fig. 15.6.6 shows block diagram of HSO unit.

GS modiHighlight

Fig. 15.6.6 : High Speed Output Unit

A content addressable memory file is the main component of the HSO. It stores upto

8 events that are pending to occur. Every state time one location of CAM is

compared with the two timers. After 8 state times, the entire CAM is been searched

for time matches.

If a match occurs a specified event will be triggered and that location of CAM will be

made available for another pending event.

Each CAM register is 23 bits wide. Fig. 15.6.7 shows the format of command to HSO

unit.

Fig. 15.6.7 : HSO Command Tag Format

To enter a command into CAM file, write 7 bit command tag to location 0006H

followed by time at which action is to be carried into word address 0004H.

It is essential to disable interrupts while writing a command tag for HSO. If an

interrupt occurs during the time between writing the command tag and loading the

time value, then the ISR writes to HSO time register. The command tag is written to

CAM. The command tag from main program will not be executed.

15.6.3.2 HSO Interrupts

The HSO unit can generate two type of interrupts. The HSO execution interrupts

and the timer interrupt.

The HSO execution interrupts (vector = 2006 H) is generated when HSO commands

operate one or more of six output pins. However it is a maskable interrupt.

The software timer interrupt is generated by any other HSO command like

triggering the A/D, resetting Timer 2 or generating software delay.

15.6.3.3 HSO Status

The holding register must be empty before writing to HSO. If the holding register is

not empty, it will overwrite value in the holding register.

The I/O status register (IOS0) bits 6 and 7 indicted status of HSO unit.

If IOS0.6 = 0, holding register is empty and atleast one CAM register is empty.

If IOS0.7 = 0, the holding resister is empty.

15.6.3.4 Clearing HSO

All 8 CAM locations are compared before any action is taken. It allows a pending

external event to be cancelled by writing the opposite event to the CAM.

However, if an entry is placed in the CAM it cannot be removed till either the

specified timer matches the written values or chip is reset.

Internal events are not synchronized to timer 1. Hence they cannot be cleared.

It includes events on HSO channels 8 through F and all interrupts. The interrupts

are not synchronized. Hence, it is possible to have multiple interrupts at same time.

15.6.3.5 Using Timer 2 with HSO

The timer 1 is incremented once every 8 state times. If it is being used as a reference

timer for the HSO action, then the comparator can observe all 8 CAM registers

before Timer 1 changes its value.

Timer 2 is synchronized to allow it to change to a maximum rate of once per 8 state

times.

The Timer 2 increments on both the edges of the input signal.

If Timer 2 is used as a reference, care must be taken that the Timer 2 is not reset

prior to highest value for a Timer 2 match in the CAM because HSO CAM holds the

pending event till a time match occurs. If match is not reached then the event

remains pending in the CAM fill the 8096 is reset.

When Timer 2 is reset using HSO unit additional, care must be taken. This is

because the HSO event is an internal event. It can happen at any time in the eight

state time window.

If two events are scheduled such that they must occur at the same time as the

Timer 2 reset then they must be logged into the CAM with a Timer value of zero.

If this method is used to design a programmable modulo counter, the count will

remain at the maximum value of Timer 2 till a reset Timer 2 command is given.

The count remains zero for a transition that would change the count value from N

to zero and then change on the next transition.

15.6.3.6 Software Timers

At present times the HSO can be programmed to generate interrupts. At a time four

software interrupts can be used.

A software Timer flag is set by the HSO unit every time a programmed time is

reached. An interrupt will be generated if the interrupt bit in the command tag is

set. The Interrupt Service Routine (ISR) can then observe the contents of the I/O

status register 1 (IOS1) to tell which of the software timers has expired and

generated the interrupt.

When the HSO resets Timer 2 or starts an A / D conversion it can be programmed to

generate a software timer interrupt. There is no flag to indicate the occurrence of

event.

Multiple interrupts can also be generated.

15.6.4 Pulse Width Modulation Output

Fig. 15.6.8 shows the block diagram of a pulse width modulation circuit. It

comprises of PWM register, PWM counter and comparator.

Fig. 15.6.8 : Pulse width modulated circuit

The PWM output is set to one when the counter value is zero.

The 8 bit is incremented every state time. If the counter value matches with the

value in the PWM register the output is switched low.

Incase the counter overflows the output is again switched high.

Fig. 15.6.9 shows the PWM output waveforms.

The output is low when the value of PWM register is 00. The output waveform is

variable duty cycle pulse that repeats every 256 state times. (64 s at 12 MHz).

By writing the PWM register at location 17H, changes are made in the duty cycle.

Normally motors need PWM waveform for efficient operation. If the PWM waveform

is integrated it produces a DC level that can be changed in 256 steps by modifying

the duty cycle.

A Port 2 pin5 is shared with the PWM output. Hence, both these features cannot be

used at the same time. The PWM function is selected by IOC01. 0 bit is set.

Fig. 15.6.9 : PWM outputs

15.6.5 Serial Port

The 8096 has an on-chip serial port to minimize the number of chips needed in the

system.

It has one synchronous and three asynchronous mode.

In the asynchronous modes baud rate of upto 18.5 Kbaud can be used while in

asynchronous mode baud rates upto 1.5 Mbaud are available.

The chip has a baud rate generator that is independent of Timer 1 and Timer 2.

The asynchronous modes are full duplex i.e. they can simultaneously transmit and

receive. Also they are double buffered i.e. they can begin reception of the second data

byte before a previously received byte has been read from the receive register.

The serial port registers used for transmission and reception are SBUFTx and

SBUFRx. Both these registers share same address 07H. They are physically

separate.

The SBUFTx register hold data that is ready for transmission while SBUFRx

register has data that is received by the serial port.

Fig. 15.6.10 shows the serial port status / control register. Control of serial port is

provided through the SPCON / SPSTAT register.

Some bits are read only while some bits are write only.

Fig. 15.6.10 : Serial port control / status register

Note : RI and TI are cleared when SPSTAT is read.

15.6.5.1 Serial Port Modes

The four modes of serial port are modes 0, 1, 2 and 3.

Mode 0

It is a synchronous mode. It is commonly used for interfacing to shift registers for

I/O expansion.

In this mode the port outputs a pulse train on the TxD pin and either transmits or

receives data on the RxD pin.

Fig. 15.6.11 shows timing diagram.

Fig. 15.6.11 : Serial port mode 0 timing

Mode 1

It is standard asynchronous mode, 8 bits plus a stop bit and start bit are sent or

received. Hence, total frame size is of 10 bits.

If parity is enabled (PEN = 1) then an even parity bit is transmitted instead of 8th

data bit.

It is commonly used for CRT terminals. Fig. 15.6.12 shows mode 1 data frame.

Fig. 15.6.12 : Mode 1 data frame for serial port

Mode 2

It is an asynchronous 9th bit recognition mode.

11 bit frames are transmitted through the TxD and are received through RxD start

bit 0, 8 data bits, a programmable 9th bit and one stop bit.

A 0 or 1 can be assigned to the 9th data bit using the 88 bit in control register before

writing to SBUFTx. This bit can be used to provide a selective reception on the data

link.

The serial port interrupt and receive interrupt (RI) will not be activated till the 9th

received bit is 1 during the reception of data.

Mode 2 is used with 3 for multiprocessor communication.

Mode 3

It is also an asynchronous 9th bit mode. 11 bit frames a transmitted with one start

bit, 8 data bits, a programmable 9th bit and one stop bit. 11 bit data frame is

identical to data frame of mode 2.

The only difference is that the 9th bit becomes a parity bit. If parity is not enabled

(PEN = 0), the TBS controls the status of ninth transmitted bit. It must be set before

each transmission. On reception, if PEN = 0, the RB8 bit indicates the state of the

ninth received bit.

If the parity is enabled i.e. PEN = 1 then the same bit is called (RPE) receive parity

error. It is used to indicate a parity error.

Fig. 15.6.13 shows the data frame for Mode 2 and 3.

Fig. 15.6.13 : Serial port mode 2 and 3 frames

15.6.5.2 Controlling the Serial Port

The status/control register can be used to control the operation of the serial ports.

Fig. 15.6.10 shows serial port control/status register. It is divided into two sections.

SPSTAT (read only) and SPCON (write only).

TB8 is cleared after each byte is transmitted. RI and TI bits are cleared when

SPSTAT is accessed.

15.6.5.3 Multiprocessor Communication

Modes 2 and 3 can be used for multiprocessor configuration.

Fig. 15.6.14 : Multiprocessor communication

If the 9th received bit is not set in mode 2 then the serial port interrupt is not

activated. This feature is used in multiprocessor systems.

When the master processor wishes to transmit a block of data to one of its several

slaves then it first sends an address frame that identifies the target slave.

An address frame will differ from the data frame by the 9th data bit. If the 9th data

bit is 1 then it is an address frame, if bit is 0 then it is a data frame.

A data frame does not interrupt a slave in mode 2. However an address frame

interrupts all slaves so that each slave can examine the received byte and observe if

it is being addressed.

The addressed slave will switch to mode 3 inorder to receive the coming data frames.

The slaves that were unaddressed remain in mode 2 and do not receive any byte.

15.6.5.4 Determining Baud Rates

The baud rates for all the modes are controlled with the help of a baud rate register.

It is a byte wide register that is sequentially loaded with two bytes. It internally

stores the value as a word.

The least significant byte is loaded to the register followed by the most significant

byte.

The most significant byte of the baud value determines the clock source for the baud

rate generator.

If a bit is one, the XTAL1 pin is used as source, if bit is zero, the T2 CLK pin is used.

The baud rate formulas are given below :

Using XTAL1

Mode 0 : Baud rate = XTAL1 frequency

4* (B + 1) ; B0

Others : Baud rate = XTAL1 frequency

64* (B + 1)

Using T2 CLK

Mode 0 : Baud rate = T2 CLK frequency

B ; B0

Others : Baud rate = T2 CLK frequency

16 * B ; B0

Note : B cannot be equal to 0, except when using XTAL1 in other mode than mode 0.

The vaiable B is used to represent the least significant 15 bits of the value loaded into the baud rate register. The maximum value of B is 32767. Table 15.6.2 gives

baud rates for values 10, 11, 12 MHz.

Table 15.6.2 : Baud rates for 10, 11, 12 MHz

XTAL1 frequency = 12.0 MHz

Baud rate Baud register value

19.2 K 8009H

9600 8013H

4800 8026H

2400 804DH

1200 809BH

300 8270H


19.2 K 8008H

9600 8011H

4800 8023H

2400 8047H

1200 808EH

300 823CH


19.2 K 8007H

9600 800FH

4800 8020H

2400 8040H

1200 8081H

300 8208H

15.6.6 I/O Ports 0, 1, 2, 3 and 4

8096 has five 8 bit I/O ports. Some of them are input ports while some of the ports

are output ports and other ports are bidirectional and have alternate functions.

The input ports connect to the internal bus through an input buffer.

The output ports connect through the output buffer to an internal register that holds

the output bits.

Bidirecctional ports comprise of an internal register, an input buffer and an output

buffer.

When an instruction accesses a bidirectional port as source register, the value comes

from the port pins, not the internal register.

15.6.6.1 Port 0

Port 0 is an input port. It shares its pins with the analog inputs to the A/D

converter.

15.6.6.2 Port 1

A is a quasi-bidirectional I/O port. The word quasi-bidirectional means that the port pin has a weak internal pull up that is always active and an internal pull-down

than can be on/off.

The pins logic level can be controlled by an external pull-down if the internal pull-down is left off. (i.e. a 1 is written).

A quasi-bidirectional port will source current if externally held it. It will pull itself

high if it is left unconnected.

If the processor writes to the pins of a quasi-bidirectional port it actually writes into

the register that drives the port pin.

If the port pin is to be used as an input then the software must write a one to SFR

bit. This causes the low impedance pull down device to turn off and leave the pin

pulled with a high impedance pull up device that can be driven by the device that

drives the input.

15.6.6.3 Port 2

It is a multi-functional port.

Table 15.6.3 gives Port 2 functions.

Table 15.6.3 : Port 2 functions

Port Function Alternate Function Controlled by

P2.0 Output TxD (Serial Port Transmit) IOC1.5

P2.1 Input RxD (Serial Port Receive) in Model -3 N/A

P2.1 Output RxD (Serial Output Port) in Mode 0 N/A

P2.2 Input External interrupt IOC1.1

P2.3 Input T2CLK (Timer 2 input) IOC1.7

P2.4 Input R2RST (Timer 2 Reset) IOC0.5

P2.5 Output PWM (Pulse Width Modulation) IOC1.0

P2.6 Quasi-bidirectional N/A

P2.7 Quasi-bidirectional N/A

15.6.6.4 Ports 3 and 4/ AD0 AD15

These pins serve as bidirectional ports with open drain outputs or system bus pins

used by memory controller when it accesses external memory.

If the EA line is low, it serves as system bus. If

EA line is set then they are used

as Ports. The port pins and their system bus functions are given below :

Port Pin System Bus Function

P3.0 AD0

P3.1 AD1

P3.2 AD2

P3.3 AD3

P3.4 AD4

P3.5 AD5

P3.6 AD6

P3.7 AD7

P4.0 AD8

P4.1 AD9

P4.2 AD10

P4.3 AD11

P4.4 AD12

P4.5 AD13

P4.6 AD14

P4.7 AD15

15.6.7 Status and Control Registers

15.6.7.1 I/O Control Registers

There are two I/O control register, IOC0 and IOC1.IOC0 controls Timer 2 and HSI

lines. IOC1 controls some pin function, interrupt sources and two HSO pins.

15.6.7.2 I/O Control Registers 0 (IOC0)

The address of IOC0 control register is 0015H. Fig. 15.6.15 shows format for I/O

control register0 (IOC0).

The four HSI lines can be enabled or disabled to the HSI unit by setting or clearing

bits in IOC0.

The Timer 2 functions include clock and reset sources can be determined by IOC0.

0 HSI.0 input Enable/Disable

1 Timer 2 Reset each write


3 Timer 2 External Reset Enable/Disable

4 HSI.2 Input Enable/Disable

5 Timer 2 Reset Source HSI.0/T2RST


7 Timer 2 clock source HSI 1/T2CLK

Fig. 15.6.15 : I/O Control Register 0 (IOC0)

15.6.7.3 I/O Control Register 1 (IOC1)

The address of IOC1 control register is 0016H. Fig. 15.6.16 shows format of I/O

control register 1.

0 Select PWM/Select P 2.5

1 External Interrupt ACH7/

EXTINT

2 Timer 1 overflow interrupt Enable/

Disable

3 Timer 2 overflow interrupt Enable/

Disable

4 HSO.4 output Enable/

Disable

5 Select TXD/Select P2.0

6 HSO.5 output Enable/

Disable

7 HSI interrupt

FIFO FULL /

Holding Register Loaded

Fig. 15.6.16 : I/O Control Register 1 (IOC1)

It is used to select some pin functions and enable / disable some interrupt sources.

Pin P2.5 can be selected to PWM output. The external interrupt source can be

selected to EXTINT or analog channel 7(A CH7).

Timer 1 and 2 overflow interrupts also can be individually enabled or disabled.

The HSI interrupt can be selected inorder to activate either when there is 1 FIFO

entry or 7.

The port pint P2.0 can be selected to TXD output. HSO.4 and HSO.5 can be enabled

or disabled to HSO unit.

15.6.7.4 I/O Status Register 0 (IOS0)

Its address is 0015H. Fig. 15.6.17 shows IOS0 register. It holds the current status of

HSO lines and CAM.

0 HSO.0 current state






6 CAM or Holding Register if Full

7 HSO Holding Register is Full

Fig. 15.6.17 : I/O Status Register 0(IOS0)

15.6.7.5 I/O Status Register 1 (IOS1)

Its address is 0016H. It shares the address of IOC1 control register.

Fig. 15.6.18 shows IOS1 status register.

0 Software Timer 0 expired.

1 Software Timer 1 expired



4 Timer 2 has overflow

5 Timer 1 has overflow

6 HSI FIFO is FULL

7 HSI Holding Register Data Available

Fig. 15.6.18 : IOS1 Stats Register

It contains the status bits for timers and HS I/O. Each access to this register clears

all time related flags. Hence, it is important to store a byte in temporary location

before attempting to test bit.

15.6.8 A/D Converter

The A/D converter on 8096 provides 8 input channels with a 10 bit digital output.

The channels are multiplexed. For A/D conversion successive approximation method

is used.

The digital output is equivalent to ratio of input voltage divided by the analog

supply voltage. If ratio is unity then result is all ones.

15.6.8.1 A/D Conversion Time and Formula

On 8096 each conversion need 168 state times (42 s at 12 MHz) independent of

accuracy of value of input voltage.

On 8096 BH each conversion requires 88 state times (22 s at 12 MHz) independent

of accuracy or value of input voltage.

The analog input voltage should be in range of 0 to VRFF A/D result is calculated as,

= 1023 (i/p voltage ANGND)

(VREF ANGND)

The change in VREF or ANGND effects the output of the converter. It is

advantageous if a radiometric sensor is used as these sensors have an output that can be

measured in proportion of VREF.

15.6.8.2 A/D Commands

ACH0 through ACH8 are 8 analog inputs. These inputs are shared with the pins of

port 0. Fig. 15.6.19 shows A/D command register.

The analog channels are multiplexed. Any one of the eight inputs can be sampled for

A/D conversion at a time.

The A/D command register at location 02H selects which channel is to be converted

and whether the conversion is to start immediately or when an HSO channel trigger

it.

The A/D command register must be written for each conversion, even if the HSO is

used as trigger.

Fig. 15.6.19 : A/D Command Register

15.6.8.3 A/D Output

The output of analog conversions are read from A/D Result.

The register at location 02 and 03 H. These registers are on a word boundary. They

need to be read as individual bytes. Fig. 15.6.20 shows A/D result register.

Fig. 15.6.20 : A/D Result Register

15.6.9 Watchdog Timer (WDT)

The watchdog timer is a method of recovery from software upset.

After it is initialised, if the software fails to reset the watchdog at least every 64 K

state times, a hardware reset will be initiated. The system will not restart.

The watchdog timer is a 16 bit counter. It is incremented each and every state time.

It is cleared by program after periodic interval. It is not allowed to overflow.

If a program does not properly progress then an overflow occurs. As a result of

overflow the hardware causes the system to restart and prevents the controller from

causing a malfunction for longer than 16 ms in case a 12 MHz oscillator is used.

In reset the watchdog timer can be disabled.

A clear WDT instruction enables it. Code is first written to WDT register. The

timer is cleared by writting a 01EH followed by 0E1H to WDT register at memory location 00AH.

After WDT in initialized, it cannot be disabled by software.

The only method to disable WDT is to hold the RESET pin at 2 to 2.5 volts. Voltage

above 2.5 V on pin can damage the WDT. Hence, this method is not recommended

for normal operation. It is only used for debugging.

15.7 Reset

The 8096 must be reset each time power is turned on. To complete a reset, the

RESET pin must be held active low for atleast 2 state times after VCC, oscillator and

back bias generator have stabilised. Once, the reset is made high, 8096 executes a

rest sequence that takes 10 state times.

The I/O lines and the control lines are reset within 2 state times after reset is low.

Before that the status of I/O lines is indeterminate.

After 10 state times the rest state of SFRs is listed in Table 15.7.1.

Table 15.7.1 : Reset values of SFRs

Register Reset Value

Port 1 xxxxxxxxB

Port 2 xx0xxxx1B

Port 3 11111111B

Port 4 11111111B

PWM control 00H

Serial port (Transmit) Undefined

Serial port (Receive) Undefined

Baud rate Register Undefined

Serial post control xxxx0xxxB

Serial port status x00xxxxxB

A / D Command Undefined

A / D Result Undefined

Interrupt Pending Undefined

Interrupt Mask 00000000B

Register Reset Value

Timer 1 0000H

Timer 2 0000H

Watch dog Timer 0000H

HSI mode xxxxxxxxB

HSI status Undefined

IOS0 00000000B

IOS1 00000000B

IOC0 x0x0x0x0B

IOC1 x0x0xxx1B

HSI FIFO Empty

HSO CAM Empty

HSO SFR 00000000B

PSW 0000H

Stack pointer Undefined

Program counter 2080H

Table 15.7.2 shows other conditions following a reset.

Table 15.7.2

Pin Reset Value

RD

High

WR /

WRL

High

ALE / ADV

High

BHE /

WRH

High

INST Low

HSO Lines xx0000B

The stack pointer and interrupt pending register are undefined. They need to

initialised in software.

The interrupts are disabled by mask register and PSW9 after reset.

The RESET line can be used to start the microcontroller 8096 at an exact state time

so that it is synchronized with the test equipment and other chips.

RESET is active low. For synchronization with peripherals, it is made high on rising

edge of XTAL1.

15.8 Basic Timing

8096 needs an input clock frequency

between 6 MHz and 12 MHz. The

frequency can be directly applied to

XTAL 1.

XTAL1 and XTAL2 are the inputs and

outputs of an inverter. A crystal is

used at these pins to generate the

clock.

Fig. 15.8.1 shows block diagram of an

oscillator.

Fig. 15.8.1 : Block diagram an oscillator

15.9 Internal Timings

The oscillator frequency is divided by 3 to generate three internal timing phases as

shown in Fig. 15.9.1.

Each of the phases repeat every 3 oscillator periods 3 oscillator periods are referred

to one state time.

The internal operations are synchronized to phase 1, 2 or 3 each of which have 33%

duty cycle.

Phase 1 is representated by CLKOUT signal.

Phases 2 and 3 are not externally available.

Fig. 15.9.1 shows relationships of XTAL 1, CLKOUT and Phases 1 , 2 and 3.

Fig. 15.9.1 : Internal timings relative to XTAL1

15.10 System Bus

The external memory is addressed through lines AD0 AD15 that form a 16 bit

multiplexed address/data bus.

These lines share pins with I/O ports 3 and 4.

The external latch (74LS373) is used to demultiplex the bus at the falling edge of

ALE signal.

Inorder to avoid confusion it is advisable to name the demultiplexed address / data

signals. The address signals are called as MA0 through MA15 (memory address) and

the data signals are referred as MD0 through MD15 (memory data).

The 8096s external memory can be addressed as bytes or words. For controlling the

decoding two signals are responsible. They are bus high enable (BHE) and address

data line (AD0).

The BHE signal must be latched as shown in Fig. 15.10.1.

Fig. 15.10.1 : Generation of WRITE HIGH and

WRITE LOW

If BHE is low, the memory connected to the high byte of data bus must be selected.

When MA0 is low the memory connected to the low byte of the data bus must be

selected.

Table 15.10.1 shows accesses to a 16 bit wide memory

Table 15.10.1 : Accesses to 16 bit memory

MA0 BHE Byte accessed

0 0 Both Even and Odd

0 1 Even (Low)

1 0 Odd (High)

If a memory block is being used for reads the signals MA0 and BHE need not be

decoded.

Fig. 15.10.2 shows memory read/write cycles.

Fig. 15.10.2 : Memory read /write cycle timing diagram

If an external memory fetch begins, the address latch enable (ALE) line goes high,

the address is put on AD0 AD15 and BHE is set to the required state.

ALE goes low when the address is taken off. The RD signal goes low.

The READY line can be pulled low inorder to hold the processor in that condition for

some state times. It allows the processor to access slow memories for DMA transfer.

15.11 Interrupt Structure

There are 20 different interrupts sources that can be used with 8096. The

20 interrupt sources vector through 8 locations or interrupt sources as only eight

interrupt sources are available on 8096.

Fig. 15.11.1 shows the vector names and their sources.

Table 15.11.1 lists the interrupt sources and their vector locations.

Table 15.11.1

Source Vector Location Priority

High byte Low byte

Software Trap 2011 H 2010 H Not Applicable

Extint 200F H 200EH 7 (Highest)

Serial Port 200D H 200CH 6

Software Timers 200B H 200AH 5

HSI.0 2009 H 2008 H 4

High speed outputs 2007 H 2006 H 3

HSI Data Available 2005 H 2004 H 2

A/D conversion complete 2003 H 2000 H 1

Timer overflow 2001 H 2000 H 0 (Lowest)

Fig. 15.11.1 : All possible interrupts

An additional TRAP instruction acts as a software interrupt. It is not currently

supported by MCS 96 assembler.

15.11.1 Interrupt Control

Fig. 15.11.1(a) shows the block diagram of interrupt system

Fig. 15.11.1(a) : Interrupt structure block diagram

Priority encoder

It takes care of all the interrupts that are both pending and enabled. Priority

encoder selects the interrupt with highest priority. (7 is highest and 0 is lowest

priority)

Interrupt mask generator

Individual interrupts can be enabled / disabled with the help of interrupt mask

register (0008 H).

If a bit in the mask register is set (i.e. 1) then the interrupt is enabled otherwise the

interrupt is disabled.

Although an interrupt is masked it may become pending. Hence, it is desired to clear

the pending bit before unmasking an interrupt.

The interrupt mask register can be accessed as lower byte of PSW. The PUSHF and

POPF instructions are used to restore the contents of the Interrupt Mask Register.

Global disable

All the interrupts can be enabled and disabled simultaneously with the help of EI

and DI instructions. EI and DI set and clear PSW.9 the interrupt enable bit. The EI

and DI do not affect the contents of interrupt mask register.

Interrupt generator

The interrupt generator forces a call to the location in the indicated vector location

of the highest priority interrupt. This location is the starting location of interrupts service

routine (ISR).

Transition detector

It tests each of the interrupt sources for 0 or 1 transition. If a transition occurs the

respective bit in interrupt pending register (0009H) is set.

Interrupt pending register

It stores the information of the interrupts activated by setting the appropriate bits.

Fig. 15.11.2 shows the bit positions for interrupt sources.

Fig. 15.11.2 : Interrupt pending register

When the interrupt service routine is called the bit is cleared.

The interrupt pending register is a read/write register. Hence, it is possible to

generate software interrupts. It is achieved by setting the bits within the interrupt

pending register or by removing pending interrupts by clearing the corresponding

bit in the register.

While writing to the pending register it is essential to clear interrupts.

If an interrupt has already been acknowledged when the bit is cleared, a 4 state

time partial interrupt cycle will occur. It is because 8096 will have to fetch the next

instruction of the normal instruction flow, instead of continuing with the interrupt

processing.

15.12 University Questions

Dec. 2010

Q. 1 Explain features and architecture of 8096 Microcontroller. (Sections 15.2 and 15.3) (8 Marks)

May 2011

Q. 2 Draw and explain architecture of 8096 microcontroller.

(Sections 15.3, 15.5 and 15.6) (8 Marks)

Dec. 2011

Q. 3 Draw and explain architecture of 8096 microcontroller.

(Sections 15.3, 15.5 and 15.6) (8 Marks)

8096or8097 microcontroller.pdf

Documents

byte register file

high speed inputs

memory controller

high speed outputs

digital converter

high speed io section

data bus transfers data

memory organization