8086 Architecture

8086 Architecture

It is a 16 bit p.

8086 has a 20 bit address bus can access up to 220 memory locations ( 1 MB) .

It can support up to 64K I/O ports.

It provides 14, 16-bit registers.

It has multiplexed address and data bus AD0- AD15 and A16 A19.

CISC Complex Instruction Set Computers

Pipelining Two ways to make CPU process information faster:

Increase the working frequency technology dependent

Change the internal architecture of the CPU

Pipelining is to allow CPU to fetch and execute at the same time

Internal Architecture of 8086 8086 has two blocks BIU and EU.

The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands.

The instruction bytes are transferred to the instruction queue.

EU executes instructions from the instruction system byte queue.

Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance.

BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.

EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.

Internal Registers of 8086

The 8086 has four groups of the user accessible internal registers. They are the instruction pointer, four data registers, four pointer and index register, four segment registers.

The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status register, with 9 of bits implemented for status and control flags.

Registers To store information temporarily

AH

8-bit reg.

AX

16-bit register

AL

8-bit reg.

Category Bits Register Names

General 16 AX, BX, CX, DX

8 AH, AL, BH, BL, CH, CL, DH, DL

Pointer 16 SP (stack pointer), BP (base pointer)

Index 16 SI (source index), DI (destination index)

Segment 16 CS (code segment), DS (data segment)

SS (stack segment), ES (extra segment)

Instruction 16 IP (instruction pointer)

Flag 16 FR (flag register)

Anatomy of a Register

Bits 16-31 Bits 8-15 Bits 0-7

Extended Register

Word Register

High ByteRegister

Low ByteRegister

32 bit Registers 16 bit Registers 8 bit Registers

EAX EBP AX BP AH AL

EBX ESI BX SI BH BL

ECX EDI CX DI CH CL

EDX ESP DX SP DH DLBits 16-31 Bits 8-15 Bits 0-7

General Registers

The 32-bit general-purpose registers EAX, EBX, ECX, EDX, ESI, EDI, EBP, and ESP are provided for holding the following items: operands for logical and arithmetic operations, operands for address calculations, and memory pointers.

Registers can be broken down into 16 and 8 bit registers.

We will use the notation (E)AX to refer to any of AL, AH, AX, or EAX.

Each of the lower two bytes of the EAX, EBX, ECX, and EDX registers can be referenced by the names AH, BH, CH, and DH (high bytes) and AL, BL, CL, and DL (low bytes).

The lower two bytes of the other registers EBP, ESI, EDI, and ESP can not be referenced.

Many instructions assign specific registers to hold operands. For example, string instructions use the contents of the ECX, ESI, and EDI registers as operands.

EAX Accumulator

accumulator for operands and results data

usually used to store the return value of a procedure

EBX Base Register

pointer to data in the DS segment

ECX Counter

counter for string and loop operations

EDX Data Register

I/O pointer

General Registers I

ESI Source Index

source pointer for string operations

typically a pointer to data in the segment pointed to

by the DS register

EDI Destination Index

destination pointer for string operations

typically a pointer to data/destination in the

segment pointed to by the ES register

General Registers II

EBP Base Pointer

pointer to data on the stack

points to the current stack frame of a procedure

ESP Stack Pointer

pointer to the top address of the stack

holds the stack pointer and as a general rule should

not be used for any other purpose

General Registers III

CS Code Segment contains the segment selector for the code segment where

the instructions being executed are stored

DS(ES,FS,GS) Data Segment contains the segment selectors for the data segment

where data is stored

SS Stack Segment contains the segment selector for the stack segment,

where the procedure stack is stored

Segment Registers

Carry Flag CF (bit 0) Set if an arithmetic operation generates a carry or a

borrow out of the most-significant bit of the result; cleared otherwise.

Parity Flag PF (bit 2) Set if the least-significant byte of the result contains an

even number of 1 bits; cleared otherwise.

Adjust Flag AF (bit 4) Set if an arithmetic operation generates a carry or a

borrow out of bit 3 of the result; cleared otherwise.

The EFLAGS Register I

Zero Flag ZF (bit 6) Set if the result is zero; cleared otherwise

Sign Flag SF (bit 7) Set equal to the most-significant bit of the result, which

is the sign bit of a signed integer

Overflow Flag OF (bit 11) Set if the integer result is too large a positive number or

too small a negative number (excluding the sign-bit) to fit in the destination operand; cleared otherwise

The EFLAGS Register II

Instruction Pointer

EIP Instruction Pointer

Contains the offset within the code segment of the next instruction to be executed

Cannot be accessed directly by software

Rule #3:If a value less than FFH is moved into a 16-bit register, the rest of the bits are assumed to be all zeros.

MOV BX, 5 BX =0005

BH = 00, BL = 05

Program Segments

A segment is an area of memory that includes up to 64K bytes

Begins on an address evenly divisible by 16

8085 could address a max. of 64K bytes of physical memory- it has only 16 pins for the address lines (216 = 64K)

8088/86 stayed compatible with 8085- Range of 1MB of memory, it has 20 address pins (220 = 1 MB)

- Can handle 64KB of code, 64KB of data, 64KB of stack

A typical Assembly language program consist of three segments: Code segments

Data segment

Stack segment

Program SegmentsCode segment

The 8086 fetches the instructions (opcodes and operands) from the code segments.

The 8086 address types: Physical address

Offset address

Logical address

Physical address 20-bit address that is actually put on the address pins of 8086

Decoded by the memory interfacing circuitry

A range of 00000H to FFFFFH

It is the actual physical location in RAM or ROM within 1 MB mem. range

Offset address A location within a 64KB segment range

A range of 0000H to FFFFH

Logical address

consist of a segment value and an offset address

Program Segmentsexample

Define the addresses for the 8086 when it fetches the instructions

(opcodes and operands) from the code segments.

Logical address: Consist of a CS (code segment) and an IP (instruction pointer)

format is CS:IP

Offset address IP contains the offset address

Physical address generated by shifting the CS left one hex digit and then adding it to the IP

the resulting 20-bit address is called the physical address

Program Segmentsexample

Suppose we have:CS 2500

IP 95F3

Logical address: Consist of a CS (code segment) and an IP (instruction pointer)

format is CS:IP 2500:95F3H

Offset address IP contains the offset address which is 95F3H

Physical address generated by shifting the CS left one hex digit and then adding it to the IP

25000 + 95F3 = 2E5F3H

Data segment refers to an area of memory set aside for data

Format DS:BX or DI or SI

example:DS:0200 = 25

DS:0201 = 12

DS:0202 = 15

DS:0203 = 1F

DS:0204 = 2B

Program SegmentsData segment

Example:

Add 5 bytes of data: 25H, 12H, 15H, 1FH, 2BH

Program SegmentsData segment

Not using data segment

MOV AL,00H ;clear AL

ADD AL,25H ;add 25H to AL

ADD AL,12H

ADD AL,15H

ADD AL,1FH

ADD AL,2BH

Example:

Add 5 bytes of data: 25H, 12H, 15H, 1FH, 2BH

Program SegmentsData segment

using data segment with a constant offset

Data location in memory:

DS:0200 = 25

DS:0201 = 12

DS:0202 = 15

DS:0203 = 1F

DS:0204 = 2B

Program:

MOV AL,0

ADD AL,[0200]

ADD AL,[0201]

ADD AL,[0202]

ADD AL,[0203]

ADD AL,[0204]