8085 Instruction Addressing Modes Impp

8085 Microprocessor

Pin diagram of 8085

Group of signals

• 8085 is a 40 pin IC, DIP package

• The signals from the pins can be grouped as follows

• Power supply and clock signals

• Address bus

• Data bus

• Control and status signals

• Interrupts and externally initiated signals

• Serial I/O ports

Power supply and Clock frequency signals:

• Vcc + 5 volt power supply

• Vss Ground

• X1, X2 : Crystal or R/C network or LC network connections to set the frequency of internal clock generator.

• The frequency is internally divided by two. Since the basic operating timing frequency is 3 MHz, a 6 MHz crystal is connected externally.

• CLK (output)-Clock Output is used as the system clock for peripheral and devices interfaced with the microprocessor.

Address bus

• A8 - A15 Address bus :

• These are output, tri-state signals used as higher order 8 bits of 16 bit address. These signals are unidirectional meaning that the address is given by 8085 to select a memory or an I/O device.

Multiplexed address/data bus :• AD0 - AD7

• These signals are I/O tristatable signals.

• These pins provides multiplexed address and data bus. They are used as lower address bus of total 16 bit address i.e. A7-

Ao,as well as used as data bus the bus works in conjunction with ALE.

• In earlier part it will output address. Address will remain there for finite time. After that it will vanish. In later part it is used as data bus , i.e. either for reading or writing.

• Multiplexed address/data bus

• The advantage of multiplexed bus is microprocessor requires less number of pins. But disadvantage is, we extra IC (Latch) for demultiplexing. Second disadvantage is, due multiplexing, little bit more time required for read/write operations).

Control and Status signals:

• RD (output 3-state, active low) - Read memory or IO device.

• This indicates that the selected memory location or I/O device is to be read and that the data bus is ready for accepting data from the memory or I/O device.

• WR (output 3-state, active low) - Write memory or IO device.

• This indicates that the data on the data bus is to be written into the selected memory location or I/O device.

Status Signals:

• ALE (output) - Address Latch Enable.

• This signal helps to capture the lower order address presented on the multiplexed address / data bus.

• IO/M (output) - Select memory or an IO device.

• This status signal indicates that the read / write operation relates to whether the memory or I/O device.

• It goes high to indicate an I/O operation.

• It goes low for memory operations.

Status Signals:

• S0,S1 (output) - It is used to know the type of current operation of the microprocessor.

• These are generally not used in small systems but can be used to generate advanced control signals for large systems.

Single Bit Serial I/O ports:

• SID (input) - Serial input data line• This is an active high, serial input port pin, used to accept serial

1 bit data under software control. When a RIM instruction is executed, the SID pin data is loaded in bit D7 of accumulator.

• SOD (output) - Serial output data line• This is an active high, serial output port pin, used to transfer

serial 1 bit data under software control. When a SIM instruction is executed the SOD pin is set or reset depending on D7 and

D6 bits of accumulator.

• These signals are used for serial communication.

DMA: Direct Memory Access Signals

• DMA is used to transfer data from memory to peripheral or peripheral to memory without the interference of the microprocessor.

• HOLD (input) - HOLD is an active high signals. Its means other device is requesting for DMA operations.

• HLDA (output) - This signal acknowledges the HOLD request.It is active high signal.

• It’s inactive by the microprocessor after the I/O device has completed the DMA operation.

Tri state devices:• 3 output states are high & low states & additionally a high impedance state.

• When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is 0, Q is 1, otherwise Q is 0). However, when E is low the gate is disabled and the output Q enters into a high impedance state.

• For both high and low states, the output Q draws a current from the input of the OR gate.

• When E is low, Q enters a high impedance state; high impedance means it is electrically isolated from the OR gate's input, though it is physically connected. Therefore, it does not draw any current from the OR gate's input

• HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the microprocessor acknowledges the request by sending out HLDA signal and leaves out the control of the buses. After the HLDA signal the DMA controller starts the direct transfer of data.

DM

A

Con

troller

• READY (input)

• This is an active high input control signal.

• It is used by microprocessor to detect whether a peripheral has completed the data transfer or not.

• If ready pin is HIGH, the microprocessor will complete the operation and proceed for next operation.

• But if ready pin is LOW (i.e. peripheral has not yet completed the operation), microprocessor will WAIT until it goes HIGH.

• The main function of this pin is to synchronize slower

peripheral to the faster microprocessor.

Interrupts and Externally initiated operations:

• They are the signals initiated by an external device to request the microprocessor to do a particular task or work.

• TRAP (output) - This is an active high level, edge triggered, non maskable, highest priority interrupt. When TRAP line is active microprocessor performs internal restart automatically at address 0024. The net effect of TRAP is, it transfers program control at address 0024.

• RST 7.5, RST 6.5,RSR 5.5 Restart interrupts (output) -These are active high, edge (RST 7.5) or level (RST 6.5 and RST 5.5) triggered maskable interrupt.

• The priorities of these are TRAP and RST 7.5, RST 6.5, RST 5.5.

• When RST 7.5, RST 6.5, RST 5.5 is active RST 5.5 microprocessor performs internal restart automatically at address 003C, 0034, 002C respectively.

• The net effect is, it transfers program control at address, specified above.

• There are five hardware interrupts called,

• INTR Interrupt request (output) -

INTA Interrupt Acknowledge (input) - INTR is an active high, level triggered general purpose and interrupt. When INTR is active, microprocessor generate an interrupt acknowledge signal INTA.

Multiplexed address/data bus :• AD0 - AD7 Multiplexed address/data bus : These signals are I/O

tristatable signals. These pins provides multiplexed address and data bus. They are used as lower address bus of

• total 16 bit address i.e. A7-Ao,as well as used as data bus the bus

works in conjunction with ALE. In earlier part it will output address. Address will remain there for finite time. After that it will vanish. In later part it is used as data bus , i.e. either for reading or writing.

•

• Fig. 1.2: Multiplexed address/data bus

• The advantage of multiplexed bus is microprocessor requires less number of pins. But disadvantage is, we extra IC (Latch) for demultiplexing. Second disadvantage is, due multiplexing, little bit more time required for read/write operations).

EU & BIU• The 8086 CPU logic has been partitioned into

two functional units namely Bus Interface Unit (BIU) and Execution Unit (EU)

• The major reason for this separation is to increase the processing speed of the processor

• The BIU has to interact with memory and input and output devices in fetching the instructions and data required by the EU

• EU is responsible for executing the instructions of the programs and to carry out the required processing

EU & BIU

BUS INTERFACE UNIT (BU)The BIU performs all bus operations for EU .

Fetching instructions

Responsible for executing all external bus cycles.

Read operands and write result.

EXECUTION UNIT (EU)

Execution unit contains the complete infrastructure required to execute an instruction

Architecture Diagram

Execution Unit

• The Execution Unit (EU) has

– Control unit

– Instruction decoder

– Arithmetic and Logical Unit (ALU)

– General registers

– Flag register

– Pointers

– Index registers

Execution Unit

• Control unit is responsible for the co-ordination of all other units of the processor

• ALU performs various arithmetic and logical operations over the data

• The instruction decoder translates the instructions fetched from the memory into a series of actions that are carried out by the EU

Execution Unit - Registers

• General registers are used for temporary storage and manipulation of data and instructions

• Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX

• Accumulator can be used for I/O operations and string manipulation

Execution Unit - Registers• Base register consists of two 8-bit registers BL

and BH, which can be combined together and used as a 16-bit register BX

• BX register usually contains a data pointer used for based, based indexed or register indirect addressing. Similar to 8085 H-L register.

• Count register consists of two 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX

• Count register can be used as a counter in string manipulation and shift/rotate instructions


• Data register consists of two 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX

• Data register can be used to hold 16 bit result in 16 in 16x16 multiplication.


Pointer Registers

Stack pointer and BP are used to access data in the stack segment.

SP is used as an offset from the current SS during execution of instructions that involve the stack segment in external memory.

BP is used in based addressing mode.


Index Register

Source index register (SI) and Destination Index Registers are used in indexed addressing.


Execution Unit - Flags

Execution Unit - Flags• Overflow Flag (OF) - set if the size of the exceeds the

capacity of the destination location.

• Direction Flag (DF) – It is used with string operations. When set , it causing string instructions to auto – decrement or to process strings from right to left.

• Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts . When IF = 0 , all maskable interrupt are disable.

• Single-step Flag (Trap F) – put 8086 in the single step mode.

Execution Unit - Flags• Sign Flag (SF) - set if the most significant bit of the

result is one.

• Zero Flag (ZF) - set if the result is zero.

• Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL register.

• Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result is even.

• Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit during last result calculation

Execution Unit - Flags

Execution Unit - Pointers• Stack Pointer (SP) is a 16-bit register pointing to

program stack

• Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing.

• Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data addresses in string manipulation instructions.

• Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data addresses in string manipulation instructions.

Execution Unit - Pointers

Bus Interface Unit

• The BIU has

– Instruction stream byte queue

– A set of segment registers

– Instruction pointer

BIU – Instruction Byte Queue

• 8086 instructions vary from 1 to 6 bytes

• Therefore fetch and execution are taking place concurrently in order to improve the performance of the microprocessor

• The BIU feeds the instruction stream to the execution unit through a 6 byte prefetch queue

BIU – Instruction Byte Queue• Execution and decoding of certain instructions do not

require the use of buses

• While such instructions are executed, the BIU fetches up to six instruction bytes for the following instructions (the subsequent instructions)

• The BIU store these prefetched bytes in a first-in-first out register by name instruction byte queue

• When the EU is ready for its next instruction, it simply reads the instruction byte(s) for the instruction from the queue in BIU

Segment: Offset Notation

• The total addressable memory size is 1MB

• Most of the processor instructions use 16-bit pointers the processor can effectively address only 64 KB of memory

• To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory

Segment: Offset Notation• A simple scheme would be to order the bytes in a serial

fashion and number them from 0 (or 1) to the end of memory

• The scheme used in the 8086 is called segmentation

• Every address has two parts, a SEGMENT and an OFFSET (Segmnet:Offset )

• The segment indicates the starting of a 64 kilobyte portion of memory, in multiples of 16

• The offset indicates the position within the 64k portion

• Absolute address = (segment * 16) + offset

Segment Registers

• The memory of 8086 is divided into 4 segments namely

– Code segment (program memory)

– Data segment (data memory)

– Stack memory (stack segment)

– Extra memory (extra segment)

Different Areas in Memory• Program memory – Program can be located anywhere in

memory

• Data memory – The processor can access data in any one out of 4 available segments

• Stack memory – A stack is a section of the memory set aside to store addresses and data while a subprogram executes

• Extra segment – This segment is also similar to data memory where additional data may be stored and maintained

Segment Registers• Code Segment (CS) register is a 16-bit register containing

address of 64 KB segment with processor instructions

• The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register

• Stack Segment (SS) register is a 16-bit register containing address of 64KB segment with program stack

• By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment

Segment Registers• Data Segment (DS) register is a 16-bit register containing

address of 64KB segment with program data

• By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment

• Extra Segment (ES) register is a 16-bit register containing address of 64KB segment, usually with program data

• By default, the processor assumes that the DI register references the ES segment in string manipulation instructions

Segment Registers

If a location 109F0 of Code Segment is to be addressed to fetchAn instruction, the physical address will be calculated as followsCSR = 010AIP = F950Effective Address = 109F0

Minimum-Mode and Maximum-Mode System

Minimum-Mode and Maximum-Mode System (cont.)

Signals common to both minimum and maximum mode


Unique minimum-mode signals


Unique maximum-mode signals

PIN DESCRIPTION -8086Pin 1, 20

Ground

Pin 40

Vcc

Pin 19

CLK

Pin 17

INTR

Pin 18

NMI

AD15 –AD0 [ Pin 2- 16 &39]

The signal have dual function as in case of the 8085. They act as bus during the first part of machine cycle and as data bus in the later part.

A19/S6 –A16/S3 [Pin 35- 38]

Contains address information in the first part and status bits in the later part. The status bits, when decoded, indicates the type of operations (eg. Memory access) being performed and the segment register being used.

S4 S3 SEGMENT REGISTER

0 0 ES

0 1 SS

1 0 CS

1 1 DS

S5 = IFS6 = 0 (ALWAYS)

BHE/S7 [pin 34]

MN/MX [pin 33]

High – Minimum Mode Operation

Low – Maximum Mode Operation

RD [pin 32]

Read or receive data from M or I/O device

TEST [pin 23]

Relate to wait instruction. The instruction puts the 8086 in idle state which ends only when the TEST input goes low

READY [Pin 22]

Ready is a signal provided by the memory or I/O devices to the microprocesssor.When READY = High, the microprocessor proceeds to process the data in usual manner. When READY = Low, the micropressor goes into wait state and waits for READY to become High.

RESET [Pin 21]

Resets the Processor

……….PIN DESCRIPTION

DEN

Data bus Enable. This signal, when low indicates that the microprocessor address/data bus is to be used as data bus.

HOLD

HLDA

Minimum Mode pin Functions Pin 24 -31

INTA - Pin 24

ALE - Pin 25

Address Latch Enable. Since data and address are multiplexed on a single bus. ALE is output high to identify a valid address.

DEN -Pin 26

Data Bus Enable. This signal, when low indicates that the microprocessor address/data bus is to be used as data bus.

DT/R - Pin 27

Data transmission/ Receive

M/ IO – Pin 28

WR – Pin 29

HOLD – Pin 30

HLDA - Pin 31

Addressing Modes• Implied Addressing – The data value/data address is

implicitly associated with the instruction

• Register Addressing – The data is specified by referring the register or the register pair in which the data is present

• Immediate Addressing – The data itself is provided in the instruction

• Direct Addressing – The instruction operand specifies the memory address where data is located

Addressing Modes• Register indirect addressing – The instruction specifies a

register containing an address, where data is located

• Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the resulting value is a pointer to location where data resides

• Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides

Addressing Modes

• Based Indexed - the contents of a base register (BX or BP) is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides

• Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer to location where data resides

Data Transfer Instructions

Data Transfer Instructions

Arithmetic Instructions

Arithmetic Instructions

Number Representation

Logical Instructions

String Instructions

Program Transfer Instructions

Program Transfer Instructions

Processor Control Instructions

Assembler Directives• Assembler directives give instruction to the assembler

where as other instructions discussed in the above section give instruction to the 8086 microprocessor

• Assembler directives are specific for a particular assembler

• However all the popular assemblers like the Intel 8086 macro assembler, the turbo assembler and the IBM macro assembler use common assembler directives

Important Directives• The ASSUME directive tell the assembler the name of the logical

segment it should use for a specified segment

• The DB directive is used to declare a byte-type variable or to set aside one or more storage locations of type byte in memory (Define Byte)

• The DD directive is used to declare a variable of type doubleword or to reserve memory locations which can be accessed as type doubleword (Define Doubleword)

• The DQ directive is used to tell the assembler to declare a variable 4 words in length or to reverse 4 words of storage in memory (Define Quadword)

Important Directives

• The ENDS directive is used with the name of a segment to indicate the end of that logical segment

• The EQU is used to give a name to some value or symbol

Assembly Language Program• Writing assembly language programs for 8086 is slightly

different from that of writing assembly language programs for 8085

• In addition to the instructions that are meant for solving the problem, some additional instructions are required to complete the programs

• The purpose of these additional programs is to initialize various parts of the system, such as segment registers, flags and programmable port devices

• Some of the instructions are to handle the stack of the 8086 based system

Assembly Language Program• Another purpose of these additional instructions is to

handle the programmable peripheral devices such as ports, timers and controllers

• The programmable peripheral interfaces should be assigned suitable control words to make them to function in the way as we expect

• The best way to approach the initialization task is to make a checklist of all the registers, programmable devices and flags in the system we are working on

Assembly Language Program

• An 8086 assembly language program has five columns namely

– Address

– Data or code

– Labels

– Mmnemonics

– Operands

– Comments


• The address column is used for the address or the offset of a code byte or a data byte

• The actual code bytes or data bytes are put in the data or code column

• A label is a name which represents an address referred to in a jump or call instruction

• Labels are put in the labels column


• The operands column contains the registers, memory locations or data acted upon by the instructions

• A comments column gives space to describe the function of the instruction for future reference

8085 Instruction Addressing Modes Impp

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