8 - 1 Texas Instruments Incorporated European Customer Training Centre University of Applied Sciences Zwickau (FH) Module 8 : Serial Communication Interface.

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Texas Instruments Incorporated

European Customer Training Centre

University of Applied Sciences Zwickau (FH)

Module 8 : Serial Communication Interface C28xModule 8 : Serial Communication Interface C28x

32-Bit-Digital Signal ControllerTMS320F2812

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SPI SummarySPI Summary

Provides Provides synchronoussynchronous serial communications serial communications Two wire transmit or receive (Two wire transmit or receive (half duplexhalf duplex)) Three wire transmit and receive (Three wire transmit and receive (full full duplex)duplex)

Software configurable as master or slaveSoftware configurable as master or slave C28x provides clock signal in master modeC28x provides clock signal in master mode

Data length programmable from 1-16 bitsData length programmable from 1-16 bits 125 different programmable baud rates125 different programmable baud rates

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SPI Example 1: DAC TLV 5617SPI Example 1: DAC TLV 5617

Texas Instruments Digital to Analogue Texas Instruments Digital to Analogue Converter (DAC) TLV 5617AConverter (DAC) TLV 5617A 10 10 MBPSMBPS SPI Data Communication SPI Data Communication Dual Channel Analogue Output ( Out A + B) Dual Channel Analogue Output ( Out A + B) 10 Bit resolution10 Bit resolution /CS is connected to C28x GPIO – D0 at the /CS is connected to C28x GPIO – D0 at the

Zwickau Adapter BoardZwickau Adapter Board REF – Voltage defines Analogue Range / 2 REF – Voltage defines Analogue Range / 2 SOIC-8SOIC-8 Operating Voltage : 0 to 3.3VOperating Voltage : 0 to 3.3V

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SPI Example : DAC TLV 5617SPI Example : DAC TLV 5617

Timing Diagram: Timing Diagram:

© Texas Instruments SLAS234F – JULY 1999 – REVISED JULY 2002 ; page 6

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SPI Example : DAC TLV 5617SPI Example : DAC TLV 5617

Serial Data Format:Serial Data Format:

0

DATA0

SPD DATA6DATA9

DATA3

1234567

89101112131415

00DATA2 DATA1

DATA7

DATA4

DATA8

DATA5

R0PWRR1

SPDSpeed Control

0 = slow mode1 = fast mode

PWRPower Control

0 = normal operation1 = power down

R1 , R0 Register Select00: Write to DACB and Buffer01: Write to Buffer10: Write to DACA and update

DACB with Buffer 11: reserved

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Lab 7: DAC TLV 5617Lab 7: DAC TLV 5617

Objective:Objective: Generate a rising saw-tooth (0V…3.3V) at Generate a rising saw-tooth (0V…3.3V) at

channel OUTA and a falling saw-tooth (3.3V…channel OUTA and a falling saw-tooth (3.3V…0V)0V) at channel OUTBat channel OUTB

GPIO – D0 is DAC’s chip select (/CS) at the GPIO – D0 is DAC’s chip select (/CS) at the Zwickau Adapter BoardZwickau Adapter Board

To measure the DAC outputs:To measure the DAC outputs: Use JP7 for OUTA Use JP7 for OUTA Use JP8 for OUTB ( Zwickau Adapter Board)Use JP8 for OUTB ( Zwickau Adapter Board)

REF = 3.3VREF = 3.3V Feedback the voltages into the C28x ADC:Feedback the voltages into the C28x ADC:

JP7 closed: OUTA JP7 closed: OUTA ADCINA1 ADCINA1 JP8 closed: OUTB JP8 closed: OUTB ADCINB1 ADCINB1

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SPI Example 2: SPI Example 2: EEPROMEEPROM M95080 M95080

ST Microelectronics EEPROM M95080ST Microelectronics EEPROM M95080 10 MBPS SPI Data Communication 10 MBPS SPI Data Communication CapacityCapacity: 1024 x 8 Bit : 1024 x 8 Bit /CS is connected to C28x GPIO – D5 (Zwickau /CS is connected to C28x GPIO – D5 (Zwickau

Adapter Board)Adapter Board) 6 Instructions:6 Instructions:

Write Enable, Write DisableWrite Enable, Write Disable Read Status Register, Write Status RegisterRead Status Register, Write Status Register Read Data, Write Data Read Data, Write Data

SOIC-8SOIC-8 Single Power Supply : 3.3VSingle Power Supply : 3.3V

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SCI Pin Connections SCI Pin Connections

Transmitter-databuffer register

Transmittershift register

SCI Device #1

SCIRXD

SCITXD SCITXD

SCIRXD

SCI Device #2

8

Receiver-databuffer register

Receivershift register

8

Transmitter-databuffer register

Transmittershift register

8

Receiver-databuffer register

Receivershift register

8

(Full Duplex Shown)

RX FIFO_0

RX FIFO_15

RX FIFO_0

RX FIFO_15

TX FIFO_0

TX FIFO_15

TX FIFO_0

TX FIFO_15

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SCI-A Programmable Data FormatSCI-A Programmable Data Format

Start

LSB

2 34 5 7 MSB

Parity

Stop 1

Addr/Data6

This bit present only in Address-bit mode

Stop 2

NRZ (nonreturn to zero) format

Start Bit LSB of Data

MajorityVote

Falling Edge Detected

SCIRXD

SCICLK(Internal)

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2

Note: 8 SCICLK periods per data bit

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Multiprocessor Wake-Up ModesMultiprocessor Wake-Up Modes

Allows numerous processors to be hooked up to Allows numerous processors to be hooked up to the bus, but transmission occurs between only the bus, but transmission occurs between only two of themtwo of them

Idle-line or Address-bit modesIdle-line or Address-bit modes Sequence of OperationSequence of Operation

1. Potential receivers set SLEEP = 1, which disables RXINT except 1. Potential receivers set SLEEP = 1, which disables RXINT except when an address frame is receivedwhen an address frame is received

2. All transmissions begin with an address frame2. All transmissions begin with an address frame

3. Incoming address frame temporarily wakes up all SCIs on bus3. Incoming address frame temporarily wakes up all SCIs on bus

4. CPUs compare incoming SCI address to their SCI address4. CPUs compare incoming SCI address to their SCI address

5. Process following data frames only if address matches5. Process following data frames only if address matches

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Address-Bit Wake-Up ModeAddress-Bit Wake-Up Mode

All frames contain an extra address bitAll frames contain an extra address bit Receiver wakes up when address bit detectedReceiver wakes up when address bit detected Automatic setting of Addr/Data bit in frame by setting Automatic setting of Addr/Data bit in frame by setting

TXWAKE = 1 prior to writing address to SCITXBUFTXWAKE = 1 prior to writing address to SCITXBUF

Last Data STST DataSCIRXD/SCITXD

Block of Frames

SP SP Last DataST Addr SP

Idle Periodlength of nosignificance

First frame withinblock is Address.

ADDR/DATAbit set to 1

1st data frame

0 1 0 0 SPST Addr 1SP

no additionalidle bits neededbeyond stop bits

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SCI SummarySCI Summary

Asynchronous communications formatAsynchronous communications format 65,000+ different programmable baud rates65,000+ different programmable baud rates Two wake-up multiprocessor modesTwo wake-up multiprocessor modes

Idle-line wake-up & Address-bit wake-upIdle-line wake-up & Address-bit wake-up

Programmable data word formatProgrammable data word format 1 to 8 bit data word length1 to 8 bit data word length 1 or 2 stop bits1 or 2 stop bits even/odd/no parityeven/odd/no parity

Error Detection FlagsError Detection Flags Parity error; Framing error; Overrun error; Break detectionParity error; Framing error; Overrun error; Break detection

FIFO-buffered transmit and receiveFIFO-buffered transmit and receive Individual interrupts for transmit and receiveIndividual interrupts for transmit and receive

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SCI-A RegistersSCI-A RegistersAddress Register Name

0x007050 SCICCR SCI-A commun. control register0x007051 SCICTL1 SCI-A control register 10x007052 SCIHBAUD SCI-A baud register, high byte0x007053 SCILBAUD SCI-A baud register, low byte0x007054 SCICTL2 SCI-A control register 2 register0x007055 SCIRXST SCI-A receive status register0x007056 SCIRXEMU SCI-A receive emulation data buffer0x007057 SCIRXBUF SCI-A receive data buffer register0x007059 SCITXBUF SCI-A transmit data buffer register0x00705A SCIFFTX SCI-A FIFO transmit register0x00705B SCIFFRX SCI-A FIFO receive register0x00705C SCIFFCT SCI-A FIFO control register0x00705F SCIPRI SCI-A priority control register

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SCI-A Communication Control RegisterSCI-A Communication Control Register

ADDR/IDLEMODE

STOPBITS

EVEN/ODDPARITY

PARITYENABLE

LOOP BACKENABLE

SCICHAR2

SCICHAR1

SCICHAR0

Communications Control Register (SCICCR) – 0x007050

0 = 1 Stop bit1 = 2 Stop bits

0 = Odd1 = Even

0 = Disabled1 = Enabled

0 = Disabled1 = Enabled

0 = Idle-line mode1 = Addr-bit mode

7 6 5 4 3 2 1 0

# of data bits = (binary + 1)e.g. 110b gives 7 data bits

[SCI-B Communications Control Register (SCICCR) – 0x007750]

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SCI-A Control Register 1SCI-A Control Register 1

TXWAKEreserved RX ERRINT ENA

SWRESET

reserved SLEEP TXENA RXENA

Control Register 1 (SCICTL1) – 0x007051

0 = Receive Error Interrupt disabled1 = Receive Error Interrupt enabled

Write 0 = Reset SCIWrite 1 = release from Reset

Transmitter wakeup method select1 = wakeup mode depends on SCICCR.30 = no wakeup mode

7 6 5 4 3 2 1 0

[SCI-B Control Register 1 (SCICTL1) – 0x007751]

0 = sleep mode disabled1 = sleep mode enabled

0 = transmitter disabled1 = transmitter enabled

0 = receiver disabled1 = receiver enabled

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SCI-A Baud RateSCI-A Baud Rate

BAUD15(MSB)

BAUD14

Baud-Select MSbyte Register (SCIHBAUD) – 0x0070527 6 5 4 3 2 1 0

BAUD13 BAUD12 BAUD11 BAUD10 BAUD9 BAUD8

BAUD6

Baud-Select LSbyte Register (SCILBAUD) – 0x0070537 6 5 4 3 2 1 0

BAUD5 BAUD4 BAUD3 BAUD2 BAUD1BAUD7 BAUD0(LSB)

SCI baud rate =

LSPCLK

(BRR + 1) x 8

LSPCLK

16

, BRR = 1 to 65535

, BRR = 0

[SCI-B Baud-Select MSbyte Register (SCIHBAUD) – 0x007752][SCI-B Baud-Select LSbyte Register (SCILBAUD) – 0x007753]

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TXRDYTX

EMPTYRX/BK

INT ENA

SCI-A Control Register 2SCI-A Control Register 2SCICTL2 @ 0x007054SCICTL2 @ 0x007054

0TX

INT ENA

17 6 5 - 2

reserved

SCI TX READY 0 = SCITXBUF is full 1 = SCITXBUF is empty

SCI TX EMPTY0 = TXBUF or shift register are loaded with data1 = Transmit buffer and shift register both empty

reserved

15 - 8

[SCI-B Control Register 2(SCICTL2) – 0x007754]

SCI TX INT ENA 0 = Disable TXRDY interrupt 1 = Enable TXRDY interrupt

SCI RX/BK INT ENA 0 = Disable RXRDY/BRKDT interrupt 1 = Enable RXRDY/BRKDT interrupt

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SCI-A Receiver Status RegisterSCI-A Receiver Status RegisterSCIRXST @ 0x007055SCIRXST @ 0x007055

[SCI-B Receiver Status Register (SCIRXST) – 0x007755]

OERX

ERRORRXRDY BRKDT FE PE RXWAKE reserved

0 = No error flags set1 = Error flag(s) set

0 = no new character in SCIRXBUF1 = new character in SCIRXBUF

1 = Break condition occurred0 = no break condition

7 6 5 4 3 2 1 0

1 = Framing Error detected

1 = Overrun Error detected

1 = Parity Error detected

1 = Receiver wakeup condition detected

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SCI-A FIFO Transmit RegisterSCI-A FIFO Transmit RegisterSCIFFTX @ 0x00705ASCIFFTX @ 0x00705A

0

TXFFIL2

SCIFFENA TXFFST0TXFFST3

TXFFIENA

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89101112131415

TXFFIL0TXFFIL1TXFFIL4 TXFFIL3

TXFFST1

TXFFINTCLR

TXFFST2

TXFFINT

TXFFST4TXFIFORESET

SCIRST

TX FIFO Status (read-only)00000 TX FIFO empty00001 TX FIFO has 1 word00010 TX FIFO has 2 words00011 TX FIFO has 3 words

10000 TX FIFO has 16 words

... ... ...

TX FIFO Interrupt LevelInterrupt when TXFFST4-0and TXFFIL4-0 match

SCI FIFOEnhancements

0 = disable1 = enable

TX FIFO Reset0 = reset (pointer to 0)1 = enable operation

TX FIFOInterrupt

(on match)Enable

0 = disable1 = enable

TX FIFOInterrupt

Flag (read-only)0 = not occurred1 = occurred

TX FIFOInterruptFlag Clear0 = no effect1 = clear

SCI Reset0 = reset1 = enable operation

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SCI-A FIFO Receive RegisterSCI-A FIFO Receive RegisterSCIFFRX @ 0x00705BSCIFFRX @ 0x00705B

0

RXFFIL2

RXFF-OVF CLR

RXFFST0RXFFST3

RXFFIEN

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89101112131415

RXFFIL0RXFFIL1RXFFIL4 RXFFIL3

RXFFST1

RXFFINTCLR

RXFFST2

RXFFINT

RXFFST4RXFIFORESET

RXFF-OVF

RX FIFO Status (read-only)00000 RX FIFO empty00001 RX FIFO has 1 word00010 RX FIFO has 2 words00011 RX FIFO has 3 words

10000 RX FIFO has 16 words

... ... ...

RX FIFO Interrupt LevelInterrupt when RXFFST4-0and RXFFIL4-0 match

RX FIFO Reset0 = reset (pointer to 0)1 = enable operation

RX FIFOInterrupt

(on match)Enable

0 = disable1 = enable

RX FIFOInterrupt

Flag (read-only)0 = not occurred1 = occurred

RX FIFOInterruptFlag Clear0 = no effect1 = clear

RX FIFOOverflow

Flag (read-only)0 = no overflow1 = overflow

RX FIFOOverflowFlag Clear0 = no effect1 = clear

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SCI-A FIFO Control RegisterSCI-A FIFO Control RegisterSCIFFCT @ 0x00705CSCIFFCT @ 0x00705C

0

ABDCLR

1234567

89101112131415

CDCABD

FFTXDLYTime delay between every transfer from FIFOto transmit shift register in number of SCI baud clock cycles( 0 to 255 )

CDC calibrate ‘A’0 = disabled auto-baud alignment1 = enables auto-baud alignment

Auto Bauddetection

Flag (read-only)0 = not complete1 = complete

Auto BauddetectionFlag Clear0 = no effect1 = clear

reserved

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SCI Example 1: transmit a text - stringSCI Example 1: transmit a text - string

Lab 8: Basic SCI Communication

  Send a string from DSP to a PC’s COM-port. Connect the RS232 - Connector of the Zwickau adapter board

with a standard DB9 - cable ( 1:1 ) to a serial port of the PC (COM1or COM2).

DSP shall transmit a string from the DSP to the PC periodically. No SCI interrupt services in this lab After transmission of the first character we just poll the

transmission ready flag (TXEMPTY) before loading the next character into the transmit buffer - and wait again.

The Windows-Hyper Terminal program is used as the counterpart from the PC’s-side and must be initialized properly for correct function(Baud rate, Parity, no protocol).