70-90GHz Self-Tuned Polyphase Filter for Wideband I/Q LO Generation in a 55nm BiCMOS Transmitter Farshad Piri 1 , E. Rahimi 2 , M. Bassi 3 , F. Svelto 2 , A. Mazzanti 2 [email protected]September 23-26, 2019 ESSCIRC/ DE , Cracow, Poland ESS RC 2019 1 Infineon Technologies AG, Linz, Austria 2 University of Pavia, Pavia, Italy 3 Infineon Technologies AG, Villach, Austria 1 of 19
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70-90GHz Self-Tuned Polyphase Filter for Wideband I/Q LO Generation in a 55nm BiCMOS Transmitter
Farshad Piri1, E. Rahimi2, M. Bassi3, F. Svelto2, A. Mazzanti2
Absence of IF mmWave stages allows wide-band Power and area saving Key issue is quadrature LO generation directly at E-band PA challenging in silicon to deliver high Pout with good efficiency
ESSCIRC/ DE , Cracow, PolandESS RC 2019
gm
G
G
S
PA
LO I
LO Q
PA
BB I
BB Q
gm
70-90 GHz LO
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Active VCO + divider Quadrature VCOs
Passive Quadrature Couplers (Lange, branch-line,
Hybrid) All pass networks (LC and RC Polyphase
Filters)
E-band Quadrature LO Generation
Quadrature hybrids disregarded because of large footprint, limited accuracy (φe≃2-3°) and limited bandwidth
Polyphase filters (PPF) are very compact and can reach 40dB Image Rejection Ratio (φe <1°) but needs several stages (>3) considering PVT variations
ESSCIRC/ DE , Cracow, PolandESS RC 2019 6 of 19Farshad Piri
E-band Quadrature LO Generation
Quadrature hybrids disregarded because of large footprint, limited accuracy (φe≃2-3°) and limited bandwidth
Polyphase filters (PPF) are very compact and can reach 40dB Image Rejection Ratio (φe <1°) but needs several stages (>3) considering PVT variations
ESSCIRC/ DE , Cracow, PolandESS RC 2019
0
10
20
30
40
50
60
70
30 40 50 60 70 80 90 100 110 120
Imag
e Re
ject
ion
Ratio
[dB]
Freq. [GHz]
slow, 110° typ, 27° fast, -40°
Desired BW
3-Stage PPF
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Inp
Inn
Ip
Qp
+
+
-
-
RC
Type-A PPF (∆Amp =0)
E-band Quadrature LO Generation
1-stage (low-loss) MOSFET-C Polyphase filter (C=28fF) Phase detector measures quadrature deviation, and error Amp derives the
PPF(Vtune) to maintain minimum phase error Calibration loop needs 16mW only Transformer-based interface network for flat amplitude response, Wide BW.
ESSCIRC/ DE , Cracow, PolandESS RC 2019
Vtune
buff
buff
Amp
to Mixer
LO_I
LO_Q
to Mixer
1-stage tunable PPF
70-90 GHz
I
Q
Phase Detector
Vtune1 Vtune2 Vtune3
IRR[
dB]
Image Rejection Ratio
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Vtune
buff
buff
Amp
to Mixer
LO_I
LO_Q
to Mixer
1-stage tunable PPF
70-90 GHz
I
Q
Phase Detector
Loop Gain
ESSCIRC/ DE , Cracow, PolandESS RC 2019
Loop Gain of >30dB required to reduce 20° Open loop phase error to <1°(IRR>40dB)
GLoop= KPD.AV.KPPF
Phase detector Gain (KPD) has to be maximized to reduce offset/mismatch effect KPPF is about 100 [°/V] KPD.AV designed to achieve >0.3 [V/°]
KPD
AV
KPPF
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Quadrature Phase Detector
ESSCIRC/ DE , Cracow, PolandESS RC 2019
Phase detector realized with – Gilbert cells driven by exchanged LO signals Matched loading for LO_I and LO_Q Cancels the effect of the phase skew (∆φ) introduced by each cell at the output
M1 M2
LO_I LO_Q
Gm gm
AB
gm
Vout
LO_Q LO_I
Vcc
Ia+ Ia-Ib+ Ib-IP IN
IDC
Q1a Q1b
Q2a,b
QP QN
Ia+ Ia-
QPQ2c,d
𝐋𝐋𝐋𝐋_𝐈𝐈:𝐀𝐀𝐀𝐀𝐀𝐀𝐀𝐀(𝛚𝛚𝐋𝐋𝐋𝐋𝐭𝐭)
𝐋𝐋𝐋𝐋_𝐐𝐐:𝐀𝐀𝐀𝐀𝐀𝐀𝐀𝐀(𝛚𝛚𝐋𝐋𝐋𝐋𝐭𝐭 + 𝛟𝛟𝐞𝐞)
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Phase Skew in each Gilbert Cell
ESSCIRC/ DE , Cracow, PolandESS RC 2019
Mismatch between rbcπ of Q1-Q2 and Caps Cxy responsible for large ∆φ (≈78°) (Ia+−Ia−) ∝ sin(ϕe − ∆𝛟𝛟) (Ib+−Ib−) ∝ sin(ϕe + ∆𝛟𝛟)
Output of each cell is not zero even if LO_I and LO_Q are in quadrature (φe=0)
IPIN
IDC
Q1a Q1b
Q2a,b
QP QN
Ia+ Ia-
QPQ2c,d
rb1
cπ1
rb2
cπ2cx cy
M1 M2
LO_I LO_Q
Gm gm
AB
gm
Vout
LO_Q LO_I
Vcc
Ia+ Ia-Ib+ Ib-
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𝐋𝐋𝐋𝐋_𝐈𝐈:𝐀𝐀𝐀𝐀𝐀𝐀𝐀𝐀(𝛚𝛚𝐋𝐋𝐋𝐋𝐭𝐭)
𝐋𝐋𝐋𝐋_𝐐𝐐:𝐀𝐀𝐀𝐀𝐀𝐀𝐀𝐀(𝛚𝛚𝐋𝐋𝐋𝐋𝐭𝐭 + 𝛟𝛟𝐞𝐞)
Farshad Piri
Phase Skew in each Gilbert Cell
ESSCIRC/ DE , Cracow, PolandESS RC 2019
By summing the output currents with M1-M2, the detector output voltage is: 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 ∝ (Ia+ − Ia−) + (Ib+−Ib−) ∝ cos(∆𝛟𝛟)sin(ϕe)
∆φ does not introduce systematic phase error, but reduces severely the detector gain (cos(78 °)=0.2)
IPIN
IDC
Q1a Q1b
Q2a,b
QP QN
Ia+ Ia-
QPQ2c,d
rb1
cπ1
rb2
cπ2cx cy
M1 M2
LO_I LO_Q
Gm gm
AB
gm
Vout
LO_Q LO_I
Vcc
Ia+ Ia-Ib+ Ib-
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Δϕ=k if k<1
π2 +k− k2−1− arcsin k−1 if k>1
k=π CX,Y Aeff fLO
IDC
𝐋𝐋𝐋𝐋_𝐈𝐈: 𝐀𝐀𝐀𝐀𝐀𝐀𝐀𝐀(𝛚𝛚𝐋𝐋𝐋𝐋𝐭𝐭)
𝐋𝐋𝐋𝐋_𝐐𝐐:𝐀𝐀𝐀𝐀𝐀𝐀𝐀𝐀(𝛚𝛚𝐋𝐋𝐋𝐋𝐭𝐭 + 𝛟𝛟𝐞𝐞)
Farshad Piri
Final phase detector
ESSCIRC/ DE , Cracow, PolandESS RC 2019
Explicit resistors (R) added in series to the switching transistors, sized to cancel the intrinsic mixers skew (∆φ≈0°).
Detector gain restored, key to limit the effect of random offset (Vos) From Monte-Carlo simulations, w./.o. R, φe_Vos=3.5°, w. R, φe_Vos=0.85°
M1 M2
LO_I LO_Q
Gm gm
AB
gm
Vout
LO_Q LO_I
Vcc
RR
vos
8µA/°
30µA/°
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PA Core - Single-Path
ESSCIRC/ DE , Cracow, PolandESS RC 2019
T1 (1:1 xfrm) matches 50Ω off-chip load to 70Ω differential load resistance Common-Base output stage (Q1A,B) with current clamping (LE) Inter-stage matching (T2) introduces 3x AC current gain Cascode driver (Q2A,B-Q3A,B) in Class-A for high linearity Varactors (not shown) at collectors of Q3A,B for AM-PM correction
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Two-Way PA
G
G
S
Combiner
PA
LO I
LO Q
PAgm
gm
Signal Path of TX
ESSCIRC/ DE , Cracow, PolandESS RC 2019
Combiner and Splitter for two-way Power combining (similar PA cores) Up-Conversion with Double-Balance Gilbert Mixer structure. Programmable gain configuration with variable RE is employed to compensate the gain variation of
chain in corners.
LO IPLO IN
IDC
Q1 Q2
Q3 Q4 Q5 Q6
BB IP BB IN
LO IP
IDC
RE
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Chip Microphoto
Technology, 55nm SiGe BiCMOS by STM fT=320 GHz, fMAX=370 GHz Core Area of full TX is 690um x 320um Core Area of IQ LO Generator part is 170µm x 300 µm
IRR>40dB for 70-90GHz when Loop is on. Negligible impact of the input/output Power on IRR for different TX gains. OP1dB > 18dBm with -3dB bandwidth from 71GHz to > 90GHz with Pimage<-20 dBm.
ESSCIRC/ DE , Cracow, PolandESS RC 2019 18 of 19Farshad Piri
Compared to works in E-band +10dB IRR without calibration, higher OP1dB and efficiency levels.
Higher-order Modulations enabled thanks to large dynamic range.ESSCIRC/ESSDERC 2019, Cracow, Poland 19 of 19Farshad Piri
Conclusions
5G communication systems require high purity local oscillator signals.
Providing wideband quadrature LO signal with good IRR is challenging for higher-ordermodulations.
Delivering Large output power with high-efficiency in PA in silicon is limited.
A single-stage low-loss PPF stage in combination with a calibration loop is proposed toachieve both wide bandwidth, low loss, phase noise and high IRR.
From measurements, the TX performs well in compare to previously reported realizationsin terms of Image Rejection Ratio, Pout and efficiency
ESSCIRC/ESSDERC 2019, Cracow, Poland 20 of 19Farshad Piri
Thank You
Questions ?
ESSCIRC/ESSDERC 2019, Cracow, Poland 21 of 20Farshad Piri