DESIGN AND IMPLEMENTATION OF POWER OPTIMIZED HIGH PERFORMANCE 32 BIT FLOATING POINT ALU EMPLOYING BLOCK ENABLING TECHNIQUE Under the guidance of Dr .Y. SYAMALA Associate Professor Department of ECE Gudlavalleru Engineering College. By B N V A SURENDRA BABU 13481D5505 M.Tech -Embedded Systems.
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DESIGN AND IMPLEMENTATION OF POWER OPTIMIZED
HIGH PERFORMANCE 32 BIT FLOATING POINT ALU
EMPLOYING BLOCK ENABLING TECHNIQUE
Under the guidance of
Dr .Y. SYAMALA Associate Professor
Department of ECE
Gudlavalleru Engineering College.
By
B N V A SURENDRA BABU
13481D5505
M.Tech -Embedded Systems.
CONTENTS
Motivation
Introduction
Literature survey
Objective
Floating point ALU
Block enabling technique
Floating point ALU block diagram
Tools required
Plan of action
Conclusion
References
1-May-15 1
INTRODUCTION
Floating point describes a system for representingnumbers that would be too large or too small.
IEEE-754 32-bit Single-Precision Floating-PointNumbers represented as
The floating point coprocessor perform operationsmore efficiently and faster, so that it increasingthe overall speed of a computer.
1-May-15 3
LITERATURE SURVEY
In 2013, Manisha Sangwan and Angeline implemented Floating
point ALU with four basic operations like addition, subtraction,
multiplication ,division and they performed functional verification
of the system.
Itagi Mahal and S.S kerur implemented Floating point point ALU
in 2013, and they had shown results in terms of number of clock
cycles required for each operation.
In 2011, Ankit mitra implemented ALU with clock gating technique
and the results were compared with the ALU with out clock gating
technique.
Jagrit Kathuria and Ayoubkhan implemented different types of
clock gating techniques in 2011 and they had shown their simulation
results.
In 2013, Manisha and Anita Angeline implemented a Pipelined FP
Co-Processor which performs four basic arithmetic operations and
results were compared with the existing coprocessor.1-May-15 4
CONVENTIONAL FLOATING POINT ALU
1-May-15 5
OBJECTIVE
To design a 64bit floating point ALU core using
verilog HDL.
To simulate using xilinx-14.7 ISE simulator .
To synthesize using xilinx-14.7 XST synthesizer.
Power analysis will be observed using xilnx-
14.7 XPA .
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FLOWCHART FOR FLOATING POINT ADDER
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SIMULATION RESULTS OF FLOATING POINT ADDER
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SYNTHESIS RESULTS AND POWER ANALYSIS OF
FLOATINGPOINT ADDER
Number of Slice Registers utilized 617 out of 69120 0%
Number of Slice LUTs utilized 514 out of 69120 0%
Number of fully used LUT-FF pairs 330 out of 801 41%
umber of bonded IOBs utilized 198 out of 640 30%
Adders/ Subtractors 5
Registers 23
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frequency(MHZ) power(W)
100 1.212
200 1.376
300 1.535
400 1.693
500 1.849
Device utilization summary:
power analysis :
FLOWCHART FOR FLOATING POINT SUBTRACTOR
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SIMULATION RESULTS OF FLOATING POINT
SUBTRACTOR
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SYNTHESIS RESULTS AND POWER ANALYSIS OF
FLOATINGPOINT SUBTRACTOR
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frequency(MHZ) power(W)
10 1.074
100 1.278
200 1.506
300 1.731
400 1.955
500 2.719
Device utilization summary:
Number of Slice Registers utilized 689 out of 69120 0%
Number of Slice LUTs utilized 1138 out of 69120 1%
Number of fully used LUT-FF pairs 437 out of 1390 31%
umber of bonded IOBs utilized 437 out of 1390 31%
Adders/ Subtractors 3
Registers 688
power analysis :
FLOWCHART FOR FLOATING POINT MULTIPLIER
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SIMULATION RESULTS OF FLOATING POINT
MULTIPLIER
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SYNTHESIS RESULTS AND POWER ANALYSIS
OF FLOATINGPOINT MULTIPLIER
1-May-15 15
Device utilization summary:
Number of Slice Registers utilized 1214 out of 69120 1%
Number of Slice LUTs utilized 1991 out of 69120 2%
Number of fully used LUT-FF pairs 1060 out of 2145 49%
umber of bonded IOBs utilized 200 out of 640 31%
Adders/ Subtractors 9
Registers 1236
power analysis :
frequency(MHZ) power(W)
10 1.052
100 1.143
200 1.365
300 1.585
400 1.805
500 2.024
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FLOWCHART FOR FLOATING POINT DIVIDER
SIMULATION RESULTS OF FLOATING POINT
DIVISON MODULE
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SYNTHESIS RESULTS AND POWER ANALYSIS
OF FLOATINGPOINT DIVISION MODULE
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Device utilization summary:
Number of Slice Registers utilized 938 out of 69120 1%
Number of Slice LUTs utilized 1843 out of 69120 2%
Number of fully used LUT-FF pairs 638 out of 2143 29%
umber of bonded IOBs utilized 200 out of 640 31%
Adders/ Subtractors 10
Registers 919
power analysis :
frequency(MHZ) power(W)
10 1.059
100 1.221
200 1.388
300 1.552
400 1.716
500 1.879
BLOCK ENABLING TECHNIQUE
Changing the logic stateof the circuit leadsto power dissipation.
Block enabling techniqueis used to reduceunnecessary Switchingactivities.
1-May-15 7
FLOATING POINT ALU
In this work, the floating point ALU will be
designed to perform eight number of different
arithmetic and logical operations.
This floating point ALU is employed with block
enabling technique which is used to reduce the
total power consumption of the existing FPU.
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FLOATING POINT ALU
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TOOLS USED
Tools Required: Front end Design Tools-XILINX 14.7
Language Required: verilog HDL programming
language.
1-May-15 9
PLAN OF ACTION
S.NO ACTIVITY WEEKS(40)
1 Literature survey 3
2 Study and implementation of base paper 4
3 Implementation of floating point addition
/subtraction module+ Literaure survey.
3
4 Implementation of other floating point
modules +Literaure survey.
8
5 Implementation of floating point ALU with
block enabling technique.
6
6 Power Analysis of Proposed floating point ALU
and Conventional ALU +Literature survey
8
7 Paper publication work +Literature survey 4
8 Project documentation work +Literature survey 4
1-May-15 10
CONCLUSION
A double precision 64 bit floating point
ALU will implement with block enabling
technique.
The results of this proposed floating point
ALU with block enabling technique will
compared with the conventional floating
point ALU.
1-May-15 11
REFERENCES
[1] Manisha Sangwan, A Anita Angeline “Design and Implementation of Single Precision
Pipelined Floating Point Co-Processor” 2013 International Conference on Advanced