6. What is the function of program counter in 8085 microprocessor? (May-2013) Program counter stores the address of the next instruction to be fetched. Thus it is used as pointer to the instruction. 7. What is trap interrupt and its significance? (May-2012) This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable. TRAP has the highest priority. TRAP interrupt is edge and level triggered. This means that the TRAP must go high and remain high until it is acknowledged. This avoids false triggering caused by noise and transients. 8. List the control and status signals of 8085 and mention its need. (Dec-2012) ALE (Address Latch Enable) and (Read and Write) IO/ , S0 S1 READY 9. Define the function of parity flag and zero flag in 8085. (May-2012) Parity flag – Parity is defined by the number of one‟s present in the accumulator. After an arithmetic or logical operation if the result has an even number of ones, ie., even parity, the flag is set. If the parity is odd, flag is reset. Zero flag – the zero flag sets if the result of operation in ALU is zero and flag resets if result is non zero. The zero flag is also is also set if a certain register content becomes zero following an increment or decrement operation of that register. 10. To obtain a 320 ns clock, what should be the input clock frequency? What is the frequency of clock signal at CLK OUT? (May-2014) System clock frequency = 1/T = 1 / 320*10 -9 = 3.125 MHz Crystal clock frequency = 2* System clock frequency = 2*3.125*10 6 = 6.25 MHz The frequency of clock signal at CLK OUT= Crystal frequency/2 = 6.25/2 =3.125 MHz. 2
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Transcript
6. What is the function of program counter in 8085
microprocessor? (May-2013)
Program counter stores the address of the next instruction to be fetched. Thus it
is used as pointer to the instruction.
7. What is trap interrupt and its significance? (May-2012)
This interrupt is a non-maskable interrupt. It is unaffected by any mask or
interrupt enable. TRAP has the highest priority. TRAP interrupt is edge and level
triggered. This means that the TRAP must go high and remain high until it is
acknowledged. This avoids false triggering caused by noise and transients.
8. List the control and status signals of 8085 and mention its
need. (Dec-2012)
ALE (Address Latch Enable)
and (Read and Write)
IO/ , S0 S1
READY
9. Define the function of parity flag and zero flag in 8085. (May-2012)
Parity flag – Parity is defined by the number of one‟s present in the accumulator.
After an arithmetic or logical operation if the result has an even number of ones,
ie., even parity, the flag is set. If the parity is odd, flag is reset.
Zero flag – the zero flag sets if the result of operation in ALU is zero and flag
resets if result is non zero. The zero flag is also is also set if a certain register
content becomes zero following an increment or decrement operation of that
register.
10. To obtain a 320 ns clock, what should be the input clock frequency? What
is the frequency of clock signal at CLK OUT? (May-2014)
System clock frequency = 1/T = 1 / 320*10-9
= 3.125 MHz
Crystal clock frequency = 2* System clock frequency
= 2*3.125*106
= 6.25 MHz
The frequency of clock signal at CLK OUT= Crystal frequency/2
= 6.25/2
=3.125 MHz.
2
11. List the five interrupts pins available in the 8085.
(May-2010)
The five interrupt pins are
TRAP, RST 7.5, RST 6.5, RST 5.5, INTR.
12. Specify the size of data, address, and memory word and memory capacity
of 8085 microprocessor. (May-2011)
Size of data bus = 8-bits Size
of memory word = 8-bits
Size of address bus = 16-bits
Memory capacity = 64 Kbytes
13. What is interrupt? (May-2006, May-2009)
Interrupt is an external signal that causes a microprocessor to jump to a specific
subroutine.
14. How performance of a microprocessor is measured in terms of MIPS?
(June-2007)
The performance of a microprocessor is measured in terms of MIPS (Million
instructions per Second).
MIPS rate = 1/(Average time required for the execution of instruction * 106)
15. What are the different machine cycles in 8085 microprocessor? (May-2008)
4..Draw the timing diagram for Opcode Fetch machine cycle, Memory Read
machine cycle,MemoryWrite,I/O read machine cycle and I/O write machine Cycle.
(Nov/Dec-2014)
Instruction Cycle:
The time required to execute an instruction is called instruction cycle.
Machine Cycle
The time required to access the memory or input/output devices is called machine
cycle.
T-State
A portion of an operation carried out in one system clock period is called as T-state.The
machine cycle and instruction cycle takes multiple clock periods.
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Opcode Fetch Machine Cycle: Fig: Timing Diagram of 8085 Microprocessor
Opcode fetch cycle is part of any instruction execution. In this machine cycle 8085
fetches opcode of instruction. The following are the sequence of actions that are
performed by 8085 to fetch an opcode from memory. This machine cycle consists of 4
T-states.
8085 places 16-bit address from PC on to the address bus and issues ALE pulse in
first T-state (T1). This is used to de-multiplex the address and data bus. It also issues
IO/M‟ signal to „0‟. This indicates that processor is performing memory related
operation. In second T-state (T2) processor issues RD‟ control signal to memory.
This enables memory to put data present at the address location given in previous T-
state on to data bus. RD‟ control signal is active for two clock pulses.
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In T3 state memory places opcode on Data bus. Processor reads opcode present on
data bus and de-asserts RD‟ signal. Thus data bus goes into high impedance state.
In T4 state processor decodes instruction and necessary actions are performed.
Memory Read machine cycle:
This machine cycle is required when an operand is present in memory. This machine
cycle requires three T-states. The following are the sequence of actions performed by
microprocessor during this machine cycle.
In the first T-state (T1) 8085 places address on address bus and issues ALE signal.
And also IO/M‟ signal is made low, since it is memory related operation.
In the second T-state (T2), processor issues RD‟ control signal to memory. In
response to this memory places data on data bus.
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In the third T-state (T3), processor reads data from data bus, and de-asserts RD‟
signal.
Memory Write Machine cycle:
This machine cycle is required when the results of operation needs to store in memory.
This machine cycle requires three T-states. The following are sequence of actions
performed by processor in this machine cycle.
In first T-state (T1), 8085 processor places 16- bit address on address bus and issues
ALE signal. And also it makes IO/M‟ signal to low, indicating it is memory related
operation.
In second T-state (T2), processor places data to be written on data bus and asserts
WR‟ signal to the memory.
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In the third T-state (T3), memory stores the data and processor de-asserts WR‟
signal.
IO read machine cycle:
This machine cycle is required, when data needs to be read from an input device. This
machine cycle requires three T-states. The following are the sequence of actions
performed by processor during this machine cycle.
In the first T-state (T1) 8085 places port address(for IO mapped addresses port
address is 8-bit, but for memory mapped addresses IO device address is 16-bit, but
reading from such is performed by memory read machine cycle) on address bus and
issues ALE signal. And also IO/M‟ signal is made high, since it is IO related operation.
In the second T-state (T2), processor issues RD‟ control signal to IO peripheral.
In response to this input device places data on data bus.
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In the third T-state (T3), processor reads data from data bus, and de-asserts RD‟
signal.
IO write Machine cycle:
This machine cycle is required when data needs to be output to an output device. This
machine cycle requires three T-states. The following are the sequence of actions
performed by processor during this machine cycle.
In first T-state (T1), 8085 processor places 8-bit port address on address bus (for IO
mapped addresses port address is 8-bit, but for memory mapped addresses, IO device
address is 16-bit, but writing to such is performed by memory write machine cycle) and
issues ALE signal. And also it makes IO/M‟ signal to high, indicating it is IO related
operation.
In second T-state (T2), processor places data to be written on data bus and asserts
WR‟ signal to the peripheral.
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In the third T-state (T3), peripheral accepts the data and processor de-asserts
WR‟ signal.
5.Explain how the memory organization was done in 8085.
8085 has 16 bit address bus, hence it can access 216 no. of memory locations,
which is equal to 64KB memory. Memory is required to store program as well as data.
Since microprocessor doesn‟t have on-chip memory, we need to connect it
externally.So it requires addressing mechanism.
The following are the steps involved in interfacing memory with 8085 processor.
1. First decide the size of memory requires to be interfaced. Depending on
this we can say how many address lines are required for it. For example if you
want to interface 4KB (212) memory it requires 12 address lines. Remaining
address lines can be used in address decoding.
2. Depending on the size of memory required and given address range,
construct address decoding circuitry. This address decoding circuitry can be
implemented with NAND gates and/or decoders or using PAL.
3. Connect data bus of memory to processor data bus.
4. Generate the control signals required for memory using IO/M‟, WR‟, RD‟
signals of 8085 processor.
Example:
Interface 4KB memory to 8085 with starting address A000H.
1. 4KB memory requires 12 address lines for addressing as already
mentioned. But 8085 has 16 address lines. Hence four of address lines are used
for address decoding
2. Given that starting address for memory is A000H. So for 4KB memory
ending address becomes A000H+0FFFH (4KB) = AFFFH.
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A0-A11 address lines are directly connected to address bus of memory chip. A12-A15
are used for generating chip select signal for memory chip.
Address decoding circuit using 3X8 decoder:
A15 line is use for enabling 74x138 decoder chip. A12, A13, A14 lines are connected to
74X138 chip as inputs. When theses lines are 010 output should be „0‟. This is provided
at O2 pin of 74X138 chip.
Address decoding circuit using only NAND gates:
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A15, A14, A13, A12 inputs should be 1010, for enabling the chip. So the circuit for this
is as shown above.
Types of address decoding:
There are two types of address decoding mechanism, based on address lines used for
generating chip select signal.
1. Absolute decoding
2. Partial decoding
Absolute decoding:
All the higher order lines of microprocessor, left after using the required signals for
memory are completely used for generating chip select signal.This type of decoding is
called absolute decoding. Partial decoding:
Only some of the address lines of microprocessor left after using the required
signals for memory are used for generating chip select signal. Because of this multiple
address ranges will be formed. If total memory space is not required for the system
then, this type of address decoding can be used. The advantage of this technique is
fewer components are required for memory interfacing because of this board size
reduces and in turn cost reduces.
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UNIT-II PROGRAMMING OF 8085 PROCESSOR
PART - A
1. What is indexing? NOV/DEC 2012
Indexing technique allows programmer to point or refer the data stored in sequential
memory locations one by one.
2.What are the various types of 8085 instructions?
MAY/JUNE2013,NOV/DEC2011
1. Data transfer group – MOV A,B 2. Arithmetic group – ADD B 3. Logical group- ANA B 4. Branch group – JMP LABEL 5. Stack I/O and Machine Control group – PUSH,POP,HLT.
3. Explain the difference between a JMP instruction and CALL instruction.
MAY/JUNE2012
A JMP instruction permanently changes the program counter. A CALL instruction leaves information on the stack so that the original program
execution sequence can be resumed.
4. What is meant by lookup table? NOV/DEC 2014
A lookup table is an array that replaces runtime computation with a simpler array
indexing operation.The savings in terms of processing time can be significant, since
retrieving a value from memory is often faster than undergoing an expensive
computation or input/ouput operation.
5. Explain the functioning of CMP instructions? NOV/DEC 2015
This instruction subtracts the contents of the specified register from contents of
the accumulator and sets the condition flags as a result of the subtraction.
6. Mention the similarity and difference between compare and subtract
instructions. May/June 2014
The compare and subtract instructions both are subtract one operand from
another and sets the flag register accordingly.The subtract instruction stores the result
in the accumulator while the compare instruction does not store any result except flags.
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7. State the purpose and importance of NOP instruction. May/June 2014
The NOP instruction in CPU‟s is to insert a time delay.It may be useful to force
the CPU to wait for external (slower) devices to complete its work.
8. What are the different types of addressing modes?NOV/DEC 2013,MAY/JUNE
2012
The addressing modes specifies the location of the operand(data). The different
types are as follows 1. Immediate addressing 2. Register addressing 3. Direct addressing 4. Indirect addressing 5. Implicit addressing
9. Define stack and stack related instructions? MAY/JUNE
2013,NOV/DEC2012
The stack is a group of memory locations in the R/W memory that is used for the
temporary storage of binary information during the execution of the program. The stack
related instructions are PUSH and POP 10. State the function of given 8085 instructions:JP,JPE,JPO,JNZ
JP – Jump on positive
JPE- Jump on parity even
JPO- Jump on parity odd
JNZ-Jump if no zero
S=0
P=1
P=0
Z=0
11.What are subroutine?
Subroutine are group of instructions stored as a separate program in memory
and it is called from the main program whenever required.
12.What is a recursive procedures?
A recursive procedure is a procedure, which calls itself. Recursive procedures
are used to work with complex data structures called trees. If the procedure is called
with N=3,then the N is decremented by 1 after each procedure CALL and the procedure
is called until N=0.
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13. How to access subroutine with in the main program procedure? NOV/DEC
2013 i) Accessed by CALL & RET instruction ii)Machine code of instruction is put only once in the
memory iii)With procedures less memory is required iv)Parameters can be passed in registers, memory location or stack 14.What are the four instructions which control the interrupt structure of the
8085 microprocessor? DI(disable interrupts)
EI(enable interrupts)
RIM(read interrupt masks)
SIM(set interrupt masks)
15. How the microprocessor is synchronized with peripherals?
The timing and control unit synchronizes all the microprocessor operations with
clock and generates control signals necessary for communication between the
microprocessor and peripherals.
PART - B
1. What are the different addressing modes in 8085 microprocessor? Explain it
with an example? NOV/DEC 2015,NOV/DEC 2014,NOV/DEC 2012,MAY/JUNE 2012
MAY/JUNE 2011
Addressing mode specifies the location of operand(data).Every instruction of a
program has to operate on a data. The method of specifying the data to be operated by
the instruction is called Addressing. The 8085 has the following 5 different types of addressing.
1. Immediate Addressing
2. Direct Addressing
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3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing
1.Immediate Addressing :
In immediate addressing mode, the data is specified in the instruction itself. The data
will be a part of the program instruction.All instructions that have „I‟ in their mnemonics
are of Immediate addressing type.
Example: MVI A, 01H- Move the data 01H given in the instruction to A register.
2.Direct Addressing :
In direct addressing mode, the address of the data is specified in the instruction.The
data will be in memory. In this addressing mode, the program instructions and data can
be stored in different memory blocks. This type of addressing can be identified by 16-bit
address present in the instruction.
Example:LDA 4500H- Load the data available in memory location 4500H in A register.
3.Register Addressing :
In register addressing mode, the instruction specifies the name of the register in which
the data is available.This type of addressing can be identified by register names in the
instruction.
Example: MOV A, B -Move the content of B register to A register.
4.Register Indirect Addressing :
In register indirect addressing mode, the instruction specifies the name of the register in
which the address of the data is available. The data will be in memory and the address
will be in the register pair.
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This type of addressing can be identified by letter „M‟ present in the instruction.
Example: MOV A, M - The content of memory (data) addressed by HL pair is
moved to A register.
5.Implied Addressing :
In implied addressing mode, the instruction itself specifies the type of operation and
location of data to be operated. This type of instruction does not have any address,
register name, immediate data specified along with it.
Example:CMA - Complement the content of accumulator
2.Explain the Different types of instruction in 8085. NOV/DEC 2013,MAY/JUNE
2013,NOV/DEC 2012,MAY/JUNE 2012,MAY/JUNE 2011
An instruction is a command given to the microprocessor to perform specified operation
on a given data.The instruction set of a microprocessor is the collection of instructions
that the microprocessor is designed to execute.It is classified into
1. Data Transfer Instructions.
2. Arithmetic Instructions.
3. Logical Instructions.
4. Branching / Control Transfer Instructions.
5. Stack & I/O Machine Control Instructions.
1.DATA TRANSFER INSTRUCTIONS:
The data transfer instructions move the data between registers or between registers
and memory. It copies the data from source location to destination location.No flags will
be affected. MOVE INSTRUCTION:
MOV Rd, Rs
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MOV M, Rs
MOV Rd, M
This instruction copies the contents of the source register into the destination register.
The contents of the source register are not altered.If one of the operands is a memory
location, its location is specified by the contents of the HL registers.
Example: MOV B, C - This instruction move the content of C register to B register.
MOV B, M -This instruction move the content of memory location pointed by HL
register to B register.
MOVE IMMEDIATE 8-BIT:
MVI Rd, data
MVI M, data
The 8-bit data is stored in the destination registeror memory.If the operand is a memory
location, its location is specified by the contents of the HL registers.
Example:MVI A,01 - The data 01 will move to A register.
MVI M, 01 – The data 01 will move to the memory location pointed by HL
registers.
LOAD ACCUMULATOR:
LDA 16-bit address
The contents of a memory location, specified by a16-bit address in the operand, are
copied to the accumulator. The contents of the source are not altered. This is a 3-byte
instruction, the second byte specifies the low-order address and the third byte specifies
the high-order address. Example: LDA 4000 –The content of memory location 4000 is loaded into A register.
STORE ACCUMULATOR:
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STA 16-bit address
The contents of the accumulator are copied into the memory location specified by the
operand.This is a 3-byte instruction, the second byte specifies the low-order address
and the third byte specifies the high-order address. Example: STA 4500–The content of A register is loaded into memory location 4500.
EXCHANGE:
XCHG
The contents of register H are exchanged with the contents of register D, and the
contents of register L are exchanged with the contents of register E.
Example: XCHG :This instruction exchange the content of H and L with D and E
2.ARITHMETIC INSTRUCTIONS:
The arithmetic instructions includes addition, subtraction ,increment and decrement
operations.
ADDITION:
ADD REGISTER OR MEMORY TO ACCUMULATOR
ADD Rs
ADD M
The contents of the operand (register or memory) are added to the contents of the
accumulator and the result is stored in the accumulator. If the operand is a memory
location, its location is specified by the contents of the HL registers. All flags are
modified to reflect the result of the addition.
Example: ADD B – The content of A register is added with the content of B register and
the result is stored in A register.
ADD M -The content of A register is added with the content of
memory location pointed by HL register and the result is stored in A register.
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ADD REGISTER TO ACCUMULATOR WITH CARRY: ADC R
ADC M
The contents of the operand (register or memory) and the Carry flag are added to the
contents of the accumulator and the result is stored in the accumulator.If the operand is
a memory location, its location is specified by the contents of the HLregisters. All flags
are modified to reflect the result of the addition.
Example: ADC B -The content of A register is added with the content of B register and
also Carry and the result is stored in A register.
ADC M - The content of A register is added with the content of memory location
pointed by HL register and also carry and the result is stored in A register.
ADD IMMEDIATE TO ACCUMULATOR
ADI 8-bit data
The 8-bit data (operand) is added to the contents of the accumulator and the result is
stored in the accumulator.All flags are modified to reflect the result of the addition.
Example: ADI 45 – The data 45H is immediately added with the content of A register
and result Is stored in A register.
SUBTRACTION:
SUBTRACT REGISTER OR MEMORY FROM ACCUMULATOR
SUBRs
SUB M
The contents of the operand (register or memory) are subtracted from the contents of
the accumulator and the result is stored in the accumulator.If the operand is a memory
location, its location is specified by the contents of the HLregisters.All flags are modified
to reflect the result of the subtraction.
Example: SUB B – The content of A register is subtracted with the content of B register
and the result is stored in A register.
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SUB M -The content of A register is subtracted with the content of memory
location pointed by HL register and the result is stored in A register.
SUBTRACT SOURCE AND BORROW FROM ACCUMULATOR :
SBB R
SBB M
The contents of the operand (register or memory ) and the Borrow flag are subtracted
from the contents of the accumulator and the result is placed in the accumulator. If the
operand is a memory location, its location is specified by the contents of the HL
registers.All flags are modified to reflect the result in accumulator.
Example: SBB B -The content of A register is subtracted with the content of B register
and also Borrow flag and the result is stored in A register.
SBB M - The content of A register is subtracted with the content of memory
location pointed by HL register and also Borrow and the result is stored in A register.
SUBTRACT IMMEDIATE FROM ACCUMULATOR:
SUI 8-bit data
The 8-bit data (operand) is subtracted from the contents of the accumulator and the
result is stored in the accumulator. All flags are modified to reflect the result of the
subtraction.
Example: SUI 45 -The data 45H is immediately subtracted with the content of A register
and Result is stored in A register.
INCREMENT REGISTER OR MEMORY
INR R
INR M
The contents of the designated (register or memory) are incremented by 1 and the
result is stored in the same place.If the operand is a memory location, its location is
specified by the contents of the HL registers.
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Example:INR B – The content of B register is incremented by 1.
INR M – The content of memory location pointed by HL register is incremented by 1.
INCREMENT REGISTER PAIR:
INX R
The contents of the designated register pair are incremented by1 and the result is
stored in the same place.
Example: INX H – The HL register pair is incremented by 1 and showing the next
memory location.
DECREMENT REGISTER OR MEMORY
DCR R
DCR M
The contents of the designated (register or memory) are decremented by 1 and the
result is stored in the same place.If the operand is a memory location, its location is
specified by the contents of the HL registers. Example:DCR B – The content of B register is decremented by 1.
DCR M –The content of memory location pointed by HL register is decremented by 1.
DECREMENT REGISTER PAIR:
DCX R
The contents of the designated register pair are decremented by1 and the result is
stored in the same place.
Example: DCX H – The HL register pair is decremented by 1 and showing the previous
Memory location.
3.LOGICALINSTRUCTIONS:
The logical instructions includes AND,OR,XOR,Complement operations.
36
Logical AND :
Logical AND register or memory with accumulator
ANA R
ANA M
The contents of the accumulator are logically ANDed with the contents of the operand
(register or memory), and the result is placed in the accumulator.If the operand is a
memory location, its address is specified by the contents of HL registers.S, Z, P are
modified to reflect the result of the operation. CY is reset. AC is set.
Example: ANA B - The content of A register is ANDed with the content of B register
and the result is stored in A register.
ANA M - The content of A register is ANDed with the content of memory
location pointed by HL register and the result is stored A register.
LOGICAL AND IMMEDIATE WITH ACCUMULATOR
ANI 8-bit data
The contents of the accumulator are logically ANDed with the 8-bit data (operand) and
the result is placed in the accumulator.S, Z, P are modified to reflect the result of the
operation. CY is reset. AC is set.
Example: ANI 45 -The data 45H is immediately ANDed with the content of A register
and result is stored in A register.
EXCLUSIVE OR REGISTER OR MEMORY WITH ACCUMULATOR
XRA R
XRA M
The contents of the accumulator are Exclusive ORed with the contents of the operand
(register or memory), and the result is placed in the accumulator.If the operand is a
memory location, its address is specified by the contents of HL registers.
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S, Z, P are modified to reflect the result of the operation. CY and AC are reset.
Example: XRA B -The content of A register is XORed with the content of B register and
the result is stored in A register.
XRA M -The content of A register is XORed with the content of memory
location pointed by HL register and the result is stored A register.
EXCLUSIVE OR IMMEDIATE WITH ACCUMULATOR
XRI 8-bit data
The contents of the accumulator are Exclusive ORed with the8-bit data (operand) and
the result is placed in the accumulator.S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: XRI 45 -The data 45H is immediately XORed with the content of A register
and result is stored in A register.
LOGICAL OR REGISTER OR MEMORY WITH ACCUMULATOR
ORA R
ORA M
The contents of the accumulator are logically ORed with the contents of the operand
(register/memory), and the Result is placed in the accumulator.If the operand is a
memory location, its address is specified by the contents of HL registers.
S, Z, P are modified to reflect the result of the operation. CY and AC are reset.
Example: ORA B -The content of A register is ORed with the content of B register and
the result is stored in A register.
ORA M- The content of A register is ORed with the content of memory
location pointed by HL register and the result is stored A register.
LOGICAL OR IMMEDIATE WITH ACCUMULATOR:
38
ORI 8-bit data
The contents of the accumulator are logically ORed with the8-bit data (operand) and the
result is placed in the accumulator.S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: ORI 45 - The data 45H is immediately ORed with the content of A register
and result is stored in A register.
COMPLEMENT ACCUMULATOR:
CMA
The contents of the accumulator are complemented.
No flags are affected.
Example: CMA
COMPLEMENT CARRY:
CMC
The Carry flag is complemented.No other flags are affected.
Example: CMC
SET CARRY :
STC
The Carry flag is set to 1.No other flags are affected.
Example: STC
4. BRANCHING (CONTROL TRANSFER)INSTRUCTIONS :
The branching instructions are used to change the execution order.They are divided into
conditional jump/call or unconditional jump/call.
39
JUMP UNCONDITIONALLY
JMP 16-bit address
The program sequence is transferred to the memory location specified by the 16-bit
address given in the operand.
Example: JMP 4000
JUMP CONDITIONALLY
The program sequence is transferred to the memory location specified by the 16- bit
address given in the operand based on the specified flag of the PSW.
Example:
OPCODE DESCRIPTION FLAG STATUS
JC Jump on Carry CY = 1
JNC Jump on no Carry CY = 0
JP Jump on Positive S = 0
JM Jump on Minus S = 1
JZ Jump on Zero Z =1
JNZ Jump on no Zero Z = 0
JPE Jump on parity even P = 1
JPO Jump on parity odd P = 0
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UNCONDITIONAL SUBROUTINE CALL :
CALL 16-bit address
The program sequence is transferred to the memory location specified by the 16-bit
address given in the operand. Before the transfer, the address of the next instruction
after CALL the contents of the program counter is pushed onto the stack. Example: CALL 4000
CONDITIONAL SUBROUTINE CALL :
The program sequence is transferred to the memory location specified by the 16-bit
address given in the operand based on specified flag of the PSW. Before the transfer,
the address of the next instruction after the call the contents of the program counter is
pushed onto the stack.
Example: CZ 4000
OPCODE DESCRIPTION FLAG STATUS
CC Call on Carry CY = 1
CNC Call on no Carry CY = 0
CP Call on Positive S = 0
CM Call on Minus S = 1
CZ Call on Zero Z =1
CNZ Call on no Zero Z = 0
CPE Call on parity even P = 1
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CPO Call on parity odd P = 0
UNCONDITIONALRETURN FROM SUBROUTINE:
RET
The program sequence is transferred from the subroutine to the calling program. The
two bytes from the top of the stackare copied into the program counter, and program
execution begins at the new address.
Example: RET
CONDITIONAL RETURN FROM SUBROUTINE:
The program sequence is transferred from the subroutine to the calling program based
on the specified flag of the PSW.The two bytes from the top of the stack are copied into
the program counter, and program execution begins at the new address.
Example: RZ
OPCODE DESCRIPTION FLAG STATUS
RC Return on Carry CY = 1
RNC Return on no Carry CY = 0
RP Return on Positive S = 0
RM Return on Minus S = 1
RZ Return on Zero Z =1
RNZ Return on no Zero Z = 0
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RPE Return on parity even P = 1
RPO Return on parity odd P = 0
5.STACK I/O,MACHINE CONTROL INSTRUCTIONS:
These instructions are used to manipulate the stack to perform the input /output and to
alter the internal control flags.Unless specified the flags are not affected.
STACK INSTRUCTION:
PUSH :
Example: PUSH PSW
The contents of register A and the contents of condition flags which form the PSW are
pushed onto the stack.
POP INSTRUCTION:
Example: POP PSW
The contents of register A and the contents of condition flags which form the PSW are
restored from the stack.
I/O INSTRUCTION :
IN port
The data placed on the 8 bit bidirectional data bus by the specified port is moved to
register A.
OUT port
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The contents of register A are placed on the 8 bit data bus is transferred to the specified
port.
MACHINE CONTROL INSTRUCTION:
EI
The interrupt system is enabled.
DI
The interrupt system is disabled.
NOP
No Operation is performed.No flags are affected.
HLT
The processor is stopped.No flags are affected.
3.Write an 8085 ALP to add, subtract, multiply and divide two 8 bit numbers
stored at consecutive memory locations. NOV/DEC 2015
8 BIT ADDITION:
ALGORITHM:
1. Initialize memory pointer to data location.
2. Get the first number from memory in accumulator.
3. Get the second number and add it to the accumulator.
4. Store the answer at another memory location.
44
PROGRAM:
ADDRESS LABEL MNEMONICS OPERAND COMMENT
4100 START MVI C, 00 Clear C reg.
4101
4102 LXI H, 4500 Initialize HL reg. to
4500
4103
4104
4105 MOV A, M Transfer first data to
accumulator
4106 INX H Increment HL reg. to point
next memory Location.
4107 ADD M Add first number to acc.
Content.
4108 JNC L1 Jump to location if result
does not yield carry. 4109
410A
410B INR C Increment C reg.
410C L1 INX H Increment HL reg. to point
next memory Location.
410D MOV M, A Transfer the result from acc.
to memory.
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410E INX H Increment HL reg. to point
next memory Location.
410F MOV M, C Move carry to memory
4110 HLT Stop the program
8 BIT SUBTRACTION:
1. Initialize memory pointer to data location.
2. Get the first number from memory in accumulator.
3. Get the second number and subtract from the accumulator.
4. If the result yields a borrow, the content of the acc. is complemented and 01H is
added to it (2‟s complement). A register is cleared and the content of that reg. is
incremented in case there is a borrow. If there is no borrow the content of the
acc. is directly taken as the result.
5. Store the answer at next memory location.
PROGRAM:
ADDRESS LABEL MNEMONICS OPERAND COMMENT
4100 START MVI C, 00 Clear C reg.
4102
4102 LXI H, 4500 Initialize HL reg. to
4500 4103
4104
4105 MOV A, M Transferfirstdatato
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accumulator
4106 INX H Increment HL reg. to point
next mem. Location.
4107 SUB M Subtract first number from
acc. Content.
4108 JNC L1 Jump to location if result does
not yield borrow. 4109
410A
410B INR C Increment C reg.
410C CMA Complement the Acc. Content
410D ADI 01H Add 01H to content of acc.
410E
410F L1 INX H Increment HL reg. to point
next mem. Location.
4110 MOV M, A Transfer the result from acc.
to memory.
4111 INX H Increment HL reg. to point
next mem. Location.
4112 MOV M, C Move carry to mem.
4113 HLT Stop the program
8 BIT MULTIPLICATION:
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ALGORITHM:
LOGIC: Multiplication can be done by repeated addition.
1. Initialize memory pointer to data location.
2. Move multiplicand to a register.
3. Move the multiplier to another register.
4. Clear the accumulator.
5. Add multiplicand to accumulator
6. Decrement multiplier
7. Repeat step 5 till multiplier comes to zero.
8. The result, which is in the accumulator, is stored in a memory location.
PROGRAM:
ADDRESS LABEL MNEMONICS OPERAND COMMENT
4100 START LXI H, 4500 Initialize HL reg. to
4500
4101
4102
Transfer first data to reg. B 4103 MOV B, M
4104 INX H Increment HL reg. to point
next mem. Location.
4105 MVI A, 00H Clear the acc.
4106
4107 MVI C, 00H Clear C reg for carry
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4108
4109 L1 ADD M Add multiplicand multiplier
times.
410A JNC NEXT Jump to NEXT if there is
no carry 410B
410C
410D INR C Increment C reg
410E NEXT DCR B Decrement B reg
410F JNZ L1 Jump to L1 if B is not zero.
4110
4111
4112 INX H Increment HL reg. to point
next mem. Location.
4113 MOV M, A Transfer the result from
acc. to memory.
4114 INX H Increment HL reg. to point
next mem. Location.
4115 MOV M, C Transfer the result from C
reg. to memory.
4116 HLT Stop the program
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8 BIT DIVISION:
ALGORITHM:
LOGIC: Division is done using the method Repeated subtraction.
1. Load Divisor and Dividend
2. Subtract divisor from dividend
3. Count the number of times of subtraction which equals the quotient
4. Stop subtraction when the dividend is less than the divisor .The dividend now
becomes the remainder. Otherwise go to step 2.
5. stop the program execution.
PROGRAM:
ADDRESS LABEL MNEMONICS OPERAND COMMENTS
4100 MVI B,00 Clear B reg for quotient
4101
4102 LXI H,4500 Initialize HL reg. to
4500H 4103
4104
4105 MOV A,M Transfer dividend to acc.
4106 INX H Increment HL reg. to point
next mem. Location.
4107 LOOP SUB M Subtractdivisorfrom
dividend
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4108 INR B Increment B reg
4109 JNC LOOP Jump to LOOP if result
does not yield borrow 410A
410B
410C ADD M Add divisor to acc.
410D DCR B Decrement B reg
410E INX H Increment HL reg. to point
next mem. Location.
410F MOV M,A Transfer the remainder
from acc. to memory.
4110 INX H Increment HL reg. to point
next mem. Location.
4111 MOV M,B Transfer the quotient from
B reg. to memory.
4112 HLT Stop the program
4.Write an 8085 ALP to find largest & smallest numbers. MAY/JUNE 2011
LARGEST NUMBER:
ALGORITHM:
1. Place all the elements of an array in the consecutive memory locations.
2. Fetch the first element from the memory location and load it in the accumulator.
51
3. Initialize a counter (register) with the total number of elements in an array.
4. Decrement the counter by 1.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content (next element).
7. If the accumulator content is smaller, then move the memory content (largest
element) to the accumulator. Else continue.
8. Decrement the counter by 1.
9. Repeat steps 5 to 8 until the counter reaches zero
10. Store the result (accumulator content) in the specified memory location.
PROGRAM:
ADDRESS LABEL MNEMONICS OPERAND COMMENTS
8001 LXI H,8100 Initialize HL reg. to
8100H
8002
8003
8004 MVI B,04 Initialize B reg with no.
of comparisons(n-1)
8005
8006 MOV A,M Transfer first data to acc.
8007 LOOP1 INX H Increment HL reg. to
point next memory
location
8008 CMP M Compare M & A
8009 JNC LOOP If A is greater than M
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800A then go to loop
800B
800C MOV A,M Transfer data from M to
A reg
800D LOOP DCR B Decrement B reg
800E JNZ LOOP1 If B is not Zero go to
loop1 800F
8010
8011 STA 8105 Store the result in a
memory location. 8012
8013
8014 HLT Stop the program
SMALLEST NUMBER:
ALGORITHM:
1. Place all the elements of an array in the consecutive memory locations.
2. Fetch the first element from the memory location and load it in the accumulator.
3. Initialize a counter (register) with the total number of elements in an array.
4. Decrement the counter by 1.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content (next element).
7. If the accumulator content is smaller, then move the memory content (largest
element) to the accumulator. Else continue.
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8. Decrement the counter by 1.
9. Repeat steps 5 to 8 until the counter reaches zero
10. Store the result (accumulator content) in the specified memory location.
PROGRAM:
ADDRESS LABEL MNEMONICS OPERAND COMMENTS
8001 LXI H,8100 Initialize HL reg. to
8100H 8002
8003
8004 MVI B,04 Initialize B reg with no. of
comparisons(n-1) 8005
8006 MOV A,M Transfer first data to acc.
8007 LOOP1 INX H Increment HL reg. to point
next memory location
8008 CMP M Compare M & A
8009 JC LOOP If A is lesser than M then
go to loop 800A
800B
800C MOV A,M Transfer data from M to A
reg
800D LOOP DCR B Decrement B reg
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800E JNZ LOOP1 If B is not Zero go to loop1
800F
8010
8011 STA 8105 Store the result in a
memory location. 8012
8013
8014 HLT Stop the program
5.Write an 8085 ALP to arrange in ascending and descending order. MAY/JUNE
2013,MAY/JUNE 2012
Ascending Order:
ALGORITHM:
1. Get the numbers to be sorted from the memory locations.
2. Compare the first two numbers and if the first number is larger than second then
interchange the number. 3. If the first number is smaller, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order
PROGRAM:
ADDRESS LABEL MNEM ONICS OPERAND COMMENTS
8000 MVI B,04 Initialize B reg with
number of comparisons 8001
(n-1)
8002 LOOP 3 LXI H,8100 Initialize HL reg. to
55
8003 8100H
8004
8005 MVI C,04 Initialize C reg with no. of
comparisons(n-1) 8006
8007 LOOP2 MOV A,M Transfer first data to acc.
8008 INX H Increment HL reg. to point
next memory location
8009 CMP M Compare M & A
800A JC LOOP1 If A is less than M then go
to loop1 800B
800C
800D MOV D,M Transfer data from M to D
reg
800E MOV M,A Transfer data from acc to
M
800F DCX H Decrement HL pair
8010 MOV M,D Transfer data from D to M
8011 INX H Increment HL pair
8012 LOOP1 DCR C Decrement C reg
8013 JNZ LOOP2 If C is not zero go to loop2
8014
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8015
8016 DCR B Decrement B reg
8017 JNZ LOOP3 If B is not Zero go to loop3
8018
8019
801A HLT Stop the program
DESCENDING ORDER
ALGORITHM:
1. Get the numbers to be sorted from the memory locations.
2. Compare the first two numbers and if the first number is smaller than second then
interchange the number. 3. If the first number is larger, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order
PROGRAM:
ADDRESS LABEL MNEMONICS OPERAND COMMENTS
8000 MVI B,04 Initialize B reg with
number of comparisons 8001
(n-1)
8002 LOOP 3 LXI H,8100 Initialize HL reg. to
8100H 8003
8004
8005 MVI C,04 Initialize C reg with no.
of comparisons(n-1) 8006
57
8007 LOOP2 MOV A,M Transfer first data to
acc.
8008 INX H Increment HL reg. to
point next memory
location
8009 CMP M Compare M & A
800A JNC LOOP1 If A is greater than M
then go to loop1
800B
800C
800D MOV D,M Transfer data from M to
D reg
800E MOV M,A Transfer data from acc
to M
800F DCX H Decrement HL pair
8010 MOV M,D Transfer data from D to
M
8011 INX H Increment HL pair
8012 LOOP1 DCR C Decrement C reg
8013 JNZ LOOP2 If C is not zero go to
loop2
8014
8015
8016 DCR B Decrement B reg
58
8017 JNZ LOOP3 If B is not Zero go to
loop3 8018
8019
801A HLT Stop the program
59
UNIT-III 8051 MICROCONTROLLER
PART - A
1. What is Microcontroller?
A device which contains the microprocessor with integrated peripherals like memory,
serial ports, parallel ports, timer/counter, interrupt controller, data acquisition interfaces
like ADC, DAC is called microcontroller. 2. List the features of 8051 microcontroller. (Nov/Dec 2014)
The features are single supply +5 volt operation using HMOS technology. 4096 bytes
program memory on chip (not on 8031), 128 data memory on chip, Four register banks,
Two multiple modes, 16-bit timer/counter, Extensive Boolean processing capabilities, 64
KB external RAM size 3. How is the Program memory organized in an 8051 Microcontroller?
In an 8051 based system the entire 64KB program memory can be external or 4 KB
is internal and the remaining 60 KB is external. This is decided by the logic level of
the signal
EA Pin. When EA pin is tied high (+Vcc or 5 V) the first 4 KB of program memory is
internal and the remaining 60 KB is external. When EA pin is tied low (GND or 0 V) the
internal ROM is ignored and the entire 64 KB is external.
4. List the alternative functions assigned to port 3 pins of 8051 microcontroller.
(May/June 2011)
Port 3 Alternative
pins function
P3.0 Received Data
P3.1 Transmission Data
P3.2 INT0
P3.3 INT1
P3.4 T0
P3.5 T1
P3.6 WR
P3.7 RD
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5. What is the role of DPTR in 8051 Microcontroller?
The Data Pointer (DPTR) is the 8051s only user-accessible 16-bit (2-byte) register. The
Accumulator, "R" registers, and "B" register are all 1-byte values. DPTR, as the name
suggests, is used to point to data. It is used by a number of commands which allow the
8051 to access external memory. When the 8051 accesses external memory it will
access the external memory at the address indicated by DPTR. While DPTR is most
often used to point to data in external memory, many programmers often take
advantage of the fact that it‟s the only true 16-bit register available. It is often used to
store 2-byte values which have nothing to do with memory locations.
6. Mention the size of DPTR and stack pointer in 8051 microcontroller.
The DPTR is 16 bit data Register and SP is 8 bit Register. 7. What is the need of Coprocessor?
The general-purpose processors such as 8086 or 8085 are not optimized to do
arithmetic manipulations, CRT display manipulation and word processing. Hence we go
for a coprocessor, which is capable of doing dedicated functions (Special Operations) to
increase the overall execution speed of larger systems.
8. Write the vector address and priority sequence of 8051 interrupts (Nov/Dec
2014)
Vector
The interrupts are : address
External interrupt 0 : IE0: 0003H
TF0:
Timer interrupt 0 : 000BH
External interrupt 1 : IE1: 0013H
Timer Interrupt 1 : TF1:001BH
Serial Interrupt Receive
interrupt : RI: 0023H
Transmit interrupt : TI: 0023H
9. What are the addressing modes of 8051 microcontroller? (Nov/Dec 2014)
The 8051 provides a total of five distinct addressing modes.
or example, if you wish to enable Timer 1 Interrupt, you would execute either:
Polling Sequence:
The 8051 automatically evaluates whether an interrupt should occur after every
instruction. When checking for interrupt conditions, it checks them in the following order:
External 0 Interrupt
Timer 0 Interrupt
External 1 Interrupt
Timer 1 Interrupt
Serial Interrupt
This means that if a Serial Interrupt occurs at the exact same instant that an External 0
Interrupt occurs, the External 0 Interrupt will be executed first and the Serial Interrupt
will be executed once the External 0 Interrupt has completed.
Interrupt Priorities :
The 8051 offers two levels of interrupt priority: high and low. By using interrupt priorities
you may assign higher priority to certain interrupt conditions.Interrupt priorities are
controlled by the IP SFR (B8h).
Interrupt Priority Register (IP Register):
D7 D6 D5 D4 D3 D2 D1 D0
* * * PS PT1 PX1 PT0 PX0
The rules for interrupt priorities:
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Nothing can interrupt a high-priority interrupt--not even another high priority interrupt.
A high-priority interrupt may interrupt a low-priority interrupt.
A low-priority interrupt may only occur if no other interrupt is already executing.
If two interrupts occur at the same time, the interrupt with higher priority will execute first. If both interrupts are of the same priority the interrupt which is serviced first by polling sequence will be executed first.
Interrupt Signal Performance:
When an interrupt is triggered, the following actions are taken automatically by the
microcontroller
The current Program Counter is saved on the stack, low-byte first.
Interrupts of the same and lower priority are blocked.
In the case of Timer and External interrupts, the corresponding interrupt flag is cleared.
Program execution transfers to the corresponding interrupt handler vector
address.
The Interrupt Handler Routine executes.
If the interrupt being handled is a Timer or External interrupt, the microcontroller
automatically clears the interrupt flag before passing control to your interrupt handler
routine.
End of Interrupt:
An interrupt ends when the program executes the RETI (Return from Interrupt)
instruction. When the RETI instruction is executed the following actions are taken by the
microcontroller:
Two bytes are popped off the stack into the Program Counter to restore normal program execution.
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Interrupt status is restored to its pre-interrupt status.
Serial Interrupts :
Serial Interrupts are slightly different than the rest of the interrupts. There are two
interrupt flags: RI and TI. If either flag is set, a serial interrupt is triggered. In the serial
port, the RI bit is set when a byte is received by the serial port and the TI bit is set when
a byte has been sent. The serial interrupt is executed, because the RI flag was set or
because the TI flag was set--or because both flags were set. The, ISR must check the
status of these flags to determine what action is appropriate. The 8051 does not
automatically clear the RI and TI flags and it can be clear by interrupt handler.
3.Explain the memory organization of 8051 microcontroller.
The 8051 microcontroller has two types of
memory Program Memory
Data Memory
The separation of code and data memory in the 8051 is different from the usual Von
Neumann architecture, which defines that code and data can share the common
memory.
The separated memory architecture is referred to as Harvard architecture.
Program Memory:
Program memory – 64 KB of program memory includes the 4KB of the on- chip ROM. If
the address exceeds 0FFF H, it will access the external program memory. The
processor will come to know whether the user wants to use the Internal ROM or not
from the EA(active low) pin. If this pin is pulled low, it means that the user does not want
to use the Internal ROM available. The processor will 0000H-FFFFH from the external
Program Memory. If this pin is held high, the processor will access 0000H - 0FFFH from
the Internal ROM and as address goes above 0FFFH, it will access the external
Program Memory that is interfaced it
If EA (active low)= 5V
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Internal Program Memory (ROM) =0000H-0FFFH (4KB)
External Program Memory =1000H-FFFFH(60KB)
If EA (active low)= 0V
External Program Memory
=0000H-FFFFH(64KB)
Data Memory:
Data memory – 64 KB of external data memory and 128 bytes of internal data RAM and
21 special function registers. For accessing the external data memory, the processor
can either issue an 8 bit address or a 16 bit address. To access the internal data
memory, the 8 bit address is used. This 8 bit address can provide address space for
256 locations. The lower 128 addresses (0 – 127) are used as 128 bytes on chip RAM.
The upper part of the address space (128-255) is used to address the various SFR. The
Lowest 32 bytes (0-31) are reserved for 4 banks of 8 register each R0-R7,out of which
one bank may be used at any time. The working bank is specified in two bits of the
Program Status Word.
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4. Explain the port operation in 8051 microcontroller. (Nov/Dec 2015) (May/June
2015) I/O Port Configuration Each port of 8051 has bidirectional capability. Port 0 is called 'true bidirectional port' as it floats
(tristated) when configured as input. Port-1, 2, 3 are called 'quasi bidirectional port'. Port-0 Pin Structure Port-0
has 8 pins (P0.0-P0.7). The structure of a Port-0 pin is shown in fig 1
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Fig 1: Port-0 Structure
Port-1 Pin Structure:
Port-1 has 8 pins (P1.1-P1.7) .
The structure of a port-1 pin is shown in fig 2.
Fig 2 Port 1 Structure
Port-1 does not have any alternate function. It is dedicated only for I/O interfacing. When used
as output port, the pin is pulled up or down through internal pull-up. To use port-1 as input port,
'1' has to be written to the latch. In this input mode when '1' is written to the pin by the external
device then it read. When '0' is written to the pin by the external device then the external source
must sink current due to internal pull-up. If the external device is not able to sink the current the
pin voltage may rise, leading to a possible wrong reading. Port-2 has 8-pins (P2.0-P2.7) .
The structure of a port-2 pin is shown in fig 3.
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Fig 3 Port 2 Structure
Port-2 is used for higher external address byte or a normal input/output port. The I/O operation is
similar to Port-1. Port-2 latch remains stable when Port-2 pin are used for external memory
access. Due to internal pull-up there is limited current driving capability.
PORT 3 Pin Structure:
Port-3 has 8 pin (P3.0-P3.7) . Port-3 pins have alternate functions.
The structure of a port-3 pin is shown in fig 4.
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Fig 4 Port 3 Structure
Each pin of Port-3 can be individually programmed for I/O operation or for alternate function.
The alternate function can be activated only if the corresponding latch has been written to '1'.
To use the port as input port, '1' should be written to the latch. This port also has internal pull-up
and limited current driving capability.
5.Draw the pin diagram of 8051 microcontroller and explain its port structure.
Port 0(p0.0 to p0.7):
It is 8-bit bi-directional I/O port. It is bit/ byte addressable. During external memory access, it
functions as multiplexed data and low-order address bus AD0-AD7.
Port 1 (p1.0 to p1.7):
It is 8-bit bi-directional I/O port. It is bit/ byte addressable. When logic '1' is written into port latch
then it works as input mode. It functions as simply I/O port and it does not have any alternative
function. Port 0(p0.0 to p0.7):
It is 8-bit bi-directional I/O port. It is bit/ byte addressable. During external memory access, it
functions as multiplexed data and low-order address bus AD0-AD7.
Port 1 (p1.0 to p1.7):
It is 8-bit bi-directional I/O port. It is bit/ byte addressable. When logic '1' is written into port latch
then it works as input mode. It functions as simply I/O port and it does not have any alternative
function.
Port 2 (p2.0 to p2.7):
It is 8-bit bi-directional I/O port. It is bit/ byte addressable. During external memory access it
functions as higher order address bus (A8-A15).
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Port 3(p3.0 to port 3.7):
It is 8-bit I/O port. In an alternating function each pins can be used as a special function I/O pin.
P3.0-RxD:
It is an Input signal. Through this I/P signal microcontroller receives serial data of serial
communication circuit.
Fig: Pin Diagram of 8051 Microcontroller
80
P3.1-TxD:
It is O/P signal of serial port. Through this signal data is transmitted.
P3.2- (INT0):
It is external hardware interrupt I/P signal. Through this user, programmer or peripheral
interrupts to microcontroller.
P3.3-(INT1):
It is external hardware interrupt I/P signal. Through this user, programmer or peripheral
interrupts to microcontroller.
P3.4- T0:
It is I/P signal to internal timer-0 circuit. External clock pulses can connects to timer-0
through this I/P signal.
P3.5-T1:
It is I/P signal to internal timer-1 circuit. External clock pulses can connects to timer-1
through this I/P signal.
P3.6-WR:
It is active low write O/P control signal. During External RAM (Data memory) access it is
generated by microcontroller. when [WR(bar)]=0, then performs write operation.
P3.7- RD:
It is active low read O/P control signal. During External RAM (Data memory) access it is
generated by microcontroller. when [RD(bar)]=0, then performs read operation from
external RAM.
XTAL1 and XTAL2:
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These are two I/P line for on-chip oscillator and clock generator circuit. A resonant
network as quartz crystal is connected between these two pin. 8051 microcontroller also
drives from external clock, then XTAL2 is used to drive 8051 from external clock and
XTAL1 should be grounded.
EA/VPP:
It is and active low I/P to 8051 microcontroller. when (EA)= 0, then 8051 microcontroller
access from external program memory (ROM) only. When (EA) = 1, then it access
internal and external program memories (ROMS).
PSEN:
It is active low O/P signal. It is used to enable external program memory (ROM). When
[PSEN(bar)]= 0, then external program memory becomes enabled and microcontroller
read content of external memory location. Therefore it is connected to (OE) of external
ROM. It is activated twice every external ROM memory cycle.
ALE:
Address latch enable: It is active high O/P signal. When it goes high, external address
latch becomes enabling and lower address of external memory (RAM or ROM) latched
into it. Thus it separates A0-A7 address from AD0-AD7. It provides properly timed signal
to latch lower byte address. The ALE is activated twice in every machine cycle. If
external RAM & ROM is not accessed, then ALE is activated at constant rate of 1/6
oscillator frequency, which can be used as a clock pulses for driving external devices.
RESET:
It is active high I/P signal. It should be maintained high for at least two machine cycle
while oscillator is running then 8051 microcontroller resets.
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UNIT- IV PERIPHERAL INTERFACING
PART - A
1. Bring about the features of 8259. (May/June-2014)
It is a programmable interrupt controller. It manages eight interrupt requests. 2.
The interrupt vector addresses are programmable. 3. The priorities of interrupts are
programmable. 4. The interrupt can be masked or unmasked individually
2. How data is transmitted in asynchronous serial communication? (May/June-
2014)
In asynchronous data transfer, one character is transferred at a time. Start and
stop bits are used with each character. The transmitter and receiver use two separate
clock inputs here.
3. What are the internal registers available in 8259 PIC? (Apr/May-2015)
Interrupt mask register (IMR), Interrupt Request register(IRR),In service
register(ISR) and Priority register(PR)
4. Distinguish between synchronous and asynchronous transmission.
(Apr/May-2015)
Asynchronous
synchronous
In this,a word or character is preceeded by a
In
this,the
transmission
begins
with a block header,
Start bit and is followed by a stop bit.
Which is a sequence of bits.
Data can be sent one character at a time
amount of data
used for transferring large
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5. What are the functions of USART? (Nov/Dec-2014)
USART stands for universal Synchronous / Asynchronous Receiver /
Transmitter. It is a programmable communication interface that can communicate by
using either synchronous or asynchronous serial data.
6. What is scan counter in 8279? (Nov/Dec-2012)
The scan counter has two modes to scan the key matrix and refresh the display.
In the encoded mode, the counter provides binary count that is to be externally decoded
to provide the scan linesfor keyboard and display. In the decoded scan mode, the
counter internally decodes the least significant 2 bit and provides a decoded 1 out of 4
scan on SL3-SL 3. The keyboard and display both are in the same mode at a time.
7. What are the basic modes of operations of 8255? (Nov/Dec-2013)
a) I/O Mode i. Mode 0- Simple Input/Output. ii. Mode 1- Strobe Input/Output
(handshake mode) iii. Mode 2- Strobe bi-directional mode b) Bit Set/Reset Mode.
8. List out the operating modes in 8253 Timer/Counter. (Nov/Dec-2014)
The timer has three counters.or timers which are named as "Counter 0", "Counter 1"
and "Counter 2".Each counter has 2 input pins – "CLK" (clock input) and "GATE" – and
1-pin, "OUT", for data output. The 3 counters are 16-bit down counters independent of
each other, and can be easily read by the CPU. The first counter is used to generate
atimekeeping interrupt.The second counter is used to trigger the refresh of DRAM
memory. The last counter is used to generate tones via the PC speaker. Data/Bus Buffer: This block contains the logic to buffer the data bus to / from the microprocessor, and to
the internal registers. It has 8 input pins, usually labelled as D7..D0, where D7 is the
MSB.
Read/Write Logic: The Read/Write Logic block has 5 pins.
This instruction adds data from R0 register and Accumulator and finally result is
stored in Acc.
Syntax:
ADD A, direct
Ex:ADD A,40H
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This instruction adds data from 40H location and Accumulator and finally result is
stored in Acc.
Syntax:
ADD A, @Ri
Ex: ADD A, @R0
This instruction adds data from the content of R0 as a location and Accumulator
and finally result is stored in Acc..
Syntax:
ADD A, #data
EX: ADD A, # 40H
This instruction adds immediate data 40H and Accumulator and finally result is
stored in Acc..
3.Logical Instructions
The logical instructions includes AND,OR,EXOR,Rotate instructions.
Syntax:
ANLRn , Rn
Ex:ANL A,R0
This instruction AND with data from R0register,Accumulator and finally result is
stored in Acc.
Syntax:
ANL A, direct
Ex:ANL A,40H
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This instruction AND with data from 40H location,Accumulator and finally result is
stored in Acc.
Syntax:
ANL A, @Ri
Ex: ANL A, @R0
This instruction AND with data from the content of R0 as a location,Accumulator
and finally result is stored in Acc..
Syntax:
ANL A, #data
EX: ANL A, # 40H
This instruction AND immediate data 40H ,Accumulator and finally result is
stored in Acc..
5.Control Transfer Instructions
ACALL addr11
Absolute Call to relative address
AJMP addr11
Asolute Jump to relative address
CJNE A, direct, rel
Compare with A with memory location content if not equal then jump to relative address.
DJNZ Rn, rel
Decrement Rn, and jump if not zero to relative address
JC rel
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Jump if carry to relative address
JNC rel
Jump if no carry to relative address
2.Explain in detail about 8051 Addressing Modes(May/June 2014)
8051 has four addressing modes.
1.Register Addressing.
2.Direct Addressing.
3.Register Indirect Addressing.
4.Immediate Addressing
5.Base plus Index Register Addressing.
1.Register Addressing:
This way of addressing accesses the bytes in the current register bank.
Data is available in the register specified in the instruction.
The register bank is decided by 2 bits of ProgramStatusWord (PSW).
Example-
ADD A, R0
This instruction Adds content of R0 to A and stores in A
2.Direct Addressing:
The address of the data is available in the instruction.
Example -
MOV A, 88H;
Moves the content of address 88Hto A.
3.Register Indirect Addressing:
The address of data is available in the R0 or R1 registers as specified in the
instruction.
Example –
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MOV A, @R0
Moves content of address pointed by R0 to A .
4.Immediate Addressing:
Data is immediately available in the instruction.
Example -
ADD A, #77H
Adds 77 H to A and stores in A
5.Base plus Index Register Addressing.
The content of base register and index register content is added to locate the
data.
Example -
MOVC A, @A+DPTR
Moves content of address pointed by A+DPTR to A
3. Draw the schematic for interfacing a stepper motor with 8051 microcontroller
and write 8051 ALP for changing speed and direction of motor. The complete board consists of transformer, control circuit, keypad and stepper motor .
The circuit has inbuilt 5 V power supply so when it is connected with transformer it will
give the supply to circuit and motor both.
The 8 Key keypad is connected with circuit through which user can give the command
to control stepper motor. The control circuit includes micro controller 89C51, indicating
LEDs, and current driver chip ULN2003A. By giving different commands the stepper
motor can run clockwise, run anticlockwise, increase/decrease RPM,increase/decrease
revolutions, stop motor, change the mode, etc. Stepper motor has four coils.One end of
each coil is tied together and it gives common terminal which is always connected with
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positive terminal of supply. The other ends of each coil are given for interface. Specific
color code may also be given.
First Coil L1-Orange
Second Coil L2 -Brown
Third Coil L3 - Yellow
Fourth Coil L4 - Black
Common Terminal -Red
By means of controlling a stepper motor operation we can
1. Increase or decrease the RPM (speed) of it 2. Increase or decrease number of revolutions of it 3. Change its direction means rotate it clockwise or anticlockwise
Fig:Interfacing of stepper motor with 8051 Microcontroller
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To vary the RPM of motor we have to vary the PRF (Pulse Repetition Frequency).
Number of applied pulses will vary number of rotations and last to change direction we
have to change pulse sequence. So all these three things just depends on applied
pulses. Now there are three different modes to rotate this motor 1. Single coil excitation 2. Double coil excitation 3. Half step excitation
Pulses for stepper motor module
Clockwise B2 B1 A2 A1 Anti
clockwise D3 D2 D1 D0
1 1 0 0
1 0 0 1
0 0 1 1
0 1 1 0
1 1 0 0
The circuit consists of very few components. The major components are 7805, 89C51
and ULN2003A.
Connections:-
1. The transformer terminals are given to bridge rectifier to generate rectified DC. 2. It is filtered and given to regulator IC 7805 to generate 5 V pure DC. LED
indicates supply is ON. 3. All the push button micro switches J1 to J8 are connected with port P1 as shown to
form serial keyboard. 4. 12 MHz crystal is connected to oscillator terminals of 89C51 with two biasing
capacitors. 5. All the LEDs are connected to port P0 as shown 6. Port P2 drives stepper motor through current driver chip ULN2003A. 7. The common terminal of motor is connected to Vcc and rest all four terminals are
connected to port P2 pins in sequence through ULN chip.
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4. Draw the schematic for interfacing a servo motor with 8051 microcontroller and
write for servo motor control. (Nov/Dec 2014)
Servo motors are self-contained mechanical devices that are used to control the
machines with machines. Usually the servo motor is used to control the angular motion
among from 0° to 180° and 0° to 90°. The servo motor working principle based on the
PWM (pulse width modulation) pulses.
A Servo motor is one of the most commonly used motor for precise angular
movement. The advantage of using a servo motor is that the angular position of the
motor can be controlled without any feedback mechanism.
Pulse Width Modulated (PWM) waves are used as control signals and the angular
position is definite by the width of the pulse at the control input. Servo motor having
angle of rotation from 0-180° and angular position can be controlled by varying the duty
cycles among 1ms to 2ms.The control of servo motor connected port0 of 8051
microcontroller. The 11.0592MHz crystal oscillator is used to provide the clock pulsed to
the microcontroller and 22pf ceramic capacitors used to stabilize the operation of
crystal. 10KΩ and 10uf capacitor is used to provide the power on reset to the
microcontroller.
Controlling a Servo Motor with Angle rotations
Servo motor working principle mainly depends upon duty cycles. It uses Pulse Width
Modulated (PWM) waves as control signals. The angle of rotation is resolute by the
pulse width of the control pin.
Servo Motor Working Principle
The servo motor working principle mainly depends upon the „Fleming left hand rule‟.
Basically servo motors are adapted with DC motors, a position sensor, a Gear
reduction, and an electronic circuit. The DC motors achieve powered from a battery and
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run at high speed and low torque. We assembled shaft and gear connected to DC
motors then we can increase and decrease the motor speed gradually.
Fig:Interfacing of servo motor with 8051 Microcontroller
The position sensor senses the location of the shaft from its fixed position and sends
the information to the control circuit. The control circuit decodes the signals accordingly
from the position sensor and compares the actual location of the motors with the
preferred position and accordingly controls the direction of rotation of the DC motor to
get the necessary position. Generally the servo motor requires 4.8V to 6 V DC supply.
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5. Draw the schematic for interfacing a washing machine control with 8051
microcontroller and write8051 ALP for washing machine control. (Nov/Dec 2014)
A washing machine is an electronic device that is designed to wash laundry like clothes,
sheets, towels and other bedding. A washing machine is built with two steel tubs which
are the inner tub and the outer tub whose main role is to prevent water from spilling to
other parts of the machine.
Fig:Interfacing of washing maachine with 8051 Microcontroller
Control knobs in washing machine:
• Load select knob
• Water inlet select knob
• Mode select knob
• Program select knob
Load select knob:- load Number of clothes low medium high Load select
Water inlet select knob:- hot cold both-mixed Water inlet
Mode select knob:- Save mode Normal mode Mode
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Program select knob:- Heavy Clothes very dirty Normal Normal dirty clothes LIGHT
For light dirty clothes Delicate For silk clothes
Machine Operations:-
• Fill:- water will be filled by the pump as per the load knob selected.
• Agitate:- The wash basket will rotate in a clockwise direction for 10 revolutions,
After that basket will stop for 2 seconds, then rotate 10 revolutions in anticlockwise
direction. The process will be continued for specified minutes in cycle table.Drain:- After
agitation, the water and detergent are drained.
Spin:- During spin, agitator will be stationary, only the basket will rotate at
high speed. Then the moisture of clothes are removed through holes in
the inner metallic basket.
Machine Indicators:-
Machine ON
LED ON After completion of washing cycle, buzzer sound will be
generated.
Washing cycle :
Heavy
Normal
Light
Delicate
Washing Machine Drives/Connections:
The drives of the washing machine is connected to 8051 Microcontroller
ports. Hot/Cold Agitator motor drive
Agitator motor drive
Spin motor drive
High level
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Medium level
Low level
Drain
Washing machine ON LED
Heavy
Normal
Light
Delicate
Hot
Normal Buzzer sound Basket
Washing Machine Operation SinalsInput/Output :
The various Operation Signals are connected to microcontroller Input/output Port.
Load / water level select
Water inlet
Program select
Machine ON
Fill water
Agitation control
Output
Spin
Washing complete
Program:Commands for washing-machine controller
SETB LCALL JNB SJMP P2.0
FILL_1 P1.0,LOOP_1 HEAVY Machine ON indication Machine fill with water 1st time
Chkprogsetng knob for heavy.
If P1.0 is not set,jump to LOOP_1
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If P1.0 is set,jump to HEAVY LOOP_1 JNB SJMP P1.1,LOOP_2 NORMAL Check
progsetng knob for normal
If P1.1 is not set.jump to LOOP_2
If P1.1 is set, jump to NORM LOOP_2 JNB SJMP P1.2,LOOP_3 Chckprogsetng knob
for normal.
If P1.2 is not set,jump to LOOP_3
If P1.2 is set,jump to LIGHT LOOP_3 JNB SJMP P1.3,LOOP_4 DELICATE Check prog
set knob for delicate.
If P1.3is not set,jump to LOOP_4 If P1.2 is set,jump to delicate DISPLAY SETB P2.7
Indicate the completion of wash cycle. LOOP_4 NOP LJMP 0000 End of program