#6 - Processing Unit Design

8/12/2019 #6 - Processing Unit Design

1/49

DESIGN OF THE BASICPROCESSING UNIT

BOOK : COMPUTER ORGANISATIONCarl Hamacher Zvonko Vrane !c

Sa"#a$ Zak%


2/49

Topics Under Review

How a processor executes instructions The interna !unctiona units o! aprocessor an" how the# areinterconnecte"$

Har"ware !or %eneratin% internacontro si%na s

The &icropro%ra&&in% approach 'icropro%ra& or%ani(ation


3/49

Processing Unit

The CPU executes a sequence ofinstructions.

The execution of an instruction isorganized as an instruction cycle: it isperformed as a succession of severalsteps;

Each step is executed as a set of

several microoperations.


4/49

Instruction Execution

The processor !etches one instruction at a ti&e an"per!or&s the operations speci!ie"$

Instructions are !etche" !ro& successi)e &e&or#ocations unti a *ranch or a +u&p instruction isencountere"$

The Pro%ra& Counter ,PC- re%ister .eeps trac. o!the a""ress o! the &e&or# ocation !ro& where thenext instruction is to *e !etche"$

PC is up"ate" a!ter each instruction is !etche"$ One instruct &a# occup# &ore than one wor" /

re0uirin% &ore than one !etch operation$


5/49

Basic Instruction Cycle

etch the next!nstruction

"ecode!nstruction

etch#perand$s%

Execute!nstruction

&tart

&top

!f #perand$s%

required

#pcode etch Cycle

"ecode Cycle

#perand etch Cycle

Execute Cycle

Yes

No


6/49

Sin% e Bus Or%anisation o! a Processor

PC

'()

'")

*

+

!)

),

)$n- %

TE'P

'U/

( 0

(1U

Constant2alue

.

.

.

!nstruction"ecoder andControl logic

Control signals. . . .

Carry !n

(ddress 1ines

"ata 1ines ! n t er n

al P r o

c e s s or 0

u s

'emory0us

&elect

(dd

&u3

/#)

.

.

.

(1UControl1ines


7/49

Instruction Execution

The tas4 performed 3y any microoperationfalls in one of the follo5ing categories: Transfer data from one register to another; Transfer data from a register to an external

interface $system 3us%; Transfer data from an external interface to a

register; Perform an arithmetic or logic operation6 using

registers for input and output.


8/49

The CPU executes an instruction as a se uence o!control steps" In each control step one or several#icrooperations are executed"

$ne cloc% pulse triggers the activities corresponding toone control step & !or each cloc% pulse the control unitgenerates the control signals corresponding to the#icrooperations to 'e executed in the respective controlstep

Control Signals


9/49

Input an" Output Gatin% !or the Re%isters

! n t er n al P r o

c e s s or 0

u s

/

/

/

/

/

Ri

Y

Z

'U/

( 0

(1U

Riin

Riout

Yin

Select

Constant

Zin

Zout

R( R)7 R)$UT * )7 P+,CE o-p o! R) T$

BU.7 R(I/ * )7 +$,0. 0,T, 1R$M

BU. T$ R(


10/49

I/p and O/p Gating for One RegisterBit


11/49

Control Signals

In or"er to a ow the execution o! a microoperation 1 one or se)eracontrol signals ha)e to *e issue"2 the# a ow the correspon"in% "atatrans!er an"3or co&putation to *e per!or&e"$

Exa&p es4

a- si%na s !or trans!errin% content o! re%ister R5 to R64R5out1 R6in

*- si%na s !or a""in% content o! 7 to that o! R5 ,resu t in 8-4

R5out1 A""1 8in

c- si%na s !or rea"in% a &e&or# ocation2 a""ress in R94

R9out1 'ARin1 Rea"


12/49

Register Trans!ers

Instruction execution in)o )es a serieso! steps in which "ata are trans!erre"!ro& one re%ister to another$

For each re%ister1 two contro si%na sare use" to p ace the contents o! there%ister on to the *us or or to oa" the"ata on the *us into the re%isters$


13/49

Re%ister Trans!er

Ti&in% o! a processor operations an""ata trans!ers within the processor"e!ine" *# the processor c oc.$

Contro si%na s are asserte" at the*e%innin% o! the c oc. c#c e$

The re%isters are &a"e o! e"%etri%%ere" ! ip ! ops$

Exa&p e R: R6


14/49

Per!or#ing an , or + operation A;U has no interna stora%e$ One I3p co&es !ro& the O3p o! 'ux an" the other co&es

"irect # !ro& the *us$ The resu ts are te&porari # store" in 8$ The contro si%na s are acti)ate" !or the "uration o! the

c oc. c#c e correspon"in% to the step1 a other si%na s areinacti)e$R9 R6 < R=

R6OUT 1 7INR=OUT 1 SE;ECT 7 1 ADD 1 8IN8OUT 1 R9IN


15/49

1etching a 2ord !ro# Me#ory

The processor has to speci!# the re0uire" &e&or#a""ress an" re0uest a READ operation$ The re0uire" a""ress is trans!erre" to 'AR whose

o3p is connecte" to the a""ress ines o! the &e&or#*us$

Processor uses the contro ines o! the &e&or# *usto in"icate that a READ operation is re0uire"$

The "ata rea" !ro& the &e&or# are store" in 'DR!ro& where the# can *e trans!erre" to where the#are nee"e"$


16/49

/

/

/

/

MDR

'emory 0us"ata 1ines

!nternal Processor 0us

'")outE '")out

'")inE '")in

Connection and control signals !or the register M0R


17/49

Exa#ple

For R= '>R6?6$ 'AR >R6?

=$ Start rea" on &e&or# *us9$ @ait !or 'e&or# Function Co&p ete" ,'FC- !ro& &e&or#:$ ;oa" 'DR !ro& *us$ R= >'DR?

Si%na s *ein% Acti)ate"6$ R6out1 'ARin1 Rea"=$ 'DRinE1 @'FC ,wait !or 'FC-9$ 'DRout1R=in


18/49

Co&p ete Instruction Execution

Exa&p e ADD R61 '>R9? A""s the contents o! the &e&or# ocationpointe" to *# R9 to re%ister R6$ Fetch the instruction Fetch the !irst operan" ,the contents o! the

&e&or# ocation pointe" to *# R9- Per!or& the a""ition$ ;oa" the resu t into R6


19/49


20/49

Sin% e Bus Or%anisation o! a Processor

PC

'()

'")

*

+

!)

),

)$n- %

TE'P

'U/

( 0

(1U

Constant2alue

.

.

.

!nstruction"ecoder andControl logic

Control signals. . . .

Carry !n

(ddress 1ines

"ata 1ines ! n t er n

al P r o

c e s s or 0

u s

'emory0us

&elect

(dd

&u3

/#)

.

.

.

(1UControl1ines


21/49

Instruction 1etch Phase

)" PC loaded into M,R3 read re uest to #e#ory3 MU4 gives (3added to B 5PC6 andstored in 7

PC$UT3 M,RI/3 RE,03 .E+ECT8(3 ,003 7I/

9" 7 #oved to PC while waiting !or #e#ory7$UT3 PCI/3 :I/3 2M1C

;" 2ord !etched !ro# #e#ory and loaded into IRM0R$UT3 IRI/

1igure out what the instruction should do and set control circuitry !or steps (8


22/49

Pro'le#

Assu&in% a &e&or# rea" or write operationta.es the sa&e ti&e as one internaprocessor step an" that *oth the processoran" the &e&or# are contro e" *# the sa&e

c oc.$ Esti&ate execution ti&e @hat wi *e the execution ti&e i! the

&e&or# access ti&e is e0ua to twice theprocessor c oc. perio"$

< cloc%s > cloc%s


23/49

Pro'le#s 'ased on .ingle Bus structure

Assu&in% that each instruction consists o! twowor"s$ The !irst wor" speci!ies theoperation an" the secon" wor" containsthe nu&*er NU'$ A so assu&e a sin% e *usstructure as "iscusse"$ @rite the se0uenceo! contro steps re0uire" !or4

a- A"" the nu&*er NU' to re%ister R6*- A"" the contents o! &e&or# ocation NU'

to re%ister R6c- A"" the contents o! the &e&or# ocationwhose a""ress is at the &e&or# ocationNU' to re%ister R6


24/49

,dd the nu#'er /UM to register R)

6$ PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in=$ 8out1 PCin1 7in1 @'FC9$ 'DRout1 IRin:$ PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in$ 8out1 PCin1 7in$ R6out1 7in1 @'FC$ 'DRout1 Se ect71 A""1 8in$ 8out1 R6in1 En"


25/49

,dd the contents o! #e#ory location /UM to register R)

6$ PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in=$ 8out1 PCin1 7in1 @'FC9$ 'DRout1 IRin:$ PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in

$ 8out1 PCin1 @'FC$ 'DRout1 'ARin1 Rea"$ R6out1 7in1 @'FC$ 'DRout1 Se ect 71 A""1 8in$ 8out1 R6in1 En"


26/49

,dd the contents o! the #e#ory location whose address is at the #e#ory location/UM to register R)

6$ PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in=$ 8out1 PCin1 7in1 @'FC9$ 'DRout1 IRin:$ PCout1 'ARin1 Rea"1 Se ect:1 A""1 8in$ 8out1 PCin1 @'FC$ 'DRout1 'ARin1 Rea"1 @'FC$ 'DRout1 'ARin1 Rea"$ R6out1 7in1 @'FC$ 'DRout1 Se ect 71 A""1 8in

65$ 8out1 R6in1 En"


27/49

BR,/C I/.TRUCTI$/

Rep aces the contents o! PC with the*ranch tar%et a""ress$ Usua # o*taine" *# a""in% an o!!set 1

%i)en in the *ranch instruction1 to the

up"ate" )a ue o! PC$ O!!set is the "i!!erence *etween the*ranch tar%et a""ress an" the a""ressi&&e"iate # !o owin% the *ranch

instruction$ E$%$ i! *ranch instruction is at ocation =555 an"*ranch tar%et a""ress is =5 51 the )a ue o! o!!setis :


28/49

THE FETCH PHASE

6$ PCout1 'ARin 1 Rea"1 Se ect:1 A""1 8in=$ 8out1 PCin1 7in1 @'FC9$ 'DRout 1 IRin

END OF FETCH PHASEThe o!!set )a ue is extracte" !ro& the IR *#

the instruction "eco"in% circuit$:$ O!!set !ie " o! IRout1 Se ect 71 A""1 8in$ 8out1 PCin1 En"


29/49

@e nee" to chec. the status o! the con"ition co"es *e!ore

oa"in% a new a""ress into the PCFor exa&p e 1 !or a Branch on ne%ati)e ,Branch 5-

6$ PCout1 'ARin 1 Rea"1 Se ect:1 A""1 8in

=$ 8out1 PCin1 7in1 @'FC

9$ 'DRout 1 IRin:$ O!!set !ie " o! IRout1 Se ect 71 A""1 8in 1 I! NJ5 then En"

$ 8out1 PCin1 En"

Thus i! NJ51 the processor returns to step 6 i&&e"iate # a!ter

step :$ I! NJ61 step is per!or&e" to oa" a new )a ue intoPC1 thus per!or&in% the *ranch operation$

Conditional Branch .tate#ent


30/49

Multiple Bus $rganisation

Sin% e Bus s#ste&s ha)e;en%th# contro se0uences

On # one "ata ite& can *etrans!erre" at a ti&e So ution is to pro)i"e

&u tip e interna paths$


31/49

'emory 3usdata lines

0us ( 0us 0 0us C

!nstructiondecoder

PC

)egister file

Constant

(1U

'")

(

0)

' U /

!ncrementer

(ddresslines

'()

!)

Three Bus Organisation of the Datapath


32/49

A %enera purpose re%isters are co&*ine" into asin% e * oc. ca e" the register file which has 9 ports

Two o3p1 a owin% the contents o! two "i!!erent re%isters to*e accesse" si&u taneous # an" ha)e their contents p ace" on*uses A an" B

Thir" a ows the "ata on *us C to *e oa"e" on a thir" re%ister"urin% the sa&e c oc. c#c e$

Buses A an" B are use" to trans!er the source operan"sto A an" B I3p o! A;U$ The resu t is trans!erre" to the"estination o)er *us C$

The A;U can a so pass one o! the I3p unchan%e" to o3p

C *# usin% si%na s RJA or RJB$ No nee" !or the re%isters 7 an" 8$ Incre&enter unit a""s : to PC1 e i&inatin% the nee" to

"o so in A;U$


33/49

Exa#ple ,00 R(3 RD3 R

6$ PCout1 RJB1 'ARin 1 Rea"1 IncPC=$ @'FC9$ 'DRoutB1 RJB1 IRin:$ R:outA1 R outB1 Se ect A1 A""1 R in1 En"

$ Contents o! PC are passe" throu%h A;U an" oa"e"into 'AR to start a 'e&or# Rea"$ The PC is thenincre&ente" *# : an" the incre&ente" )a ue isoa"e" into PC$

$ The processor waits !or 'FC an" oa"s the "atarecei)e" into 'DR$ The contents o! 'DR are trans!erre" to IR$ Execution Phase


34/49

Control Unit

The 'asic tas% o! the control unit !or each instruction the contro unit causes the CPU to %o

throu%h a se0uence o! contro steps2 in each contro step the contro unit issues a set o! si%na s

which cause the correspon"in% &icrooperations to *e execute"$ The contro unit is "ri)en *# the processor c oc.$

The si%na s to *e %enerate" at a certain &o&ent "epen" on4 the actua step to *e execute"2 the con"ition an" status ! a%s o! the processor2 the actua instruction execute"2 externa si%na s recei)e" on the s#ste& *us ,e$%$ interrupt

si%na s-$


35/49


36/49

Control Unit 0esign

To execute instructions1 the processor&ust ha)e so&e &eans o! %eneratin%the contro si%na s nee"e" in properse0uence$

Techni0ues !or i&p e&entation o! thecontro unit4

Har"wire" contro 'icropro%ra&&e" contro


37/49

HARDWIREDCONTROL

UNIT


38/49

ardwired Control Units

In har"wire" contro units1 contro si%na s e&anate!ro& * oc.s o! "i%ita o%ic co&ponents$

These si%na s "irect a o! the "ata an" instructiontra!!ic to appropriate parts o! the s#ste&$

@e nee" a specia "i%ita circuit that uses1 as inputs1the *its !ro& the opco"e !ie " in our instructions1*its !ro& the ! a% ,or status- re%ister1 si%na s !ro&the *us1 an" si%na s !ro& the c oc.$ It shou "pro"uce1 as outputs1 the contro si%na s to "ri)e the

)arious co&ponents in the co&puter


39/49

A o! the contro ines are ph#sica # connecte" tothe actua &achine instructions$

The instructions are "i)i"e" up into !ie "s1 an""i!!erent *its in the instruction are co&*ine"throu%h )arious "i%ita o%ic co&ponents to "ri)e thecontro ines$

ardwired Control Units


40/49

Control UnitOrganisation


41/49


42/49

Hard ired Control Unit

The counter .eeps trac. o! the contro steps The re0uire" contro si%na s are "eter&ine"*# Contents o! contro step counter

Contents o! Instruction Re%ister Contents o! con"ition co"e ! a%s Externa input si%na s1 i.e 'FC an" interrupt

re0uests$


43/49

Separation of De!oding " En!oding #$n!tions


44/49


45/49

E%a&ple ' (in

Generation of signal Zin: first step of all instructions (fetch

instruction) step 6 of ADD with register

addressing step 4 of BR step 6 of ADD with register-

indirect addressing

Zin = ! " 6 ADD " 4 BR " # #


46/49

E%a&ple ' END

E/0 * T


47/49

Control H/ as a State )a!*ine

The contro h3w can *e )isua i(e" as astate &achine that chan%es !ro& onestate to another in e)er# c oc. c#c e"epen"in% on the contents o! the IR1the con"ition co"es an" the externaI3p$

The o3p o! the state &achine are thecontro si%na s$


48/49

+ros and Cons

The a")anta%e o! har"wire" contro is that it is )er#!ast$

The "isa")anta%e is that the instruction set an" thecontro o%ic are "irect # tie" to%ether *# speciacircuits that are co&p ex an" "i!!icu t to "esi%n or&o"i!#$

I! so&eone "esi%ns a har"wire" co&puter an" ater"eci"es to exten" the instruction set the ph#sicaco&ponents in the co&puter &ust *e chan%e"$

This is prohi*iti)e # expensi)e1 *ecause not on # &ust

new chips *e !a*ricate" *ut a so the o " ones &ust eocate" an" rep ace"$


49/49

Blo!, Diagra& of a !o&plete +ro!essor

#6 - Processing Unit Design

Documents