1 Analog to Digital Analog to Digital Conversion Conversion ADC Essentials ADC Essentials A/D Conversion Techniques A/D Conversion Techniques Interfacing the ADC to the IBM PC Interfacing the ADC to the IBM PC DAS (Data Acquisition Systems) DAS (Data Acquisition Systems) How to select and use an ADC How to select and use an ADC A low cost DAS for the IBM PC A low cost DAS for the IBM PC
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
1
Analog to Digital ConversionAnalog to Digital Conversion
cancelled out by integration Proper T1 eliminates line
noise Easy to obtain good
resolution Low Speed
If T1 = 60Hz, converter throughput rate < 30 samples/s
1
0
T
iv dt2
0
t
rV dt1 ( ) 2i AVG rT v t V
2( )
1i AVG r
tv V
T
Chap 0 18
Voltage to Frequency ADCVoltage to Frequency ADC
VFC (Voltage to Frequency Converter) Convert analog input
voltage to train of pulses Counter
Generates Digital output by counting pulses over a fixed interval of time
Low Speed Good Noise Immunity High resolution
For slow varying signal With long conversion
time Applicable to remote data
sensing in noisy environments Digital transmission
over a long distance
Chap 0 19
Parallel or Flash ADCParallel or Flash ADC
Very High speed conversion Up to 100MHz for 8 bit
resolution Video, Radar, Digital
Oscilloscope Single Step Conversion
2n –1 comparator Precision Resistive
Network Encoder
Resolution is limited Large number of
comparator in IC
Homework #5-1 어떻게 동시에 비교가
되는지를 설명하라 .
Chap 0 20
Software ImplementationSoftware Implementation
Implementation with software using microprocessor Counting Shifting Inverting Code Conversion …
Limited Practical Use Availability of Good
performance with very reasonable Cost
Chap 0 21
Shaft EncoderShaft Encoder Elctromechanical ADC
Convert shaft angle to digital output
Encoding Optical or Magnetic Sensor
Applications Machine tools, Industrial
robotics, Numerical control
Binary Encoder Misalignment of mechanism
causes large error Ex: 011 111 (180deg)
Gray Encoder Misalignment causes 1 LSB
error
Chap 0 22
Interfacing the ADC to the IBM PCInterfacing the ADC to the IBM PC
Interface Operations Most-recent-data Scheme
At end of conversion it updates an output FIFO
Automatically start new conversion
CPU read FIFO to acquire most recent data
Start-and-wait Scheme CPU initiate conversion
every time it needs new data
CPU check EOC until conversion is finished
Using CPU Interrupt CPU initiate conversion
every time it needs new data
CPU can proceed to do other thing
ADC interrupt CPU when conversion is complete
CPU goes to ISR
See Chapter 3, For more information about 8259A
Chap 0 23
Interface SoftwareInterface Software
Memory Mapped Transfers ADC is assigned in
Memory Space MRD, MWR signal MOV instruction
More complex decoding logic
I/O Mapped Transfers ADC is in I/O Space
IOR, IOW signal IN, OUT instruction
More Simple decoding logic
DMA (Direct Memory Access) CPU release system bus
by the request of DMA DMA controller carried out
data transfer by generating the required addresses and control signals
The system bus control reverts back to CPU when data transfer is finished
DMA is useful High Speed High volume data transfer
Disk Drive interface
Chap 0 24
Interface HardwareInterface Hardware
Parallel Data Format Three state output
buffer in ADC To Interface ADC
CPU + Decoding logic• To generate Chip
Select signal
• To generate Start Signal
• To Check EOC signal
Serial Data Format Asynchronous Serial
transmission to send data over long distance to a monitoring station
UART is commonly used
Interfacing 10 or 12 bit ADC Transfer data in chunks
of 8 bits one after another
Chap 0 25
DAS (Data Acquisition System)DAS (Data Acquisition System)
DAS performs the complete function of converting the raw outputs from one or more sensors into equivalent digital signals usable for further processing, control, or displaying applications
Applications Simple monitoring of a
single analog variable Control and Monitoring
of hundreds of parameters in a nuclear plant
Chap 0 26
Single Channel SystemSingle Channel System
Transducer Generate signal of low
amplitude, mixed with undesirable noise
Amplifier, Filters Amplify Remove noise Linearize
S/H (Sample and Hold) Reduce uncertainty error
in the converted output when input changes are fast compared to the conversion time
In Multi-channel system To hold a sample from
one channel while multiplexer proceed to sample next one
Simultaneous sampling of two signal
Chap 0 27
Sample and Hold CircuitsSample and Hold Circuits
Care in selecting hold capacitor Ch Low Value
Reduces acquisition time Increase Droop
High Value Minimize Droop Increase acquisition time
Choose capacitor to get a best acquisition time while keeping the droop per conversion below 1 LSB
Chap 0 28
Commercially Available S/HCommercially Available S/H
Chap 0 29
Multi-channel SystemMulti-channel System
Analog multiplexer and a ADC Low cost
Local ADCs and digital multiplexer Higher sampling rate
Chap 0 30
How to select and use an ADCHow to select and use an ADC
Range of commercially available ADCs
Guidelines for using ADCs Use the full input range
of the ADC Use a good source of
reference signal Look out for fast input
signal changes Keep analog and digital
grounds separate Minimize interference
and loading problem
Chap 0 31
Commercially available monolithic Commercially available monolithic ADCsADCs
Chap 0 32
Commercially available hybrid ADCsCommercially available hybrid ADCs
Chap 0 33
A low cost DAS for the IBM PCA low cost DAS for the IBM PC
Multi-channel system Less than $100 ADC0816 from
National Semiconductor
Constant, repetitive rate
1000 samples/s
Generating clock For starting ADC
conversion For causing interrupt Make a pulse stream
from TCLK with short pulses of duration = ½ x BCLK/4
TCLK from 8253 Timer/Counter
• Wide pulse
Chap 0 34
ADC circuit for ADC circuit for PC prototype PC prototype boardboard
SCSLCT(Start Conversion SeLeCT): Latched trough port 30CHSCSLCT = H Selection of 30AH (/E10) start conversionSCSLCT = L TCLK’ start conversion
INTSLCT(INTerrupt SeLeCT): Latched trough port 30CHINTSLCT = H EOC cause IRQ2INTSLCT = L No Interrupt CPU read Status register (Port 309H) to check EOC
Chap 0 35
Status RegisterStatus Register
For polling TCLK and EOC signal
Port 309H (/E9) Polling of EOC results
in a low level after the data from ADC have been read