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A 500-MHz Low-Voltage Programmable GainAmplifier for HD Video in 65-nm CMOS

Syed Ahmed Aamir and J Jacob WiknerDepartment of Electrical Engineering

Linkoping UniversitySE-581 83 Linkoping, Sweden

E-mails: [email protected], [email protected]

Abstract—This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD)video digitizers in a 65-nm digital CMOS process.

The “pseudo” switched-capacitor (SC) PGA architecturebuffers the video signal, without switching, during the activevideo. The SC circuitry is used for setup of DC operating pointduring horizontal and vertical blanking periods. Additionally,it compensates for the ’sync-tip’ of analog video signals to anequal blanking level for increased dynamic range to the digitizerfollowing the PGA.

The operational transconductance amplifier (OTA) employedas main amplifier in the PGA is a pseudo-differential, positive-feedback input stage architecture with a common-mode feedfor-ward (CMFF) technique. The common-mode feedback (CMFB)is provided once two OTAs are cascaded.

Schematic-level simulation results show that the OTA main-tains a −3-dB bandwidth of 550 MHz, while keeping thedistortion HD3 at –60 dB for a 30-MHz, 850 mVpp high definitionvideo signal. The 88 dB DC gain is distributed among fourOTA stages and the overall, combined PGA achieves a signal-to-noise ratio of 63 dB. Due to only two stacked transistors, itachieves high output swing of ±0.85 V, 1240 V/µs slew rate whileconsuming 10.4 mW power.

Index Terms—CMOS analog integrated circuits, switchedcapacitor circuits, programmable gain amplifiers, feedforwardamplifiers, operational amplifiers

I. INTRODUCTION

The rapidly growing trends of home entertainment video in-dustry has pushed the traditional video screens to deliver moredetailed, high resolution and sharper pictures. With the adventof high definition progressive scanning (e.g. HDTV 1080p),video technology is bounded by stringent specifications, andany design lapse is more ”visible” than ever. The video analogfrontends have faced its direct impact, which coupled withlower supplies and scaled sub-micron digital processes, makethe design more challenging.

A typical modern video analog front-end (AFE) receiverchain is outlined in Fig. 1 (digital parts omitted). An ACcoupled video signal which is multiplexed and selected froma set of different input sources (there could be many videosources connected to the same TV set) is buffered. Inside theAC capacitor there is no connection to ground, i.e., no leakage.The signal is possibly amplified or attenuated by the PGA toadjust the levels to fit the digitizing ADC range. The signalleakage is prevented or restored by a clamp circuit, ensuring

identical brightness levels across each horizontal line drawnon the screen.

Fig. 1. A video analog front-end (AFE) showing the interfacing circuits.

In this work we propose a programmable gain amplifier(PGA) for such high definition video analog front-ends. Wehave aimed the integration of AFE in a system-on-chip (SOC)environment and have therefore explored a low-voltage imple-mentation in a 65-nm digital CMOS process.

Notice that the high-definition video and graphics stan-dards have a high signal bandwidth. Signal frequencies upto 30 MHz must be multiplexed, buffered and digitized withhigh linearity maintained throughout the AFE. To preventother types of artifacts from appearing on the high-resolutionpicture screen, a bandwidth up to 20 times higher is required.For the high-resolution graphics formats the bandwidth needsto be beyond 500 MHz. This type of bandwidth puts highrequirements on the open-loop unity-gain bandwidth of thePGA. These specifications are considerably more challengingcompared to previously reported video PGAs such as [1].

An example of an analog video signal waveform is shownin Fig. 2. The active video region contains the vital pictureinformation, whereas the blanking intervals synchronize dur-ing the minimal black-time between successive frames andhorizontal lines. The blanking period typically contains a−40 IRE sync-tip, followed by a color burst (dependent on

978-1-4244-8971-8/10$26.00 c©2010 IEEE

video formats) which provide amplitude, phase reference foreach color. Traditionally, the clamping occurs during the back-porch duration.

Fig. 2. A typical analog video waveform.

In Section II we outline the PGA architecture and itsimplementation for a video digitizing AFE to be used in SOCs.In Section III the low-voltage OTA architecture is presentedand discussed. Simulation results are given in Section IV andfinally the paper is concluded in Section V.

II. PROPOSED VIDEO PGA CIRCUIT

The proposed video programmable gain amplifier (PGA)is realized as a fully-differential, ”pseudo” switched-capacitor(SC) circuit that gets the multiplexed, clamped and band-limited video signal from the first parts of the AFE.

One has to consider a couple of points before outlining avideo PGA using an SC technique, mainly:

• The circuit must not switch during the active videoduration of the analog video signal, to preserve a highersignal linearity.

• In order to increase the signal dynamic range, the PGAcompensates for the sync-tip of analog video waveform,presenting the ADC a sync-tip free signal.

A. ”Pseudo” SC Circuit with Sync-Tip Compensation

With the above considerations, we propose an SC architec-ture where charge is transferred between the nodes during thesync-tip duration only, which means the non-overlapping clockgenerator does not function beyond the sync-tip duration. Inthe absence of a sync-tip, i.e., during active video, the PGAacts like a capacitive buffer.

Additionally, we exploit the fact, that most often the realinput video signal is single ended, and the second input of thePGA is referenced from an on-chip, programmable digital-to-analog converter (DAC). We utilize this reference DAC voltageto level-shift the sync-tip duration of video signal, effectivelycanceling the sync-tip, and obtaining a clean output signal.

The resulting SC architecture is shown in Fig. 3. Noticethat the first two switches triggered by presence or absenceof sync-tip, provide separate reference DC levels Vsync andVCM . Vsync is then the sync-tip voltage level (≈ −0.3 Vor −40 IRE) and VCM is the input common-mode level.This level is maintained in accordance with the input signalbrightness.

Fig. 3. The proposed video PGA including DC conditioning SC input.

B. Gain Settings

The gain settings are achieved by means of capacitorratios, and for the input video signals we have provided twogain settings: 0.5 and 1. Capacitor Cin is then changed toaccomplish this programmable gain.

It should be mentioned that some lower voltage swing videoformats may require higher gain settings (2 times) to enable amore efficient utilization of the ADC. However, this increasesthe capacitive load on the PGA and the signal, thus decreasingthe system bandwidth. Such video formats, however, havebandwidth requirements much lower than 500 MHz too, andwould not really suffer from the impact of lower bandwidth.

The next section describes a four-stage, low-voltage pseudo-differential OTA architecture that is used in the PGA circuit.

III. PSEUDO-DIFFERENTIAL OTA ARCHITECTURE

Various designs of low-voltage OTAs have been proposed inthe literature, including for example [2]–[4]. We have exploreda pseudo-differential design, which eliminates the tail currentsource in the input differential pair and becomes particularlysuited for low voltage design. One pseudo-differential OTAwith a CMFF strategy is presented in [5]–[7]. These designswere originally implemented in a 0.5-μm CMOS process andfor higher supply voltage. We wanted to explore the design ina more modern SOC environment such as a 65-nm process.However, porting of the originally proposed architecture toa (relatively) much smaller dimension does have problems.These problems are foremost due to the low-gain devicesavailable among the core devices in an SOC process.

Thus the PGA in our work is realized using a modified OTAarchitecture, which has a positive feedback pseudo-differentialinput stage for higher gain, but additionally for achieving thehigher targeted video bandwidth, linearity, etc. The pseudo-differential OTA architecture with its inherent common-modefeedforward also provides efficient common-mode feedback(CMFB), when a similar OTA is cascaded! This saves usan additional CMFB block as proposed in [5] and shown inFig. 4. The second stage OTA provides the first stage witha common-mode feedback signal. Instead of using a separate

transconductance for common-mode detection as in [8], [9],the OTA utilizes the differential transconductance to detect theinput common-mode level too.

Fig. 4. The cascaded OTA blocks to provide CMFB.

The positive-feedback OTA with its CMFF is shownin Fig. 5. The individual input stage currents are furthercopied using a differential transconductance to detect thecommon-mode component in the OTA node Vcm. The detectedcommon-mode current, (I1 + I2)/2, is then subtracted atthe output performing the feedforward cancellation. Due tosimilar differential-mode and common-mode signal paths thebandwidths for both loops can be made fairly identical.

Fig. 5. The positive feedback pseudo-differential OTA with inherentcommon-mode feedforward.

A. OTA Parameters

To further describe the OTA design, some of the importantdesign parameters are presented in this section. The DC gainADC of the positive feedback input stage OTA is:

ADC =gm1gm4

(gm5 − (gm2 + gds1 + gds2 + gds5))(gds3 + gds4),

≈ gm1gm4

(gm5 − gm2)(gds3 + gds4),

where gmi is the transconductance of transistor Mi and gdsiis the output conductance (or channel length modulation) oftransistor Mi.

The two most dominant poles found in the OTA stage aregiven by

ωp1 =gm5 − (gds1 + gds2 + gds5 + gm2)

Cz,

and

ωp2 =gds3 + gds4

CL,

where Cz is the parasitic capacitance at the output of the inputdifferential pair (also illustrated in Fig. 5) and CL is the loadcapacitance at output node creating the most dominant pole.

B. CMFB Detection

As mentioned above, the common-mode component is ex-tracted in the Vcm node of the OTA (see Fig. 5). In a multi-stage OTA configuration, this Vcm voltage inside any OTA isthe sensed output common-mode level of the preceding OTA.Exploiting this property, one can provide CMFB as long asat least two OTAs are used in the chain (see Fig. 4). Thefirst OTA adds an additional set of devices in parallel to thebiasing PMOS of the output stage, which are controlled by thefed back Vcm, and shown in Fig. 6 as VcmNext. A common-mode reference current is further mirrored in the output stage,which then adjusts output DC point to its optimum level bycomparing the currents.

Fig. 6. One half of the pseudo-differential architecture with CMFF andCMFB.

C. Nonlinearity

Since the pseudo-differential input pairs remove the tailcurrent source, the amplifier will be more sensitive towardsmismatch variations. This implies that the second-order har-monic distortion (HD2) will be larger than for a differentialinput pair with tail current source. Cross coupling betweendifferential signal and any common-mode interferer also con-tributes to HD2 components. HD3 is contributed by shortchannel effects, as well as due to non-linear interaction ofdifferential OTA outputs and CMFB. A more detailed analysisof sources of non-linearity in pseudo-differential designs ispresented in [7].

D. Noise and SNR

Considering only transistor thermal noise, the input referrednoise power density, Pn = V 2

n−rms, of the positive feedbackOTA architecture (omitting the common-mode noise contrib-utors M6, M7, see Fig. 5) becomes:

16kT ·BW

3gm1·[1 +

E

gm2gm1+

2gm3E + 2gm4E + gm5E

gm1g2m4

],

where BW is the equivalent noise bandwidth. E is a factorgiven by E = (gm2 − gm5)

2 and once E ≈ 0, i.e., thetransconductance of the mirror transistors is approximatelyequal to that of positive feedback transistors, the signal-to-noise ratio (SNR) at the input becomes:

SNR ≈ 10 · log10[3gm1HD3Veff (1 + θ Veff )

2(2 + θ Veff )

2kT ·BW]

It can be noted that the positive feedback architecture clearlyachieves a better SNR than the one derived originally in [7].

IV. SIMULATION RESULTS

Table I compiles the simulation results for the PGA/OTAand in Table II the results are compared to other reportedresults.

In Fig. 7 we show the simulated transient response for anactive video line. The upper graph shows the input signalwith embedded sync-tip. The lower graph shows the PGAoutput where the sync-tip can be removed by the SC circuitryduring horizontal blanking. The oscillations we see during theblanking interval are given by the SC clock phases.

Parameter Value Parameter Value

Supply voltage 1.2 V DC gain 88 dBProcess node 65 nm f3dB 550 MHzPhase margin 45◦ HD2 –118 dBSlew rate 1240 V/µs HD3 –60 dBOutput swing 850 mVpp SNR 63 dBPower 10.4 mW

TABLE ISIMULATION RESULTS OF MODIFIED OTA.

0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0time (us)

750.0

500.0

250.0

0

−250.0

V (

mV

)V

(m

V)

5 0 0

2 5 0

0

−250

−500

V (

mV

)V

(m

V)

videoSignal

vOutDiff

Sync TipSync TipSync TipSync TipSync Tip

time (us)

Fig. 7. An input video signal and its corresponding sync-tip compensatedoutput, for a unity gain PGA setting.

Parameter [10] [11] [12] This workProcess (nm) 90 350 90 65Supply (V) 1.2 1.8 2.5 1.2DC gain (dB) 40 12 45 88*f3dB (MHz) 240 400 500 550Input Referred Noise 4.6 15 5.7 12.6(nV/

√Hz) @40 dB @0 dB @88 dB

THD −30 −40 - −60HD3 (dB) @80 MHz @0.8Vpp @30 MHzPower (mW) 3.48 2.1 32.5 10.4

TABLE IICOMPARISON OF RECENT PGAS (* OPEN-LOOP GAIN).

V. CONCLUSION

We have described a programmable gain amplifier archi-tecture for high definition video standards that provides sync-tip compensation using SC techniques. We maintained a low-voltage implementation in a modern short channel process toattain the challenging specifications of targeted video stan-dards. The novel pseudo-differential multi-stage OTA archi-tecture with CMFB was enhanced to provide higher gain andbandwidth, wider output swing and low distortion, to processthe video signals for best visual performance.

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