56+ Gb/s Serial Transmission using Duobinary Signaling
56+ Gb/s Serial Transmission
using Duobinary Signaling
Jan De Geest Senior Staff R&D Signal Integrity Engineer, FCI
Timothy De Keulenaer Doctoral Researcher, Ghent University, INTEC-IMEC
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Introduction
Motivation
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Standard groups looking into serial data rates of 50 Gb/s and above
IEEE 802.3bs 400 GbE
NRZ and PAM4
OIF CEI-56G-VSR/SR (< 100 mm)
NRZ and PAM4
OIF CEI-56G-MR (500 mm)
PAM4
Duobinary signaling presented as alternative for 56+ Gb/s serial data rates
Overview
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Duobinary signaling
Duobinary demonstrator
Design of duobinary chipset
Measurements
Conclusions
Duobinary Signaling
Duobinary Signaling
NRZ signaling
Requires extensive pre-emphasis or equalization
Difficult to scale to data rates beyond 40 Gb/s
PAM4 signaling Reduces spectral requirements compared to NRZ
Requires less pre-emphasis and equalization than NRZ
More complex – multi-level transmitter and receiver
Reduced level spacing – less tolerance to noise
Duobinary signaling 3-level modulation scheme
Leverages passive channel frequency response for signal shaping
Reduces spectral requirements compared to NRZ
Requires less pre-emphasis and equalization than NRZ
2T
A/3
T A/2
A T
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Duobinary Signaling
Duobinary transmission system: Data source (binary data transmitter)
Duobinary precoder
Feed-forward equalizer (FIR filter)
Passive channel (backplane)
Duobinary to binary converter (rectifier)
Binary data receiver
Equalization effort reduced Main shaping takes place in the channel
Duobinary spectrum has null at ½ data rate
FIR filter limited to 5-taps
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Emphasize high-frequency components
Flatten group delay response
Duobinary Signaling
Duobinary – correlative coding Each symbol conveys information corresponding to
the previous and current bit – partial response
Combination results in 3 level waveform
Forbidden transitions form rudimentary error
detection – not considered here
Requires simple precoding at transmitter
Duobinary PSD Spectrum compressed compared to NRZ
Same spectrum as PAM4
Relaxes channel design criteria and bandwidth
requirements of transceiver IC’s
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Duobinary Demonstrator
Duobinary Demonstrator
56 Gb/s PPG
TX board
FFE
Scope/BERT
RX board
56 Gb/s 56 Gb/s 14 Gb/s
CHANNEL
TX
28 GHz clock
RX
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
56 Gb/s PPG
TX board
FFE
Scope/BERT
RX board
56 Gb/s 56 Gb/s 14 Gb/s
TX
28 GHz clock
RX
Duobinary Demonstrator – Backplane Channel
CHANNEL
18
Figure 18: ExaMAX® backplane demonstrator.
Figure 19: Losses 13.7 in backplane channel only (red) and total losses of backplane
channel + test setup (blue).
• ExaMAX® connector system
• 24 lay – 160 mil backpanel
• 18 lay – 94 mil daughter cards
• Megtron 6 board material
• Daughter card trace length = 6”
• Backpanel trace length = 1.7” to 26.75”
• Total length = 13.7” to 38.75”
• 1.3 dB loss per inch at 28 GHz
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
18
Figure 18: ExaMAX® backplane demonstrator.
Figure 19: Losses 13.7 in backplane channel only (red) and total losses of backplane
channel + test setup (blue).
Duobinary Demonstrator – Backplane Channel
-29.5 dB
-35.5 dB -37.0 dB
-45.0 dB
56 Gb/s PPG
TX board
FFE
Scope/BERT
RX board
56 Gb/s 56 Gb/s 14 Gb/s
CHANNEL
TX
28 GHz clock
RX
TX board
FFE TX
RX board
RX
Duobinary Demonstrator – Loss
1.05 dB at 28 GHz 1.05 dB at 28 GHz
5.6 dB at 28 GHz
3.8 dB at 28 GHz
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Duobinary Demonstrator – Total Channel Loss
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
COMPONENT LOSS at 28 GHz
TX board 5.60 dB
Coax TX board to channel 1.05 dB
Channel loss IL [dB]
Coax channel to RX board 1.05 dB
RX board 3.80 dB
Total loss IL + 11.5 dB
Chip Design
Chip Design – Overview
Transceiver chain
Transmitter overview
Receiver overview
FFE parameter optimization
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Transceiver Chain
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Transmitter Building Blocks
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Transmitter Building Blocks
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Transmitter Building Blocks
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Transmitter Building Blocks
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Transmitter Building Blocks
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Transmitter Building Blocks
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Transmitter Building Blocks
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Receiver Overview
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
FFE Parameter Estimation
Channel delays, attenuates and
reduces the bandwidth of the impulse
response
FFE impulse response
calculated from
frequency response
FFE impulse response
after channel propagation
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Generating Least-square-error Fit
11
impulse response and the taps or by multiplying them in the frequency-domain and
recalculating the impulse responses.
Using the measured impulse responses, a least-square-error (LSE) fit to the idealized
duobinary response is done. The idealized response consists of two bit-spaced narrow
sinc pulses. The LSE fit matches the 5 normalized FFE parameters as well as the optimal
timing. In this way, it selects the optimal number of pre- and post-cursors in the FFE. The
result of such a fit is shown in figure 8.
Figure 8: Fitting the FFE output to the ideal duobinary response.
It is clear that the FFE is capable of matching the main cursors of the duobinary channel.
There is some remaining error which will result in extra inter symbol interference, which
is evident from the eye-diagram of figure 9.
Figure 9: Simulated eye-diagram of the ideal (left) and fitted (right) duobinary signal.
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Making a linear combination to obtain the best match
1-tap FFE Parameters 56 Gb/s NRZ 56 Gb/s Duobinary 56 Gb/s PAM4
Impulse response
desired - obtained
Obtained eye pattern normalized at output of FFE
Desired eye pattern normalized
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
2-tap FFE Parameters
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
56 Gb/s NRZ 56 Gb/s Duobinary 56 Gb/s PAM4
Impulse response
desired - obtained
Obtained eye pattern normalized at output of FFE
Desired eye pattern normalized
3-tap FFE Parameters
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
56 Gb/s NRZ 56 Gb/s Duobinary 56 Gb/s PAM4
Impulse response
desired - obtained
Obtained eye pattern normalized at output of FFE
Desired eye pattern normalized
4-tap FFE Parameters
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
56 Gb/s NRZ 56 Gb/s Duobinary 56 Gb/s PAM4
Impulse response
desired - obtained
Obtained eye pattern normalized at output of FFE
Desired eye pattern normalized
5-tap FFE Parameters
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
56 Gb/s NRZ 56 Gb/s Duobinary 56 Gb/s PAM4
Impulse response
desired - obtained
Obtained eye pattern normalized at output of FFE
Desired eye pattern normalized
Chip Design – Conclusions
Design of a 5-tap FFE capable of equalizing a backplane channel into a 56 Gb/s duobinary
channel
Design of a sensitive 56 Gb/s duobinary receiver with built-in DEMUX
Optimized FFE parameters estimation methodology based on fast frequency-domain
measurements and Matlab optimization techniques
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Measurements
Measurements – Overview
Test setup
40 Gb/s BER vs. insertion loss
56 Gb/s BER measurements
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Test Setup
56 Gb/s PPG
TX board
FFE
Scope/BERT
RX board
56 Gb/s 56 Gb/s 14 Gb/s
CHANNEL
TX
28 GHz clock
RX
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
BER Measurement Results – 40 Gb/s
40 Gb/s – 13.7” 40 Gb/s – 26.25”
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
28.0 dB at 20 GHz
BER < 1E-12
41.3 dB at 20 GHz
BER ≈ 1E-9
40 Gb/s transmission across channels ranging from 13.7” to 26.25”
BER Measurement Results – 40 Gb/s
19
Measurements started at 40 Gb/s on the shortest link (13.7 in, 35 cm). The loss at the
Nyquist frequency is 28.8 dB, resulting in a vertical and a horizontal eye-opening of 18.2
mV and 15 ps (0.6 UI) respectively, compared to the maximum output eye-pattern at the
transmitter having an eye-opening of 93.4 mV and 19.1 ps (0.76 UI) at 40 Gb/s. Both
eye-patterns are shown in figure 20. This results in error-free (BER < 1E-12)
transmission when connected to the duobinary decoder.
Figure 20: 40 Gb/s output eye-pattern at the transmitter (left) and after a 13.7 in
backplane channel (right).
Figure 21: Chart showing the BER (blue) and the vertical eye-opening (red) as a function
of the loss at the Nyquist frequency for a 40 Gb/s signal measured across the ExaMAX®
backplane.
In figure 21 it is shown that a total loss (backplane + test setup) at the Nyquist frequency
of up to 36.8 dB can be received error-free (BER < 1E-12), and up to 41.4 dB with a BER
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Error-free (BER < 1E-12) up to
about 37 dB total link loss (20”
channel + test setup) at Nyquist
(20 GHz)
BER ≈ 1E-9 up to about 42 dB
total link loss (26.25” channel +
test setup) at Nyquist (20 GHz)
BER Measurement Results – 56 Gb/s
20
below 5E-9, which is considered OK for a link with FEC in the current 25 Gb/s IEEE
802.3bj standard. The 36.8 dB loss corresponds to a total channel length of 22 in, while
the 41.4 dB loss corresponds to a total channel length of 27 in. At 36.8 dB and 41.4 dB
the vertical eye-opening are 11 mV and 5 mV respectively, as shown in figure 22.
Figure 22: Eye-diagrams of the 40 Gb/s duobinary signal across a 22 in (left) and a 27 in
(right) backplane channel.
Moving towards higher speeds leads to more frequency-dependent loss. At 50 Gb/s the
signal after a 13.7 in backplane channel was still received error-free (BER < 1E-12), with
an eye-opening of 6.8 mV as shown on the left in figure 23.
By increasing the speed to 56 Gb/s the loss at the Nyquist frequency increases further,
and the vertical eye-opening at the input of the receiver decreases to about 6 mV as
shown on the right in figure 23. The BER obtained at 56 Gb/s is better than 5E-9, which
is more than sufficient assuming FEC is applied.
Figure 23: Eye-diagrams of the 50 Gb/s (left) and 56 Gb/s (right) signal after a 13.7 in
backplane channel.
4.3 Design of active daughter cards
The performance of the transceiver chipset is limited by the total amount of losses that
can be compensated for by the FFE. In the sections above we have shown that a total of
11.5 dB of losses at 28 GHz are added by the measurement setup. These losses are caused
by the TX and RX test boards and by the coax cables needed to connect the different
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
56 Gb/s – 13.7”
41.0 dB at 28 GHz
BER < 1E-12
Error-free (BER < 1E-12) operation at 56 Gb/s across 13.7” channel with a total link loss of
about 41 dB at 28 GHz
Conclusions
Conclusions
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Selection of duobinary signaling as a modulation format for high-speed serial transmission
Duobinary demonstrator
Design of duobinary transceiver chipset
Measurement results demonstrate 56 Gb/s serial transmission over a state-of-the-art
backplane channel is possible using duobinary signaling Limited equalization: 5-taps FFE, no CTLE or DFE
10-TH3 – 56+ Gb/s Serial Transmission using Duobinary Signaling
Visit us at booth 817 for a live demo