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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012 1159

Three-Phase Dual-Buck Inverter With UnifiedPulsewidth Modulation

Pengwei Sun, Student Member, IEEE, Chuang Liu, Student Member, IEEE, Jih-Sheng Lai, Fellow, IEEE,Chien-Liang Chen, Member, IEEE, and Nathan Kees, Student Member, IEEE

Abstract—This paper presents a new type of three-phase voltagesource inverter (VSI), called three-phase dual-buck inverter. Theproposed inverter does not need dead time, and thus avoids theshoot-through problems of traditional VSIs, and leads to greatlyenhanced system reliability. Though it is still a hard-switching in-verter, the topology allows the use of power MOSFETs as the activedevices instead of IGBTs typically employed by traditional hard-switching VSIs. As a result, the inverter has the benefit of lowerswitching loss, and it can be designed at higher switching frequencyto reduce current ripple and the size of passive components. A uni-fied pulsewidth modulation (PWM) is introduced to reduce com-putational burden in real-time implementation. Different PWMmethods were applied to a three-phase dual-buck inverter, includ-ing sinusoidal PWM (SPWM), space vector PWM (SVPWM) anddiscontinuous space vector PWM (DSVPWM). A 2.5 kW proto-type of a three-phase dual-buck inverter and its control systemhas been designed and tested under different dc bus voltage andmodulation index conditions to verify the feasibility of the circuit,the effectiveness of the controller, and to compare the features ofdifferent PWMs. Efficiency measurement of different PWMs hasbeen conducted, and the inverter sees peak efficiency of 98.8% withDSVPWM.

Index Terms—Dual-buck inverter, three-phase inverter, unifiedPWM, voltage source inverter.

I. INTRODUCTION

THE widely used standard three-phase voltage source in-verter (VSI) has two active switches in one phase leg that

present some common problems. First, dead time is needed be-tween the two active switches of the same phase leg, whichreduces the equivalent pulsewidth-modulated voltage, and leadsto output waveform distortions and less energy transfer. Second,even with dead time, shoot-through is still the major killer ofVSIs, especially at some fault conditions. Third, people cannotsimply employ power MOSFETs because of the reverse recov-ery problems of the body diode [1]–[5]. In order to obtain thebenefits of using MOSFETs, such as low switching loss, re-sistive conduction voltage drop, and fast switching speed thatallows reduction of current ripple and the size of passive com-ponents, conventional approaches adopt soft-switching tech-

Manuscript received April 26, 2010; revised June 29, 2011; accepted July 30,2011. Date of current version February 7, 2012. Recommended for publicationby Associate Editor J. Clare.

P. Sun, J.-S. Lai, C.-L. Chen, and N. Kees are with Virginia PolytechnicInstitute and State University (Virginia Tech), Blacksburg, VA 24060 USA (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

C. Liu is with the Harbin Institute of Technology, Harbin 150001, China(e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2011.2164269

Fig. 1. Proposed three-phase dual buck VSI with MOSFETs.

niques [6]–[9]. However, soft-switching inverters require ad-ditional auxiliary switches, passive components, and more gatedriving circuits, which reduces reliability and increases systemcost and complexity.

This paper proposes a three-phase dual-buck inverter, shownin Fig. 1. It is hard-switching-based, but it can incorporatepower MOSFETs as the active switches. The device countis the same as that of the standard three-phase VSI usinginsulated-gate-bipolar-junction-transistors (IGBTs). The idea ofa three-phase dual-buck inverter originated from single-phasehalf-bridge and full-bridge dual-buck inverters [10]–[12]. Itdoes not need dead time and has no shoot-through concerns.Because the body diode of the MOSFET never conducts, itcan be hard-switched. The free-wheeling diodes can be chosenindependently with fast reverse recovery features to minimizeswitching loss. Compared to single-phase dual-buck inverter,the three-phase counterpart does not have double-fundamental-frequency ripple on the dc bus, and can be modulated with dis-continuous space vector PWM (DSVPWM) to further reducethe switching losses and fully utilize the dc bus voltage.

In order to modulate the three-phase dual-buck inverter, aunified pulsewidth modulation is adopted [13]–[16]. Comparedto traditional space vector PWM (SVPWM) sector calcula-tions [17]–[19], this method has much less computational bur-den when implemented by a digital signal processor (DSP). Dueto the unique operation principle of the three-phase dual-buck in-verter, the unified PWM is modified to use the current referenceto generate the required gate signals. Different PWM methodscan be considered as special cases of the unified PWM tech-nique, including sinusoidal PWM (SPWM), space vector PWM(SVPWM), and discontinuous space vector PWM (DSVPWM).

This paper first presents the basic operation principle ofthe proposed inverter. Second, it analyzes the specific uni-fied PWM technique applied to the three-phase dual-buck in-verter. Third, it introduces the closed-loop controller design with

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1160 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012

Fig. 2. Relation between phase current and conducting devices.

proportional-resonant (PR) and admittance-compensation con-trollers. Finally, it shows a 2.5-kW hardware prototype and thetest results under different dc bus voltage and duty cycle condi-tions to compare SPWM, SVPWM, and DSVPWM. Efficiencyof different cases was measured and compared. The DSVPWM-controlled three-phase dual-buck VSI with MOSFETs allows anefficiency of 98.8%.

II. TOPOLOGY AND OPERATION PRINCIPLE

The proposed three-phase dual-buck inverter has been shownin Fig. 1. Though it is a VSI, the PWMs for the active switchesare determined by the phase output current. Fig. 2 shows therelation between the polarity of phase current and the operationof switches. Take phase A, for example, when iA is positive, S1and D4 are the conducting devices and when iA is negative, S4and D1 are the conducting devices. The same operation principleapplies to phases B and C.

Fig. 3 shows the four switching states for phase A. It canclearly be seen that the body diodes of S1 and S4 never havethe opportunity to conduct, which ensures the safe switching ofpower MOSFETs.

Since there is only one active switch per leg, shoot-through isno longer possible. Therefore, the reliability of the three-phasedual-buck inverter is much higher than with traditional VSIs. Nodead time is needed because when S1 operates, S4 is always OFFand vice versa. The output waveforms are more sinusoidal and

Fig. 3. Four switching states for phase A. (a) S1 on, iA > 0. (b) D4 on, iA >0. (c) S4 on, iA <0. (d) D1 on, iA < 0.

the energy is transferred more completely without the dead-timeeffect.

Because the power MOSFET and diode can be selected in-dependently, the system efficiency can be further improved.To minimize conduction loss, it is better to choose a powerMOSFET with smaller on-resistance and a power diode withsmaller forward voltage. To optimize the switching loss, a diodewith fast reverse recovery capability is preferred.

III. UNIFIED PWM ANALYSIS

Even though MOSFETs are used for the three-phase dual-buck inverter to cut down switching losses, it is still a hard-switching VSI. Therefore, it is better to further reduce theswitching loss by incorporating DSVPWM. At the same time,the dc bus voltage can be fully utilized by adopting SVPWMor DSVPWM rather than SPWM. Traditionally, the SVPWMmethods [17]–[19] need to do trigonometric calculation andperform recombination of actual gating times, which is unfa-vorable for real-time implementation by a digital signal proces-sor. Thanks to unified PWM methods [13]–[16], SVPWM andDSVPWM can be equivalently generated using triangle carriercomparison like SPWM, which greatly reduces computationalburden and is very easy to implement by DSP.

Fig. 4 shows the unified PWM generation block diagram. Theswitch to which PWM is applied is selected based on the currentreference polarity. The phase duty cycles da , db , and dc areprovided by a closed-loop controller, which will be discussedin Section IV. The injected zero sequence duty cycle dzs isgenerated by the following equation [13]

dzs = − [(1 − 2k0) + k0 · dmax + (1 − k0) · dmin ] (1)

where dmax = max(da , db , dc)and dmin = min(da , db , dc).

SUN et al.: THREE-PHASE DUAL-BUCK INVERTER WITH UNIFIED PULSEWIDTH MODULATION 1161

Fig. 4. Unified PWM generation block diagram.

k0 is the PWM determination factor. Under this unified PWMscheme, when k0 = 0.5, the output PWM is SVPWM; when k0follows the relation in (2), the output PWM is DSVPWM withnonswitching state at phase current 60◦ peak region.

k0 = 1 J > 0

k0 = 0 J < 0

J = max(iaref , ibref , icref ) + min(iaref , ibref , icref ). (2)

Fig. 5 shows the simulation results of PWM generation usingthe unified PWM scheme with phase duty cycles da = db = dc

= 0.9: (a) is SPWM with dzs = 0; (b) shows the SVPWM whenk0 = 0.5; (c) shows the DSVPWM when k0 follows (2). ForSPWM, the maximum phase duty cycle is 1; but, after injectingdzs , SVPWM and DSVPWM can boost the phase duty cycleup to 1.15, which means 15% more dc bus voltage utilizationgain. From Fig. 5, it is clear that in terms of switching loss,SPWM is almost the same as SVPWM. In contrast, DSVPWMcan further decrease switching loss because each phase does notswitch for a 60◦ interval when its absolute phase current is thelargest among the three phase currents. In addition, from (1) and(2), it is clear that the calculation burden required to implementthis unified PWM is very small.

IV. CLOSED-LOOP SYSTEM DESIGN

In order to demonstrate the feasibility and advantages of thethree-phase dual-buck inverter, the closed-loop control is de-rived and designed for a three-phase standalone system.

Fig. 6 shows the average model of three-phase dual-buckinverter. dj (j = a, b, c) is the phase duty cycle, Lf and Cf arethe filter inductor and capacitor, and Lj is the output inductor ofeach phase.

Lj = Lp ij > 0

Lj = Ln ij < 0. (3)

Fig. 5. Unified PWM simulation results. (a) SPWM. (b) SVPWM.(c) DSVPWM.

1162 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012

Fig. 6. Average model of three-phase dual-buck inverter.

Define L = Lj + Lf , and the following equation can be ob-tained from Fig. 6

dj (t) ·Vdc

2− vj (t) = L

dij (t)dt

. (4)

Transform (4) to s domain

ij (s) =1sL

(dj (s) ·

Vdc

2− vj (s)

). (5)

So the transfer functions from duty cycle dj to current ij andvoltage vj to current ij are as follows:

Gid(s) =ij (s)dj (s)

=Vdc/2sL

(6)

Giv (s) =ij (s)vj (s)

=1sL

(7)

where Gid (s) is the control-to-output transfer function and Giv (s)is an uncontrolled feed-forward term.

Fig. 7 shows the control block diagram of the three-phasedual-buck inverter operating at standalone mode. The controladopts the natural frame in a-b-c coordinates without the burdenof transformation back and forth into rotational d-q coordinatesfor the digital signal processor [20]. Therefore, the control de-sign needs high controller gain at the fundamental frequency.The closed-loop design adopts a two-loop concept, the inner cur-rent loop with a PI controller, GPI(s), to achieve fast dynamicresponse and enough damping and the outer voltage loop with aPR controller, GPR (s), to ensure a higher loop gain at the funda-mental frequency [20]–[23]. In addition, the closed-loop controlutilizes an admittance compensation controller, GAC (s). By in-troducing the admittance compensation controller, GAC (s), theundesirable term, Giv (s), can be cancelled out, smoothing zero-current start-up and reducing current steady-state error [24],[25].

The PR controller transfer function can be represented asfollows:

GPR(s) = kp +2ωckrs

s2 + 2ωcs + ω21. (8)

For a 2.5 kW, 208VAC output inverter system, the followingparameters are obtained through frequency domain design: kp =0.02, kr = 12, ωc = 10. The current loop controller is a simpleP-controller; its design result is shown in (9). The admittanceloop gain is shown in (10).

GPI(s) = 0.05 (9)

GAC(s) =1

Vdc/2. (10)

GLPF (s) is second order low pass filter with cut-off frequency5 kHz and a damping ratio 0.7.

After obtaining phase duty cycles dj from Fig. 7, the unifiedPWM scheme shown in Fig. 4 can be used to generate the de-sired PWM to drive all the active switches. It is true that therewill be some difference between the reference current and thereal current around the zero-crossing, especially under transientconditions. In the prototype discussed here, the current sensoris simply used to feedback the real current information. It is notspecifically designed to track the zero-crossing. Therefore, theauthors believe that it is better to use the reference as the PWMcontrol signal because it has more immunity to noise, and doesnot have the current ripple problems of the real current. Exper-imental tests have been conducted using the reference signal,which proved to be no problem for the control performance. Onthe other hand, if the real current polarity information can beaccurately sensed and determined near the zero-crossing point,it might be better to use that information to generate the PWM.In [26], a real current polarity detection circuit and algorithmare provided, and these could be adopted in the proposed topol-ogy. Of course, this will increase the complexity of the sensingcircuit and require more of the computational capacity of thedigital controller.

V. EXPERIMENTAL RESULTS

To prove the viability and merits of the proposed three-phasedual-buck inverter and evaluate the unified PWM scheme, a2.5 kW, 208VAC output inverter system in standalone operationwas designed and tested. The switching frequency is 20 kHz. Allthe devices are rated at 600 V. The MOSFET is STY80NM60Nwith on-resistance 35 mΩ, and the diode is RURG3060 with re-verse recovery time 55 ns. The passive components are selectedas follows: Lp = Ln = 250 μH, Lf = 1 mH, Cf = 2.4 μF. Theobtained cut-off frequency with the filters is 2.9 kHz. The loadis variable resistive load bank.

The design rules for Lp (Ln ) are provided below:Rule No. 1: For standalone and grid-tie applications, Lp (Ln )

can be designed based on the same rule that a conventionalthree-phase VSI follows. In this case, Lp (Ln ) serves as the filterLf . It can be chosen based on the ripple current requirement ofia , ib , and ic , as well as the controller demand of filter cut-off

SUN et al.: THREE-PHASE DUAL-BUCK INVERTER WITH UNIFIED PULSEWIDTH MODULATION 1163

Fig. 7. Control block diagram of three-phase dual-buck inverter at standalone mode.

Fig. 8. Unified PWM signals for positive half-cycle switches when duty cycleis 0.9. (a) SPWM. (b) SVPWM. (c) DSVPWM.

frequency after selecting Cf . For example, if the selection of Lp

(Ln ) follows this design rule, then Lp (Ln ) = 1.25 mH.Rule No. 2: If Rule No. 1 is followed, the total inductance will

be twice that of conventional three-phase VSIs because there aresix inductors instead of three. To solve this, one phase can sharea common filter inductor Lf , and the remaining inductancescan serve as Lp (Ln ). This solution was implemented in theprototype discussed in this paper. Lf is allocated 1 mH, and theremaining inductance, 0.25 mH, is dedicated to Lp (Ln ). In thisway, a total of 3 mH inductance (1.25 mH × 6 − (0.25 mH ×6 + 1 mH × 3)) can be saved compared to Rule No. 1. The

Fig. 9. Unified PWM when duty extended to 1.1. (a) SVPWM. (b) DSVPWM.

inductance is only increased by 0.25 mH per phase comparedto conventional VSIs. However, Rule No. 2 leads to anotherquestion: What is the smallest that Lp (Ln ) can be? Besidesfiltering, one of the functions of Lp (Ln ) is to protect againstshoot-through under fault conditions. As discussed in SectionII, in normal operation, the proposed inverter totally eliminatesshoot-through problems. However, under some fault conditions,the gating signals for S1 and S4 might be high at the same time.Under this condition, Lp and Ln are inserted in the shoot-throughpath through the dc power supply, which will limit the di/dt ofthe devices, and thus decrease the failure rate of the circuit andprovide enough time for the protection circuit to shut down thesystem. Therefore, larger Lp (Ln ) leads to less failure under faultconditions. As a result, when determining the value for Lp (Ln )there is a tradeoff between cut-down of total inductance andprotection under fault conditions.

1164 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012

Fig. 10. Output voltage and current waveforms at dc bus voltage 380 V. (a)SPWM. (b) SVPWM. (c) DSVPWM.

Rule No. 3: In motor drive applications, there is no need toput in filter inductors because the motor inductance serves asthe filter. In this case, Lp (Ln ) can be a smaller value selected toprotect against shoot-through under fault conditions as discussedin Rule No. 2.

The system controller and unified PWM are implemented us-ing a TI floating point DSP TMS320F28335. For SPWM, thephase duty cycle can reach 1, while for SVPWM and DSVPWMthe duty cycle can be extended to 1.15. Two duty cycle condi-tions are tested: one is 0.9 for SPWM, SVPWM, and DSVPWM;the other is 1.1 for SVPWM and DSVPWM. For the 0.9 duty

cycle condition, the dc bus voltage is set at 380 V. For the 1.1duty cycle condition, the dc bus is lowered to 308 V. Efficiencycurves of different test conditions were measured and plotted.

Fig. 8 shows the phase A duty cycle at 0.9 and the PWM forthe active switch that operates during the positive half-cycle ofeach phase. It matches the simulation results. The PWM signalsfor the negative half-cycle are shifted 180◦ for each phase.

Fig. 9 shows the relationship between da , dan and the corre-sponding PWM when the duty cycle is 1.1. It can be seen thatafter injection of dzs for SVPWM and DSVPWM, da can belarger than 1, which means further utilization of dc bus voltage.iS4 is the current through S4 . It is clear that when S1 is switch-ing during the positive half-cycle, S4 is OFF because the currentthrough the switch is zero. When S1 is OFF during the negativehalf-cycle, S4 is operating based on the PWM pattern provided.

Fig. 10 shows three-phase output current and phase-to-neutralvoltage waveforms for SPWM, SVPWM, and DSVPWM underdc bus voltage 380 V with duty cycle 0.9. It is at the peak powercondition (2.5 kW) with 120 V rms and 7 A rms ac output of eachphase. It can be seen that the change between PWM schemescan be achieved effortlessly with unified PWM by adjusting theinjected dzs while the output characteristics remain the same.

Fig. 11 shows three-phase output current and voltage wave-forms for SVPWM and DSVPWM under dc bus voltage 308 Vwith duty cycle 1.1. It can be seen that the output voltage is still120 V, but the dc bus requirement is greatly reduced for thesetwo SVPWM methods.

Fig. 12 shows positive half-cycle three-phase output currentwaveforms for SPWM, SVPWM, and DSVPWM under dc busvoltage 380 V with duty cycle 0.9. It is the half-cycle current,unique to this topology, which ensures that only one activeswitch per phase works at any given time, eliminating the pos-sibility of shoot-through.

Loss analysis of the proposed inverter against conventionalinverter is provided below:

1) Active switch loss comparison. Because of reverse recov-ery problems with the MOSFET body diode, conventionalVSIs have to use IGBTs when the dc bus voltage rangesfrom 300 V to 600 V. This proposed topology avoids con-ducting through the body diode, and that is the reasonwhy high voltage power MOSFETs (600 V to 900 V, suchas CoolMOS or MDMesh series) can be employed. Con-ventional inverters use IGBTs, and the switching loss ofIGBTs is much higher than that of MOSFETs for two ma-jor reasons. First, the switching speed of IGBTs is slower,so the overlap time of voltage and current during switch-ing is longer and the overlap area is larger. Second, whenIGBTs turn OFF, there is a large tail current which createshigher losses. The proposed inverter uses MOSFETs to re-duce switching loss through its faster switching and lackof turn-off tail current. Because MOSFETs have a resistiveconduction voltage drop while IGBTs have a fixed voltagedrop, the conduction loss is reduced as well when usingMOSFETs. When this topology is used in higher cur-rent applications, MOSFETs can be paralleled to reducethe resistive voltage drop and thus still obtain a lowerconduction loss than IGBTs of the same current rating.

SUN et al.: THREE-PHASE DUAL-BUCK INVERTER WITH UNIFIED PULSEWIDTH MODULATION 1165

Fig. 11. Output voltage and current waveforms at dc bus voltage 308 V.(a) SVPWM. (b) DSVPWM.

Applications with very high output current may requiremore MOSFETs than can be practically put in parallel.In that case, it is a good idea to adopt the hybrid-switchconcept [9], building each active switch by placing MOS-FETs in parallel with an IGBT. The MOSFETs conductwhen current is low, and the IGBT takes over under high-current conditions. The hybrid-switch might suffer fromthe tail current of the IGBT during high-current operation,but, compared to conventional VSIs, performance is stillbetter in low-current regions because of the MOSFETs.

2) Diode loss comparison. Most conventional inverters useIGBT modules with antiparallel diodes. Most diodespaired with IGBTs are not designed to be fast switchingdiodes. When the diodes turn OFF, there are large reverserecovery losses. In contrast, the proposed topology allowsthe designer to pick a better free-wheeling diode. It isdesirable to choose diodes with fast or ultrafast reverserecovery features to further cut down the switching losses,and, at the same time, diodes with lower voltage drops canbe selected to reduce conduction losses.

3) Inductor loss comparison. When this topology is used instandalone and grid-tie applications where filter inductorsare needed, the losses in the inductors are the same as the

Fig. 12. Output positive half-cycle current waveforms at dc bus voltage 380 V.(a) SPWM. (b) SVPWM. (c) DSVPWM.

Fig. 13. Efficiency measurement under different PWM methods. (a) Efficiencyversus output power. (b) Efficiency versus output current.

1166 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 3, MARCH 2012

losses in conventional VSIs. Even though the three-phasedual-buck inverter has more inductors than a conventionalVSI, the loss is the same because Lp only works during thepositive half-cycle, and Ln only works during the negativehalf-cycle. In motor drive applications, because Lp and Ln

are small values, the associated losses are also small. Theenergy lost in the inductors is outweighed by the energysaved in the active switches.

Therefore, the overall efficiency of the proposed inverter ishigher than that of traditional VSIs.

Fig. 13 shows measured efficiency curves under different dcbus voltage and duty cycle conditions for SPWM, SVPWM,and DSVPWM. The switching frequency is 20 kHz, and theoutput phase voltage is 120 V. The load is a three-phase, Y-connected, variable resistive load bank. All efficiency mea-surements were done using digital power meters with 0.1%accuracy. The model number of the meters is YOKOGAWAWT1600. Fig. 13 (a) shows the efficiency against total outputpower, while Fig. 13 (b) shows the efficiency against phase rmscurrent to meet the common practice of drive applications. Itcan be seen that DSVPWM can improve efficiency by an aver-age of 0.4% compared to SVPWM or SPWM under the samedc bus and duty cycle conditions. In addition, with the help ofextended duty cycle, SVPWM and DSVPWM can run at lowerbus voltage, further reducing switching losses. For example, theefficiency of DSVPWM at 308 V with duty 1.1 is 0.7% higherthan that of SPWM at 380 V with duty 0.9. The peak efficiencyof the inverter is 98.8%.

VI. CONCLUSION

A new type of VSI, the three-phase dual-buck inverter, hasbeen proposed. It has the advantage of utilizing power MOS-FETs as active switches, and improves inverter reliability byeliminating the possibility of shoot-through and the need fordead-time. In order to reduce the computational load on the dig-ital signal processor, unified PWM was analyzed and applied,including SPWM, SVPWM, and DSVPWM.

To prove the effectiveness of the proposed topology and con-trol scheme, a three-phase dual-buck inverter system operatingat standalone mode with 2.5 kW, 208VAC output capability hasbeen designed and tested. Different PWM methods were testedunder different dc bus voltage and duty cycle conditions. The ef-ficiency of different cases was reported, and the peak efficiencywas 98.8%.

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SUN et al.: THREE-PHASE DUAL-BUCK INVERTER WITH UNIFIED PULSEWIDTH MODULATION 1167

Pengwei Sun (S’07) received the B.S. and M.S.degrees, in electrical engineering, in 2004 and2007, respectively, from North China Electric PowerUniversity (NCEPU), China.

Since 2007, he has been a Graduate ResearchAssistant and Ph.D. student in the Future EnergyElectronics Center (FEEC), at the Virginia Polytech-nic Institute and State University (Virginia Tech),Blacksburg, VA. His research interests are relatedto design and control of high-efficiency single-phaseand three-phase inverters, as well as multilevel and

cascade inverters for renewable energy applications, including electric vehicle,and solar and wind power systems.

Chuang Liu (S’11) received the M.S. degree in elec-trical engineering, in 2009, from Northeast DianliUniversity, China. Since 2009, he has been a Ph.D.student in electrical engineering at Harbin Instituteof Technology, China.

Since September 2010, he has been at the FutureEnergy Electronics Center (FEEC), Virginia Poly-technic Institute and State University (Virginia Tech),Blacksburg, VA, as a Visiting Student, supported bythe Chinese Scholarship Council. His research inter-ests are related to intelligent universal transformer

(IUT) for renewable energy systems, as well as future dc-based renewableenergy nanogrid, PHEV/PEV smart parking lot/building, and battery energystorage systems.

Jih-Sheng Lai (S’85–M’89–SM’93–F’07) receivedthe M.S. and Ph.D. degrees in electrical engineeringfrom the University of Tennessee, Knoxville, in 1985and 1989, respectively.

From 1980 to 1983, he was the Head of the Electri-cal Engineering Department of the Ming-Chi Instituteof Technology, Taipei, Taiwan, where he initiated apower electronics program and received a grant fromhis college and a fellowship from the National Sci-ence Council to study abroad. In 1986, he became astaff member at the University of Tennessee, where

he taught control systems and energy conversion courses. In 1989, he joinedthe Electric Power Research Institute (EPRI) Power Electronics ApplicationsCenter (PEAC), where he managed EPRI-sponsored power electronics researchprojects. Starting in 1993, he worked with the Oak Ridge National Laboratoryas the Power Electronics Lead Scientist, where he initiated a high power elec-tronics program and developed several novel high power converters includingmultilevel converters and soft-switching inverters. In 1996, he joined VirginiaPolytechnic Institute and State University (Virginia Tech), where he is currentlya Professor and the Director of the Future Energy Electronics Center (FEEC).He has published more than 200 technical papers and 2 books and received 18U.S. patents. His main research areas are in high efficiency power electronicsconversions for high power and energy applications.

Dr. Lai chaired the 2000 IEEE Workshop on Computers in Power Electronics(COMPEL 2000), the 2001 IEEE/DOE Future Energy Challenge, and the 2005IEEE Applied Power Electronics Conference and Exposition (APEC 2005). Heis the recipient of several distinctive awards including a Technical Achieve-ment Award at Lockheed Martin Award Night, two IEEE IAS Conference PaperAwards, and Best Paper Awards from IECON-97, IPEC-05, and PCC-07.

Chien-Liang Chen (M’11) received the B.S. de-gree from National Taiwan University of Science andTechnology, in 2002, the M.S. degree from NationalTsing-Hua University, in 2004, and the Ph.D. de-gree from the Virginia Polytechnic Institute and StateUniversity (Virginia Tech), in 2011, all in electricalengineering.

He is currently doing postdoctoral research at theFuture Energy Electronics Center (FEEC), VirginiaTech. His research interests include grid-tie inverters,parallel inverters, mircogrid applications, and soft-

switching techniques.

Nathan Kees (S’07) received the B.S. degree in elec-trical engineering from Virginia Polytechnic Instituteand State University (Virginia Tech), in 2008, wherehe is currently working toward the M.S. degree inelectrical engineering.

In 2008, he received the Bradley Fellowship fromthe Bradley Department of Electrical and ComputerEngineering at Virginia Tech. He joined Dr. HardusOdendaal in Electromagnetic Launcher Research atVirginia Tech as a Graduate Research Assistant inthe same year. In 2010, he began work with Dr. Jih-

Sheng Lai in the Future Energy Electronics Center (FEEC) at Virginia Tech. Heis interested in EMI problems in soft-switching inverters.