5358 IEEE TRANSACTIONS ON POWER …repository.um.edu.my/39889/1/Freddy Oct 2014.pdf · 5358 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 10, OCTOBER 2014 Comparison and Analysis

5358 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 10, OCTOBER 2014

Comparison and Analysis of Single-PhaseTransformerless Grid-Connected PV Inverters

Tan Kheng Suan Freddy, Nasrudin A. Rahim, Senior Member, IEEE, Wooi-Ping Hew, Member, IEEE,and Hang Seng Che

Abstract—Leakage current minimization is one of the most im-portant considerations in transformerless photovoltaic (PV) in-verters. In the past, various transformerless PV inverter topolo-gies have been introduced, with leakage current minimized bythe means of galvanic isolation and common-mode voltage (CMV)clamping. The galvanic isolation can be achieved via dc-decouplingor ac-decoupling, for isolation on the dc- or ac-side of the inverter,respectively. It has been shown that the latter provides lower lossesdue to the reduced switch count in conduction path. Nevertheless,leakage current cannot be simply eliminated by galvanic isolationand modulation techniques, due to the presence of switches’ junc-tion capacitances and resonant circuit effects. Hence, CMV clamp-ing is used in some topologies to completely eliminate the leakagecurrent. In this paper, several recently proposed transformerlessPV inverters with different galvanic isolation methods and CMVclamping technique are analyzed and compared. A simple modifiedH-bridge zero-voltage state rectifier is also proposed, to combinethe benefits of the low-loss ac-decoupling method and the com-plete leakage current elimination of the CMV clamping method.The performances of different topologies, in terms of CMV, leak-age current, total harmonic distortion, losses and efficiencies arecompared. The analyses are done theoretically and via simulationstudies, and further validated with experimental results. This pa-per is helpful for the researchers to choose the appropriate topol-ogy for transformerless PV applications and to provide the designprinciples in terms of common-mode behavior and efficiency.

Index Terms—Common-mode voltage (CMV), leakage current,photovoltaic (PV) system, transformerless.

I. INTRODUCTION

TODAY, the energy demand is increasing due to the rapidincrease of the human population and fast-growing indus-

tries. Hence, renewable energy plays an important role to replacetraditional natural resources such as fuel and coal. Photovoltaic(PV) energy has recently become a common interest of researchbecause it is free, green, and inexhaustible [1]–[3]. Further-more, PV systems are now more affordable due to government

Manuscript received June 17, 2013; revised August 13, 2013 and Octo-ber 21, 2013; accepted December 2, 2013. Date of current version May 30,2014. This research work was supported by the Campus Network Smart Gridfor Energy Security under Grant H-16001–00-D000032 and by the PPP un-der Grant PV105–2012 A. Recommended for publication by Associate EditorD. Xu.

T. K. S. Freddy is with the UMPEDAC, University of Malaya, 59990 KualaLumpur, Malaysia and with Faculty of Engineering, University of Malaya,50603 Kuala Lumpur, Malaysia (e-mail: [email protected]).

N. A. Rahim, W.-P. Hew, and H. S. Che are with the UMPEDAC, Universityof Malaya, 59990 Kuala Lumpur, Malaysia (e-mails: [email protected];[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2013.2294953

incentives, advancement of power electronics and semiconduc-tor technology and cost reduction in PV modules [2], [3].

Generally, there are two types of grid-connected PV systems,i.e., those with transformer and without transformer. The trans-former used can be high frequency (HF) transformer on thedc side or low frequency transformer on the ac side [4]–[13].Besides stepping up the voltage, it plays an important role insafety purpose by providing galvanic isolation, and thus elim-inating leakage current and avoiding dc current injection intothe grid. Nevertheless, the transformers are bulky, heavy, andexpensive. Even though significant size and weight reductioncan be achieved with HF transformer, the use of transformerstill reduces the efficiency of the entire PV system [9]. Hence,transformerless PV systems are introduced to overcome theseissues. They are smaller, lighter, lower in cost, and highlyefficient [4]–[13].

However, safety issue is the main concern for the transformer-less PV systems due to high leakage current. Without galvanicisolation, a direct path can be formed for the leakage currentto flow from the PV to the grid. At the same time, the fluctu-ating potential, also known as common-mode voltage (CMV),charges and discharges the stray capacitance which generateshigh leakage current. Besides safety issue, this leakage currentincreases grid current ripples, system losses, and electromag-netic interference.

In order to reduce the leakage current to meet the standardin [14], conventional half bridge inverter or full-bridge inverterwith bipolar modulation technique are used in transformerlessPV systems to generate constant CMV to reduce the leakagecurrent. However, a 700-V dc-link voltage is required for thehalf bridge and diode-clamped topologies [15]–[17]. For full-bridge bipolar modulation, high losses and reduced efficiencyare observed due to two-level bipolar output voltage. As a result,the voltage stress across the inductors is doubled and currentripples increase. Larger filter inductors are required, increasingthe cost and size of the PV systems.

Hence, many research works have been proposed recentlyto eliminate the leakage current via galvanic isolation andCMV clamping techniques. Galvanic isolation topologies suchas H5 [18], H6 family [19]–[22], and HERIC [23] introducedc-decoupling and ac-decoupling to disconnect the PV and thegrid. It is found that ac-decoupling provides lower losses due toreduced switch count in the conduction path. Nevertheless, thegalvanic isolation alone cannot completely eliminate the leakagecurrent due to the influence of switches’ junction capacitancesand parasitic parameters [21], [28]. Therefore, CMV clampinghas been used in oH5 [24], H6 [25], and H-bridge zero-voltage

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FREDDY et al.: COMPARISON AND ANALYSIS OF SINGLE-PHASE TRANSFORMERLESS GRID-CONNECTED PV INVERTERS 5359

Fig. 1. Recently proposed transformerless topologies. (a) Diode-clamped topology. (b) H5 topology. (c) HERIC topology. (d) oH5 topology. (e) H6 topology.(f) HBZVR topology.

state rectifier (HBZVR) [26], as shown in Fig. 1(d)–(f), to com-pletely eliminate the leakage current. However, the clampingbranch of HBZVR does not perform optimally. It is shown inthe later section that the leakage current is as high as those ofgalvanic isolation topologies.

In this paper, several recently proposed transformerless PVinverters with different galvanic isolation methods and CMVclamping techniques, as shown in Fig. 1, are analyzed and com-pared. A simple modified HBZVR-D is also proposed, to com-bine the benefits of the low-loss ac-decoupling method and thecomplete leakage current elimination of the CMV clampingmethod. Performance of HBZVR-D is compared to other exist-ing topologies in terms of CMV, leakage current, total harmonicdistortion (THD), losses analysis, and efficiency. Discussionsare done based on MATLAB/Simulink simulations and furthervalidated through experimental tests. It is proven that HBZVR-D topology gives the best overall performance and is suitablefor transformerless PV applications.

This paper is organized as follows: Leakage current reduc-tion methods via galvanic isolation and CMV clamping is dis-

cussed and analyzed in Section II. Proposed topology with itsconversion structure and operation principles is presented inSection III. Simulation and experimental results are shown inSection IV and Section V, respectively, to validate and discussthe performance of various topologies. Finally, conclusion ismade in Section VI to summarize the findings and results.

II. COMMON-MODE BEHAVIOR AND LEAKAGE CURRENT

REDUCTION METHODS

When the transformer is removed from the inverter, a reso-nant circuit is formed as shown in Fig. 2(a). This resonant circuitincludes stray capacitance (CP V ), the filter inductors (L1 andL2), and leakage current (IL ). Here, the power converter isrepresented by a block with four terminals to allow a generalrepresentation of various converter topologies. On the dc side,P and N are connected to the positive and negative rail of thedc-link, respectively; while on the ac side, terminals A and Bare connected to the single-phase grid via filter inductors. Fromthe view point of the grid, the power converter block shown


Fig. 2. Common-mode model for single-phase grid-connected inverter. (a) Full model. (b) Simplified model. (c) Simplified common-mode model.

in Fig. 2(a) can be considered as voltage sources, generatingvoltage VAN and VBN . Hence, regardless of the conversionstructure, this power converter block can be simplified into theequivalent circuit which consists of VAN and VBN as shownin Fig. 2(b) [30], [31]. The leakage current is thus a functionof VAN ,VBN , grid voltage, filter inductance, and stray capac-itance.

The CMV VC M and differential-mode voltage VDM can bedefined as [8], [15], [20], [29]–[32]

VC M =VAN + VBN

2(1)

VDM = VAN − VBN . (2)

Rearranging (1) and (2), the output voltages can be expressedin terms of VC M and VDM as

VAN = VC M +VDM

2(3)

VBN = VC M − VDM

2. (4)

Using (3)–(4) and considering only the common-mode com-ponents of the circuit, a simplified common-mode model canbe obtained as in Fig. 2(c), following the steps in [29] and [30].The equivalent CMV (VEC M ) is defined as

VEC M = VC M +VDM

2L2 − L1L1 + L2

. (5)

Since identical filter inductors (L1 = L2) are used in thispaper, the VEC M is equal to VC M

VEC M = VC M =VAN + VBN

2. (6)

From the model, it can be concluded that the leakage current isvery much dependent of the CMV. Thus, converter structure andthe modulation technique must be designed to generate constantCMV in order to eliminate the leakage current.

It is worth highlighting that the model in Fig. 2(c) has beencommonly used for describing the common-mode behavior ofthe conventional full-bridge (H4) topology. However, due tothe generality of the model, it is obvious that the model isvalid for other topologies discussed here, apart from H4. As amatter of fact, the same model has been used to analyze thecommon-mode behavior of various transformerless convertertopologies [16], [21], [29], [30]. However, since different topol-ogy has different VAN and VBN , the expressions for VC M

and VDM will differ from one another, which yield different

Fig. 3. Universal transformerless topologies.

common-mode behavior. Hence, to evaluate the common modebehavior of a particular topology, VAN and VBN under differentswitching condition need to be evaluated, as will be shown later.

A. Galvanic Isolation

In transformerless PV inverters, the galvanic connection be-tween the PV and the grid allows leakage current to flow. Hence,in topologies such as H5 and HERIC, galvanic isolation is pro-vided to reduce the leakage current.

The galvanic isolation can basically be categorized intodc-decoupling and ac-decoupling methods. For dc-decouplingmethod, dc-bypass switches are added on the dc side of theinverter to disconnect the PV arrays from the grid during thefreewheeling period. However, the dc-bypass branch, whichconsists of switches or diodes, is included in the conductionpath as shown in Fig. 3. For H6, output current flows throughtwo switches and the two dc-bypass branches during the con-duction period. Hence, the conduction losses increase due to theincreased number of semiconductors in the conduction path.On the other hand, bypass branch can also be provided onthe ac side of the inverter (i.e., ac-decoupling method) suchas seen in HERIC. This ac-bypass branch functions as a free-wheeling path which is completely isolated from the conductionpath, as shown in Fig. 3. As a result, the output current flowsthrough only two switches during the conduction period. There-fore, topologies employing ac-decoupling techniques [23] arefound to be higher in efficiency as compared to dc-decouplingtopologies [20]–[22], [27].

One setback of galvanic isolation is that there is no wayof controlling the CMV by PWM during the freewheeling pe-riod. Fig. 4 shows operation modes of galvanic isolation which


Fig. 4. Operation modes of dc-decoupling topology. (a) Conduction mode and(b) freewheeling mode.

employs dc-decoupling method. As shown in Fig. 4(a), duringthe conduction period, S1 and S4 conduct to generate the de-sired output voltage. At the same time, VA is directly connectedto VDC and VB is connected to the negative terminal (N) ofthe dc-link. Hence, the CMV becomes

VC M =VAN + VBN

2=

12(VDC + 0) =

VDC

2. (7)

Nevertheless, during the freewheeling period, the dc-bypassswitches disconnect the dc-link from the grid. Therefore, pointA and point B are isolated from the dc-link, and VA and VB

are floating with respect to the dc-link as shown in Fig. 4(b).The CMV during this period of time is not determined by theswitching state, but instead, is oscillating with amplitude de-pending on the parasitic parameters and the switches’ junctioncapacitances of the corresponding topology. As a result, leakagecurrent can still flow during freewheeling period. The same isthe case for converters using ac-decoupling method.

B. CMV Clamping

As mentioned earlier, CMV is one of the main causes forleakage current. H5 and HERIC focus only on providing gal-vanic isolation while neglecting the effect of the CMV. Unlikeconventional topologies, the CMV in these topologies cannotbe manipulated via PWM, due to the use of galvanic isolationas explained previously. In order to generate constant CMV,clamping branch is introduced in oH5 [see Fig. 1(d)] and H6

Fig. 5. Proposed HBZVR-D topology. (a) Converter structure. (b) Switchingwaveforms.

[see Fig. 1(e)]. Generally, the clamping branch consists of diodesor switches and a capacitor divider which ensures the freewheel-ing path is clamped to the half of the input voltage. With thecombined effect of galvanic isolation and CMV clamping, leak-age current is completely eliminated. Nevertheless, both H6 andoH5 uses dc-decoupling method, which suffers from lower effi-ciency. HBZVR also employs CMV clamping technique but itis found that the clamping branch does not function optimally. Itis shown in both the simulation and experimental results that theCMV and the leakage current in HBZVR are as high as those inthe topologies which use only galvanic isolation.

III. OPERATION PRINCIPLES OF PROPOSED TOPOLOGY

A. Structure of Proposed HBZVR-D

Based on the analysis above, a simple modified HBZVR-D isproposed to combine the benefits of the low-loss ac-decouplingmethod and the complete leakage current elimination of theCMV clamping method. HBZVR-D is modified by adding afast-recovery diode, D6 , to the existing HBZVR as shown inFig. 5(a). The voltage divider is made up of C1 and C2 . S1−S4are the switches for full-bridge inverter. The antiparallel diodes,D1−D4 , as well as S5 provide a freewheeling path for thecurrent to flow during the freewheeling period. Diodes D5 andD6 form the clamping branches of the freewheeling path.

B. Operation Modes and Analysis

In this section, the operation modes and the CMV of the pro-posed topology is discussed. Fig. 5(b) illustrates the switching


Fig. 6. Operation modes of proposed HBZVR-D topology. (a) Mode 1—conduction mode and (b) Mode 2—freewheeling mode during positive half cycle.(c) Mode 3—conduction mode and (d) Mode 4—freewheeling mode during negative half cycle.

patterns of the proposed HBZVR-D. Switches S1−S4 commu-tate at switching frequency to generate unipolar output voltage.S5 commutates complementarily to S1−S4 to create freewheel-ing path. All the four operation modes are shown in Fig. 6 togenerate unipolar output voltage.

In mode 1, S1 and S4 are ON while S2 , S3 and S5 are OFF.Current increases and flows through S1 and S4 . VAB = +VDC .The CMV becomes

VC M =VAN + VBN

2=

12(VDC + 0) =

VDC

2. (8)

In mode 2, S1−S4 are OFF. S5 is ON to create a freewheelingpath. Current decreases and freewheels through diodes D3 ,D2 ,and the grid. The voltage VAN decreases and VBN increasesuntil their values reach the common point, VDC /2, such thatVAB = 0. The CMV is

VC M =VAN + VBN

2=

12

(VDC

2+

VDC

2

)=

VDC

2. (9)

In mode 3, S2 and S3 are ON, while S1 , S4 and S5 are OFF.Current increases and flows through S2 and S3 . VAB =−VDC .The CMV becomes

VC M =VAN + VBN

2=

12(0 + VDC ) =

VDC

2. (10)

In mode 4, S1−S4 are OFF. S5 is ON to create freewheelingpath. Current decreases and freewheels through diodes D1 ,D4 ,and the grid. The voltage VAN decreases and VBN increasesuntil their values reach the common point, VDC /2, and VAB =0. The CMV is as derived in (10).

Obviously, modulation techniques are designed to generateconstant CMV in all four operation modes. All the research

works are designed based on the principles above. Practically,VAN and VBN do not reach common point during the free-wheeling period (mode 2 and mode 4). It is shown in simulationand experimental results later that the CMV is not constantwithout clamping branch. During the freewheeling period, bothVAN and VBN are not clamped to VDC /2 and is oscillatingwith amplitude depending on the parasitic parameters and junc-tions’ capacitance of those topologies. The improved clampingbranch of HBZVR-D ensures the complete clamping of CMV toVDC /2 during the freewheeling period. It is well noted that theoutput current flows through only two switches in every conduc-tion period (mode 1 and mode 3) as shown in Fig. 6(a) and (c).This explains why HBZVR-D has relatively higher efficiencythan those of dc-decoupling topologies.

C. Operation Principles of Improved Clamping Branch

During the freewheeling period, S5 is turned ON, connectingpoint A and B. Freewheeling path voltage VF P can be defined asVF P =VAN ≈VBN , since the voltage drops across diodes andS5 are small compared to VDC . There are two possible modesof operation (mode 2 and mode 4 as shown in Fig. 6) dependingon whether D5 or D6 is forward biased. When VF P is greaterthan VDC /2, D5 is forward biased and D6 is reversed biased.Current flows from the freewheeling path to the midpoint of thedc-link via the clamping diode D5 , as shown in Fig. 6(b), whichcompletely clamps the VF P to VDC /2. On the other hands,when the VF P is less than VDC /2, D6 is forward biased andD5 is reversed biased. As shown in Fig. 6(d), current flows fromthe midpoint of the dc-link to the freewheeling path via the addedclamping diode D6 , to increase the VF P to VDC /2. It should


be noted that during the dead time between the conductionperiod and freewheeling period, the freewheeling path is notwell-clamped and the CMV can be oscillating with the gridvoltage. Nevertheless, with proper selection of dead time, thiseffect can be minimized.

In HBZVR, the clamping branch consists of D5 only. Thus,the clamping of the freewheeling path is limited only for theperiod when VF P is more than VDC /2. When VF P is less thanVDC /2, the clamping branch does not function because D5 isreverse biased. During such condition, the CMV in HBZVRwill oscillate, causing the flow of leakage current. This set-back is rectified by adding a fast-recovery diode D6 in theproposed HBZVR-D topology. With both D5 and D6 , the im-proved clamping branch guarantees the complete clamping ofthe CMV to VDC /2 throughout the freewheeling period. As aresult, leakage current, which is very much dependent on CMV,is completely eliminated.

IV. SIMULATIONS

A. Output Performance and Common-Mode Behavior

Simulations are carried out as shown in Fig. 1 using MAT-LAB/ Simulink to analyze the operation and overall perfor-mance of the PV system. All the simulations are carried outbased on the same parameters. The PV array is simulated withdc voltage source of 400 V. The stray capacitance (CP V ) is mod-eled with two capacitors of 100 nF, each connected to the PVterminal and the ground. The ground resistance (RG ) is 11 Ω.The filter is made up of two inductors (L); each has a valueof 3 mH. The grid line to neutral voltage is 230 V (rms) withfrequency (f) of 50 Hz. The switching frequency (fs) is 10 kHz.

Figs. 7–12 show the simulations of output waveform andcommon-mode behavior for various topologies. All the topolo-gies share one common characteristic. They are generatingunipolar output voltage, which reduces the grid current ripplesand filter inductor losses as addressed in bipolar modulationtechniques. Hence, smaller filter inductors are required as com-pared to topologies with bipolar output.

As shown in Fig. 7(b), large oscillations with the magnitudeup to 100 V are observed in both VAN and VBN for H5 topol-ogy. Moreover, the CMV is not constant and is oscillating withthe magnitude up to 200 V. Therefore, the leakage current isnot completely eliminated. The common-mode behavior of H5topology can be studied in detail as shown in Fig. 7(c). It isclearly shown that VAN and VBN are well clamped to VDC

and 0 during the conduction period. However, during the free-wheeling period, both VAN and VBN are floating and henceCMV is not constant. Practically, this proves that the galvanicisolation and modulation technique alone are not able to gener-ate constant CMV.

HERIC topology has the similar common-mode performanceas H5 topology. Although the switches commutate diagonallyto generate constant CMV, the CMV is still floating. As shownin Fig. 8(b), VAN ,VBN , and the CMV are oscillating. There-fore, the leakage current is not totally eliminated. The detailedcommon-mode waveform can be seen in Fig. 8(c). It is proven

Fig. 7. H5 topology: (a) output voltage (top), grid current (middle), leakagecurrent (bottom); (b) VA N (top), CMV (middle), VB N (bottom); (c) VA N

(top), CMV (middle), VB N (bottom)—detail.

that the leakage current cannot be simply eliminated by galvanicisolation.

The aforementioned issues have been solved by the useof clamping branch in oH5 and H6 topologies. As shown inFigs. 9(b) and 10(b), VAN and VBN are totally complemen-tary to one another and the CMV is completely constant at200 V in both conduction period and freewheeling period. Asa result, zero leakage current is observed in both H6 and oH5topologies as shown in Figs 9(a) and 10(a). Although HBZVRemploys CMV clamping technique, it is mentioned earlier thatthe clamping branch does not perform satisfactorily. As shownin Fig. 11(b), voltage spikes with magnitudes up to 150 V areobserved in the CMV. As a result, the leakage current is noteliminated. The common-mode behavior is the same as those ofgalvanic isolation family.

Proposed HBZVR-D has improved the performance of theclamping branch as shown in Fig. 12(b). Obviously, CMV isclamped at 200 V throughout the operation period. VAN andVBN are totally complementary to one another. Thus, leakagecurrent can be eliminated.


Fig. 8. HERIC topology: (a) output voltage (top), grid current (middle), leak-age current (bottom); (b) VA N (top), CMV (middle), VB N (bottom); (c) VA N

(top), CMV (middle), VB N (bottom)—detail.

Fig. 9. oH5 topology: (a) output voltage (top), grid current (middle), leakagecurrent (bottom); (b) VA N (top), CMV (middle), VB N (bottom).

Fig. 10. H6 topology: (a) output voltage (top), grid current (middle), leakagecurrent (bottom); (b) VA N (top), CMV (middle), VB N (bottom).

Fig. 11. HBZVR topology: (a) output voltage (top), grid current (middle),leakage current (bottom); (b) VA N (top), CMV (middle), VB N (bottom).

B. Losses Analysis

The loss analysis is simulated via thermal module in PSIM.The simulations for all the topologies are carried out based onthe device parameters listed in Table I. There are two major typesof losses in PV systems; i.e., conduction losses and switchinglosses.


Fig. 12. HBZVR-D topology: (a) output voltage (top), grid current (middle),leakage current (bottom); (b) VA N (top), CMV (middle), VB N (bottom).

TABLE IPARAMETERS FOR LOSSES SIMULATION [34]

Practically, when the IGBT conducts, there is certain voltagedrop across the switch, namely saturation voltage (VC E (SAT )).Hence, the conduction losses of IGBT (PC ON IGBT ) are cal-culated by [20], [22], [31], [33]

P C ON IGBT = VC E (SAT ) · IC (11)

where IC is the on-state current.Similarly, when the freewheeling diode conducts, the forward

voltage (VF ) drop across the diode which results in conductionlosses which are calculated by [20], [22], [31], [33]

PC ON D = VF · IF (12)

where IF is the freewheeling current.Switching losses are calculated by [35]

P SW ON = EON · f · VDC /VDC DAT ASH EET (13)

P SW OF F = EOF F · f · VDC /VDC DAT ASH EET (14)

Fig. 13. Simulated losses results at 1-kW prototype.

TABLE IIPARAMETERS OF UNIVERSAL INVERTER [34]

where P SW ON and P SW OF F are the losses during turn-onand turn-off time, respectively, EON and EOF F are the turn-onand turn-off energy losses of the IGBT, VDC is the actual dcbus voltage, and VDC DAT ASH EET is the dc bus voltage in theEON and EOF F characteristics of the datasheet [35]. The totalswitching losses are

P SW IGBT = P SW ON + P SW OF F . (15)

Fig. 13 shows the losses results for various topologies. H5 andoH5 add one additional switch, whereas H6 adds two additionalswitches and diodes into the conduction path. This explains whyall the dc-decoupling topologies (H5, oH5, and H6) have higherlosses as compared to the ac-decoupling topologies (HERIC,HBZVR, and HBZVR-D). H6 topology yields the highest de-vice losses due to excessive components that are added into theconduction path. As expected, HERIC topology has the low-est device losses. HBZVR and HBZVR-D have slightly higherlosses than HERIC but they are still much lower than those ofthe dc-decoupling family.

Obviously, the conduction losses are the main contributoras shown in Fig. 13. The influence of the dc-link voltage onswitching losses is very small because the same dc-link voltageis applied to all the topologies. The influence of the filter inductorcurrent ripples is considered negligible since all the topologiesare generating three-level unipolar output voltage.

It is worth noting that the conduction losses can be further re-duced via proper choice of power electronics switches, suchas using MOSFETs instead of IGBTs [22], [27]. However,MOSFETs implementation is only limited to certain topologies


Fig. 14. Output line to line voltage (CH1) and load current (CH4): (a) H5, (b) HERIC, (c) H6, (d) oH5, (e) HBZVR, and (f) HBZVR-D.

because of the slow reverse-recovery of the body diode [22],[27]. For HERIC, HBZVR, and HBZVR-D, all the switches canbe replaced by MOSFETs because the body diodes of MOSFETsare not utilized. This means the efficiency of these topologies canbe improved further. In other words, ac-decoupling topologiesare good solutions for high-efficiency applications. Neverthe-less, the selection of switches is beyond the scope of this paper,and hence not discussed further. For this paper, IGBTs are usedin all the topologies.

Therefore, ac-decoupling family is more preferable in termsof efficiency. This is because the ac-bypass branch is isolatedand independent from the conduction path. It functions only asa freewheeling path and this decreases the conduction lossessignificantly. The losses analysis and study is useful for the en-gineer to choose and design the high-efficiency transformerlesstopology.

V. EXPERIMENTAL RESULTS

In order to verify the theoretical simulation results for differ-ent topologies, a universal inverter has been built using the samecomponents. Table II lists the inverter specifications. Resistorloads are used in replacement of grid [26]. Even though this in-creases the impedance of the leakage current path and changesthe magnitude of the leakage currents, it does not affect the va-lidity of the comparisons, since the same resistor loads are usedin all topologies. All the control algorithms are implemented inTexas Instrument’s TMS320F2812 DSP.

Fig. 14 shows the output performance for various topologies.Similar to the simulation results, all the topologies are gen-erating unipolar output line to line voltage and sinusoidal load

current. However, it is shown in Fig. 14(e) and (f) that the outputvoltage is not completely unipolar for HBZVR and HBZVR-Dtopologies. Spike with magnitude up to 200 V are observed.This problem arises due to the dead time between the operationperiod and freewheeling period. At this moment, the freewheel-ing path is not yet functioning because the freewheeling switch,S5 , is still OFF. Current freewheels through the correspondingantiparallel diodes of the switches and the load. This explainswhy the THD of the load current is slightly higher than oth-ers. The THD of the load currents for different topologies aremeasured by FLUKE 434 Series II Energy Analyzer. All theresults are listed in Table III. It can be seen that all the single-phase transformerless topologies have similar THD of the loadcurrents.

Fig. 15 shows the common-mode behavior for differenttopologies. The magnitude of the leakage current for H5,HERIC, H6, oH5, HBZVR, and HBZVR-D are 89.4, 84.3, 45.8,44.9, 74.5, and 42.7 mA (rms), respectively. Even though all ofthem meet the requirement of VDE 0126–1–1 standard, the pro-posed HBZVR-D topology gives the lowest leakage current. It isobvious that the leakage current of H5, HERIC, and HBZVR aredouble of the H6, oH5, and HBZVR-D. This is mainly becausethe HF CMV is not completely clamped as explained earlier.As shown in Fig. 15(a), (b), and (e), VAN ,VBN , and CMV ofH5, HERIC, and HBZVR are oscillating with the magnitudeup to 200 V. Therefore, leakage currents are relatively higher.This proves that modulation technique alone fails to generateconstant CMV. With clamping branch, the CMV is practicallyconstant for oH5, H6, and HBZVR-D. This explains why theleakage currents are reduced significantly.


TABLE IIIPERFORMANCE COMPARISONS FOR VARIOUS PWM

Fig. 15. VA N (CH1), CMV (M), VB N (CH2), and leakage current (CH4): (a) H5, (b) HERIC, (c) H6, (d) oH5, (e) HBZVR, and (f) HBZVR-D.

As shown in Fig. 15(e), the CMV of the HBZVR is only well-clamped in one half cycle when VF P is > VDC /2. VAN ,VBN ,and CMV are oscillating with HF when VF P is < VDC /2. Thisis due to the limitation of the clamping branch, where D5 couldonly operate when VF P is > VDC /2 as explained in SectionIII. The complete clamping has been provided by the additionaldiode, D6 , in the proposed HBZVR-D. As shown in Fig. 15(f),the CMV is constant in both positive and negative half cycle.This explains why the leakage current is reduced to 42.7 mA(rms) which is half of that of HBZVR. The experimental resultsverified the theoretical analysis.

Fig. 16 shows the measured efficiency for different topolo-gies. The Californian efficiency is calculated based on

ηC EC = 0.04η10% + 0.05η20% + 0.12η30% + 0.21η50%

+ 0.53η75% + 0.05η100% . (16)

The calculated Californian efficiency for H5, oH5, H6,HERIC, HBZVR, and HBZVR-D are 92.77, 93.32, 91.7,

Fig. 16. Measured efficiency for different topologies.

96.06, 94.91, and 95.03%, respectively. As expected, all theac-decoupling family has better efficiency than those of dc-decoupling family. Proposed HBZVR-D has the second high-est efficiency after HERIC topology. This is because the bidi-rectional switch S5 of the proposed HBZVR-D is switched athigh frequency, whereas the bidirectional switch of HERIC isswitched at grid frequency.


The experimental performance comparisons for all the topolo-gies are summarized in Table III. It is experimentally proventhat proposed HBZVR-D topology combines the superior per-formance of clamping branch family (constant CMV with lowleakage current) and ac-decoupling family (low losses and highefficiency), at a cost of a slight increase in THD.

VI. CONCLUSION

This paper presents the comparison and analysis of vari-ous recently-proposed single-phase transformerless PV invertertopologies. It is shown that two strategies have been commonlyused for reducing leakage current, i.e., galvanic isolation andCMV clamping. Based on the characteristic of the two strate-gies, performance of the different topologies can be evaluated.The patented works, such as H5 and HERIC, provide galvanicisolation for safety purposes. Nevertheless, their CMVs are notclamped and leakage currents are not completely eliminated.Other topologies, such as oH5 and H6, eliminate the leak-age current with the use of both galvanic isolation and CMVclamping, at the expense of reduced system efficiency. By usingac-decoupling method instead of dc-decoupling method for gal-vanic isolation, HBZVR and HERIC manage to achieve higherefficiency than the rest but perform poorly in terms of common-mode behavior.

With the understanding on the merits and demerits of thedifferent approaches, a modified HBZVR topology is obtainedby addition of a fast-recovery diode. The proposed topology(known as HBZVR-D) combines the advantages of the low-loss ac-decoupling method and the complete leakage currentelimination of the CMV clamping method.

The performance of the transformerless topologies, includingthe proposed HBZVR-D, is compared in terms of CMV, leakagecurrent, losses, THD, and efficiency. It is experimentally proventhat HBZVR-D topology gives the best overall performance andis suitable for transformerless PV applications for a 230-V (rms)grid system.

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Tan Kheng Suan Freddy received the B.Eng. degreein electrical engineering from the Multimedia Uni-versity, Melaka, Malaysia, in 2010. He is currentlyworking toward the Ph.D. degree in Power EnergyDedicated Advanced Center (UMPEDAC), Univer-sity of Malaya, Malaysia.

His research interests include transformerless PVinverters, power electronics and renewable energy.

Nasrudin A. Rahim (M’89–SM’08) received theB.Sc. (Hons.) and M.Sc. degrees from the Univer-sity of Strathclyde, Glasgow, U.K., and the Ph.D. de-gree from Heriot–Watt University, Edinburgh, U.K.,in 1995.

He is currently a Professor with Power EnergyDedicated Advanced Center (UMPEDAC), Univer-sity of Malaya, Kuala Lumpur, Malaysia, where he isalso the director of the centre. He has been appointedas an Adjunct Professor at King Abdulaziz Univer-sity, Jeddah, Saudi Arabia, till due date. His research

interests include power electronics, real-time control systems, and electricaldrives. He is a Fellow of the IET, U.K., and the Academy of Sciences Malaysia.

Wooi-Ping Hew (M’06) received the B.Eng. andMasters (electrical) degrees from the University ofTechnology, Johor Bahru, Malaysia. He received thePh.D. from the University of Malaya, Kuala Lumpur,Malaysia, in 2000.

He is currently a Professor in the Faculty ofEngineering, University of Malaya, Kuala Lumpur,Malaysia. He is a Member of IET and a Chartered En-gineer. His research interests include electrical drivesand electrical machine design.

Hang Seng Che received the B.Eng. degree in electri-cal engineering from the University of Malaya, KualaLumpur, Malaysia, in 2009. He then received thePh.D. degree under auspices of a dual Ph.D. pro-gramme between the University of Malaya and Liv-erpool John Moores University, Liverpool, U.K., in2013.

He is currently working as a Postdoctoral ResearchFellow at the Power Energy Dedicated AdvancedCenter, University of Malaya, Malaysia. His researchinterests include multiphase machines drives, fault

tolerant control, and renewable energy.Dr. Che was the recipient of the 2009 Kuok Foundation Postgraduate Schol-

arship Award for his Ph.D. study.

5358 IEEE TRANSACTIONS ON POWER …repository.um.edu.my/39889/1/Freddy Oct 2014.pdf · 5358 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 10, OCTOBER 2014 Comparison and Analysis

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